Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388571
A. Vaskova, M. Portela-García, C. López-Ongil, E. Sanchez, M. Sonza Reorda
The effects of permanent faults, arising along working life of digital electronic systems, may impact their reliability and performance. In-field test may help to detect these faults and to prevent serious effects in safety-critical applications. Distributed electronic systems introduce further complexity in this scenario, as the low observability and the lack of maintenance make difficult the detection as well as the identification of failing elements and their repairing. Functional workloads are often used for on-line tests of distributed systems to detect permanent faults. Suitable techniques for test generation and early identification of functionally untestable permanent faults are critical issues that are faced in this work.
{"title":"About the functional test of permanent faults in distributed systems","authors":"A. Vaskova, M. Portela-García, C. López-Ongil, E. Sanchez, M. Sonza Reorda","doi":"10.1109/DCIS.2015.7388571","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388571","url":null,"abstract":"The effects of permanent faults, arising along working life of digital electronic systems, may impact their reliability and performance. In-field test may help to detect these faults and to prevent serious effects in safety-critical applications. Distributed electronic systems introduce further complexity in this scenario, as the low observability and the lack of maintenance make difficult the detection as well as the identification of failing elements and their repairing. Functional workloads are often used for on-line tests of distributed systems to detect permanent faults. Suitable techniques for test generation and early identification of functionally untestable permanent faults are critical issues that are faced in this work.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125603491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388607
R. Madeira, N. Paulino
Switched capacitor (SC) DC-DC converters can be used to convert an input voltage range into a fixed output voltage value. The efficiency of these circuits depends on the ratio between the input and output voltages and on the parasitic capacitances of the circuit. Depending on the type of capacitor and how it is connected, the impact of the parasitic capacitances on the efficiency can vary. This paper presents an analysis of the efficiency of the 2:1 SC DC-DC converter as function of the power level and of the parasitic capacitances. This analysis shows that depending on the required power level, different types of capacitors should be used in order to maximize the efficiency of the converter.
{"title":"Improving the efficiency of a 2∶1 SC DC-DC converter using the parasitic capacitances","authors":"R. Madeira, N. Paulino","doi":"10.1109/DCIS.2015.7388607","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388607","url":null,"abstract":"Switched capacitor (SC) DC-DC converters can be used to convert an input voltage range into a fixed output voltage value. The efficiency of these circuits depends on the ratio between the input and output voltages and on the parasitic capacitances of the circuit. Depending on the type of capacitor and how it is connected, the impact of the parasitic capacitances on the efficiency can vary. This paper presents an analysis of the efficiency of the 2:1 SC DC-DC converter as function of the power level and of the parasitic capacitances. This analysis shows that depending on the required power level, different types of capacitors should be used in order to maximize the efficiency of the converter.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122387379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.17265/2328-2223/2016.03.002
Pablo Pérez-García, A. Maldonado, A. Yúfera, G. Huertas, A. Rueda, J. Huertas
In this paper are summarized some of the main contributions to BioImpedance (BI) parameter-based systems for medical, biological and industrial fields, oriented to develop micro laboratory systems. These small systems are enabled by the development of new measurement techniques and systems (labs), based on the impedance as biomarker. The electrical properties of the life mater allow the easy, cheap and usually non-invasive measurement methods to define its status or value, with the possibility to know its time evolution. In this work, it is proposed a review of bio-impedance based methods being employed to develop new Lab-on-a-Chips (LoC) systems, and some open problems identified as main research challenges, such us, the accuracy limits of measurements techniques, the role of the microelectrode-biological impedance modelling in measurements and system portability specifications demanded for many applications.
{"title":"Towards Bio-Impedance based labs: A review","authors":"Pablo Pérez-García, A. Maldonado, A. Yúfera, G. Huertas, A. Rueda, J. Huertas","doi":"10.17265/2328-2223/2016.03.002","DOIUrl":"https://doi.org/10.17265/2328-2223/2016.03.002","url":null,"abstract":"In this paper are summarized some of the main contributions to BioImpedance (BI) parameter-based systems for medical, biological and industrial fields, oriented to develop micro laboratory systems. These small systems are enabled by the development of new measurement techniques and systems (labs), based on the impedance as biomarker. The electrical properties of the life mater allow the easy, cheap and usually non-invasive measurement methods to define its status or value, with the possibility to know its time evolution. In this work, it is proposed a review of bio-impedance based methods being employed to develop new Lab-on-a-Chips (LoC) systems, and some open problems identified as main research challenges, such us, the accuracy limits of measurements techniques, the role of the microelectrode-biological impedance modelling in measurements and system portability specifications demanded for many applications.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122780951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388596
I. Dopido, C. Deniz, H. Fabelo, G. Callicó, S. López, R. Sarmiento, D. Bulters, E. Casselden, H. Bulstrode
Hyperspectral imaging is an active research field for remote sensing applications. These images provide a lot of information about the characteristics of the materials due to the high spectral resolution. This work is focused in the use of this kind of information to detect tumour tissue, particularly brain cancer tissue. In recent years, the study of this kind of tumour has been a challenging task due to the nature of these tissues. The neurosurgeon usually finds several problems to detect tumour tissues by the naked eye. In order to address this problem, this work makes use of high spectral resolution samples in the range from 400 nm to 6000 nm, provided by an Agilent Resolutions Pro V.5 spectrometer that has been diagnosed by histopathology. This instrument can sample a single pixel with a very high spectral resolution. The high spectral resolution allows a reliable separation between the different tissues in brain tumour. The proposed approach is based on a hierarchical decision tree. This approach is composed by several systems of Support Vector Machine classifiers. The 225 used samples come from 25 adults (males and females) and have been taken at different surgical procedures at the University Hospital of Southampton. The main goal is to discriminate between tumour tissue and normal tissue. Specifically, it assigns priority to the group of classes known a priori to the classification showed accordingly to the level of detail. The experimental results indicate that the use of the proposed new decision tree approach could be a solution to effectively discriminate between tumour and normal tissue and additionally provide information about the specific tissue for these classes. For our data set, a sensitivity of 100% and a specificity of 99.27% have been obtained when healthy and tumour samples are discriminated. These results clearly indicate that the use of high dimensionality spectral data is a promising and effective technique to indicate if a brain sample is or not affected by cancer with a high reliability.
高光谱成像是一个活跃的遥感应用研究领域。由于光谱分辨率高，这些图像提供了大量关于材料特性的信息。这项工作的重点是利用这类信息来检测肿瘤组织，特别是脑癌组织。近年来，由于这些组织的性质，对这类肿瘤的研究一直是一项具有挑战性的任务。神经外科医生通常通过肉眼发现几个问题来检测肿瘤组织。为了解决这个问题，这项工作利用了400 nm到6000 nm范围内的高光谱分辨率样品，由组织病理学诊断的安捷伦resolution Pro V.5光谱仪提供。这台仪器可以以非常高的光谱分辨率对单个像素进行采样。高光谱分辨率使得脑肿瘤中不同组织之间的分离可靠。所提出的方法基于分层决策树。该方法由多个支持向量机分类器系统组成。225个样本来自25个成年人(男性和女性)，并在南安普顿大学医院的不同外科手术中采集。主要目的是区分肿瘤组织和正常组织。具体来说，它将优先级分配给根据详细程度所显示的分类先验已知的类组。实验结果表明，使用所提出的新决策树方法可以有效地区分肿瘤和正常组织，并为这些类别提供有关特定组织的信息。对于我们的数据集，在区分健康样本和肿瘤样本时，获得了100%的灵敏度和99.27%的特异性。这些结果清楚地表明，使用高维光谱数据是一种有前途和有效的技术，可以高可靠性地表明大脑样本是否受到癌症的影响。
{"title":"Decision tree classification system for brain cancer detection using spectrographic samples","authors":"I. Dopido, C. Deniz, H. Fabelo, G. Callicó, S. López, R. Sarmiento, D. Bulters, E. Casselden, H. Bulstrode","doi":"10.1109/DCIS.2015.7388596","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388596","url":null,"abstract":"Hyperspectral imaging is an active research field for remote sensing applications. These images provide a lot of information about the characteristics of the materials due to the high spectral resolution. This work is focused in the use of this kind of information to detect tumour tissue, particularly brain cancer tissue. In recent years, the study of this kind of tumour has been a challenging task due to the nature of these tissues. The neurosurgeon usually finds several problems to detect tumour tissues by the naked eye. In order to address this problem, this work makes use of high spectral resolution samples in the range from 400 nm to 6000 nm, provided by an Agilent Resolutions Pro V.5 spectrometer that has been diagnosed by histopathology. This instrument can sample a single pixel with a very high spectral resolution. The high spectral resolution allows a reliable separation between the different tissues in brain tumour. The proposed approach is based on a hierarchical decision tree. This approach is composed by several systems of Support Vector Machine classifiers. The 225 used samples come from 25 adults (males and females) and have been taken at different surgical procedures at the University Hospital of Southampton. The main goal is to discriminate between tumour tissue and normal tissue. Specifically, it assigns priority to the group of classes known a priori to the classification showed accordingly to the level of detail. The experimental results indicate that the use of the proposed new decision tree approach could be a solution to effectively discriminate between tumour and normal tissue and additionally provide information about the specific tissue for these classes. For our data set, a sensitivity of 100% and a specificity of 99.27% have been obtained when healthy and tumour samples are discriminated. These results clearly indicate that the use of high dimensionality spectral data is a promising and effective technique to indicate if a brain sample is or not affected by cancer with a high reliability.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126286011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388587
S. S. Bhargav, Young H. Cho
Analog-to-digital (ADC) converters are the most direct and accurate method of power measurement. However it is impractical to instrument ADCs for large number of circuits in a digital system to measure power. In this paper, we present a high resolution digital power measurement technique that is scalable, uses lower power, and is less invasive than ADCs. The core concepts of this new technique has been demonstrated using an evaluation design on FPGA platform. Our latest design can simultaneously monitor 350 different instrumentation points on FPGA circuits and on-board components at 128 kS/sec for each point. The calculated total power differs from those acquired using low noise ADC by less than 3%. Furthermore, an offline data analysis indicates that our method is resilient to instrumentation errors and noise.
模数转换器(ADC)是最直接、最精确的功率测量方法。然而，对数字系统中大量电路的adc进行功率测量是不切实际的。在本文中，我们提出了一种高分辨率数字功率测量技术，该技术具有可扩展性，使用更低的功率，并且比adc的侵入性更小。该技术的核心概念已在FPGA平台上通过评估设计得到验证。我们的最新设计可以同时监控FPGA电路和板载组件上350个不同的仪表点，每个点的速度为128 k /秒。计算出的总功率与使用低噪声ADC获得的总功率相差不到3%。此外，离线数据分析表明，我们的方法对仪器误差和噪声具有弹性。
{"title":"Accurate power measurement technique for digital systems using independent component analysis","authors":"S. S. Bhargav, Young H. Cho","doi":"10.1109/DCIS.2015.7388587","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388587","url":null,"abstract":"Analog-to-digital (ADC) converters are the most direct and accurate method of power measurement. However it is impractical to instrument ADCs for large number of circuits in a digital system to measure power. In this paper, we present a high resolution digital power measurement technique that is scalable, uses lower power, and is less invasive than ADCs. The core concepts of this new technique has been demonstrated using an evaluation design on FPGA platform. Our latest design can simultaneously monitor 350 different instrumentation points on FPGA circuits and on-board components at 128 kS/sec for each point. The calculated total power differs from those acquired using low noise ADC by less than 3%. Furthermore, an offline data analysis indicates that our method is resilient to instrumentation errors and noise.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125263487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388608
Filipe Quendera, N. Paulino
This paper presents a low power low voltage temperature sensor designed in a 0.13 μm CMOS technology. The circuit consist of a bandgap voltage reference and a second order sigma-delta modulator. The circuit was designed to operate with a minimum power supply of 0.5 V. The voltage reference circuit operates from -50°C to 110°C with a temperature coefficient of 67.15 (ppm/°C) with a maximum power dissipation of 5.9μW. The bandgap circuit combined with the second order ΔΣ modulator dissipates 6.1μW to 11.7μW over a -30°C to 70°C range.
{"title":"A low voltage low power temperature sensor using a 2nd order delta-sigma modulator","authors":"Filipe Quendera, N. Paulino","doi":"10.1109/DCIS.2015.7388608","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388608","url":null,"abstract":"This paper presents a low power low voltage temperature sensor designed in a 0.13 μm CMOS technology. The circuit consist of a bandgap voltage reference and a second order sigma-delta modulator. The circuit was designed to operate with a minimum power supply of 0.5 V. The voltage reference circuit operates from -50°C to 110°C with a temperature coefficient of 67.15 (ppm/°C) with a maximum power dissipation of 5.9μW. The bandgap circuit combined with the second order ΔΣ modulator dissipates 6.1μW to 11.7μW over a -30°C to 70°C range.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125427025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388612
Y. Torroja, A. López, J. Portilla, T. Riesgo
In this paper, a serial port based debugging tool for the Arduino platform is presented. The tool is based on a modification of the Arduino IDE (Integrated Development Environment) and libraries. It includes the basic options of debugging tools (stepping, breakpoints, variable inspection, etc.) without the need of a hardware debugging interface. The tool has been designed taking into account that is going to be used by beginners or intermediate users, which is the most common profile among Arduino users. The tool tries to promote debugging procedures that are not based on trial and error, and contributes to the Arduino environment with another teaching resource.
{"title":"A serial port based debugging tool to improve learning with arduino","authors":"Y. Torroja, A. López, J. Portilla, T. Riesgo","doi":"10.1109/DCIS.2015.7388612","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388612","url":null,"abstract":"In this paper, a serial port based debugging tool for the Arduino platform is presented. The tool is based on a modification of the Arduino IDE (Integrated Development Environment) and libraries. It includes the basic options of debugging tools (stepping, breakpoints, variable inspection, etc.) without the need of a hardware debugging interface. The tool has been designed taking into account that is going to be used by beginners or intermediate users, which is the most common profile among Arduino users. The tool tries to promote debugging procedures that are not based on trial and error, and contributes to the Arduino environment with another teaching resource.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130258970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388605
M. Mashayekhi, S. Ogier, T. Pease, L. Terés, J. Carrabina
Process yield, variability and scalability have always been a critical issue for scaling-up circuits in printed electronics. The organic materials and fabrication process as well as physical layout design play a significant role in controlling the performance of Organic Thin Film Transistors (OTFT). In order to design a robust and reliable organic circuit, designers are interested in having stable and predictable OTFTs. In this work, we study the electrical characteristics of OTFTs and digital logic cells for different layout design styles, and provide the statistical analysis of their variability and scalability. Arrays of OTFTs and cells have been designed by using parameterized cells (PCells) and python scripts in order to facilitate design parameters sweep. Very high yield and uniform OTFTs have been fabricated with excellent electrical characteristics. Finally some ring oscillator circuits have been demonstrated as a proof of concept.
{"title":"Comparison of design styles for top-gate bottom-contact OTFTs","authors":"M. Mashayekhi, S. Ogier, T. Pease, L. Terés, J. Carrabina","doi":"10.1109/DCIS.2015.7388605","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388605","url":null,"abstract":"Process yield, variability and scalability have always been a critical issue for scaling-up circuits in printed electronics. The organic materials and fabrication process as well as physical layout design play a significant role in controlling the performance of Organic Thin Film Transistors (OTFT). In order to design a robust and reliable organic circuit, designers are interested in having stable and predictable OTFTs. In this work, we study the electrical characteristics of OTFTs and digital logic cells for different layout design styles, and provide the statistical analysis of their variability and scalability. Arrays of OTFTs and cells have been designed by using parameterized cells (PCells) and python scripts in order to facilitate design parameters sweep. Very high yield and uniform OTFTs have been fabricated with excellent electrical characteristics. Finally some ring oscillator circuits have been demonstrated as a proof of concept.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130066097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388562
O. Moldovan, F. Lime, B. Iñíguez
In this paper, we present the results of the implementation of a complete DC and AC Gate-All-Around (GAA) long-channel junctionless MOSFET model in Verilog-A code, which will be further used in commercial circuit simulators. The model in Verilog-A is integrated in the SmartSpice circuit simulator and tested in a CMOS inverter. Both p-channel and n-channel device models are validated. Also, the results are compared with data from 3D numerical simulations, showing a very good agreement in all transistors' operation regimes.
{"title":"A complete Verilog-A Gate-All-Around junctionless MOSFET model","authors":"O. Moldovan, F. Lime, B. Iñíguez","doi":"10.1109/DCIS.2015.7388562","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388562","url":null,"abstract":"In this paper, we present the results of the implementation of a complete DC and AC Gate-All-Around (GAA) long-channel junctionless MOSFET model in Verilog-A code, which will be further used in commercial circuit simulators. The model in Verilog-A is integrated in the SmartSpice circuit simulator and tested in a CMOS inverter. Both p-channel and n-channel device models are validated. Also, the results are compared with data from 3D numerical simulations, showing a very good agreement in all transistors' operation regimes.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122417079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388561
R. Akbar, I. Filanovsky, J. Jarvenhaara, N. Tchamov
The paper presents a self-oscillating DC-DC integrated converter which is operable in the frequency range of 200MHz-260MHz. The circuit includes a cascoded power stage, an integrated transformer, duty-cycle detector, and pulse shaper. The primary of the transformer provides the transmission of power to the converter load. The secondary, via detector and shaper, provides the feedback signal to the gates of cascoded transistors in the power stage. A detailed analysis of the converter operation is given. The conditions for a smooth start-up are indicated as well. The converter layout is provided. The circuit was designed and simulated in 45 nm CMOS technology, and the calculated operation parameters are compared with that of the extracted from layout converter.
{"title":"Operation and design of VHF self-oscillating DC-DC converter with integrated transformer","authors":"R. Akbar, I. Filanovsky, J. Jarvenhaara, N. Tchamov","doi":"10.1109/DCIS.2015.7388561","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388561","url":null,"abstract":"The paper presents a self-oscillating DC-DC integrated converter which is operable in the frequency range of 200MHz-260MHz. The circuit includes a cascoded power stage, an integrated transformer, duty-cycle detector, and pulse shaper. The primary of the transformer provides the transmission of power to the converter load. The secondary, via detector and shaper, provides the feedback signal to the gates of cascoded transistors in the power stage. A detailed analysis of the converter operation is given. The conditions for a smooth start-up are indicated as well. The converter layout is provided. The circuit was designed and simulated in 45 nm CMOS technology, and the calculated operation parameters are compared with that of the extracted from layout converter.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121320126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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