Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388597
H. Quintero, M. Avedillo, J. Núñez
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the non-inverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its non-inverting feature.
{"title":"Improving robustness of dynamic logic based pipelines","authors":"H. Quintero, M. Avedillo, J. Núñez","doi":"10.1109/DCIS.2015.7388597","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388597","url":null,"abstract":"Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that, in addition to the functional limitation associated to the non-inverting behavior of Domino gates, there are also robustness disadvantages when compared to inverting dynamic gates. We analyze and compare the tolerance to parameter and operating conditions variations of gate-level pipelines implemented with Domino and with DOE, an inverting dynamic gate we have recently proposed. Our experiments confirm that DOE pipelines are more robust and that improvements are due to its non-inverting feature.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129470494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388598
I. Kianpour, Bilal Hussain, V. Tavares, H. Mendonca
An integrate-and-fire modulator (IFM) is designed for power scavenging systems like: Wireless Sensor Network (WSN) and Radio Frequency Identification (RFID) sensor tags. The circuit works with a clock in order to be able to be synchronized with microprocessors, which must be used to reconstruct the signal. The modulator is simulated using 130nm CMOS technology and the resulting power consumption is around 14nW at a clock frequency of 10 kHz. The OTA individually dissipates roughly 13nW. Signal reconstruction resulted in a 9.2 ENOB.
{"title":"A low power clocked integrated-and-fire modulator for UWB applications","authors":"I. Kianpour, Bilal Hussain, V. Tavares, H. Mendonca","doi":"10.1109/DCIS.2015.7388598","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388598","url":null,"abstract":"An integrate-and-fire modulator (IFM) is designed for power scavenging systems like: Wireless Sensor Network (WSN) and Radio Frequency Identification (RFID) sensor tags. The circuit works with a clock in order to be able to be synchronized with microprocessors, which must be used to reconstruct the signal. The modulator is simulated using 130nm CMOS technology and the resulting power consumption is around 14nW at a clock frequency of 10 kHz. The OTA individually dissipates roughly 13nW. Signal reconstruction resulted in a 9.2 ENOB.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129533779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388581
M. Avedillo, J. Núñez
Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas.
{"title":"Assessing application areas for tunnel transistor technologies","authors":"M. Avedillo, J. Núñez","doi":"10.1109/DCIS.2015.7388581","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388581","url":null,"abstract":"Tunnel transistors are one of the most attractive steep subthreshold slope devices currently being investigated as a means of overcoming the power density and energy inefficiency limitations of CMOS technology. In this paper, projected tunnel transistor technologies are evaluated and compared to LP and HP versions of both conventional and FinFET CMOS in terms of their power and energy in different application areas.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130925593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388556
H. Pettenghi, L. Sousa, Jude Angelo Ambrose
This paper presents a novel approach to improve the existing Binary-to-RNS multi-moduli architectures (MMAs). These MMAs reduce the complexity by sharing common intermediate circuitry among various RNS moduli channels. Two types of MMAs are distinguished depending on whether the functionality is implemented in serial or parallel. An existing input pre-computation methodology, which improves the performance of the final MMA modular conversion of our approach herein first time used. Experimental results suggest that the proposed RNS design accelerates the execution, compensating the additional cost incurred in power and area. Moreover, the designs herein proposed have demonstrated energy reductions.
{"title":"Novel methodology to improve Multi-moduli architectures for Binary-to-RNS conversion","authors":"H. Pettenghi, L. Sousa, Jude Angelo Ambrose","doi":"10.1109/DCIS.2015.7388556","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388556","url":null,"abstract":"This paper presents a novel approach to improve the existing Binary-to-RNS multi-moduli architectures (MMAs). These MMAs reduce the complexity by sharing common intermediate circuitry among various RNS moduli channels. Two types of MMAs are distinguished depending on whether the functionality is implemented in serial or parallel. An existing input pre-computation methodology, which improves the performance of the final MMA modular conversion of our approach herein first time used. Experimental results suggest that the proposed RNS design accelerates the execution, compensating the additional cost incurred in power and area. Moreover, the designs herein proposed have demonstrated energy reductions.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123351731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388601
Gabriel Mujica, J. Portilla, T. Riesgo
The Internet of Things has emerged as one of the key aspects for the future of the Wireless Sensor Networks and their impact on new applications in real environments. This concept poses new challenges in the implementation, testing and debugging of efficient, robust and reliable technologies under this paradigm, specially in a pre-deployment stage where HW-SW platform prototypes are to be optimized prior to their inclusion in actual deployments. In this work, the design and implementation of a complete testbed infrastructure as a support tool for improving the effectiveness and the applicability of sensor nodes to real systems is presented, focused on the modular architecture of the Cookie platform and aiming to help developers to integrate and improve the whole WSN operation to final real-world scenarios.
{"title":"Testbed architecture and framework for debugging Wireless Sensor Networks","authors":"Gabriel Mujica, J. Portilla, T. Riesgo","doi":"10.1109/DCIS.2015.7388601","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388601","url":null,"abstract":"The Internet of Things has emerged as one of the key aspects for the future of the Wireless Sensor Networks and their impact on new applications in real environments. This concept poses new challenges in the implementation, testing and debugging of efficient, robust and reliable technologies under this paradigm, specially in a pre-deployment stage where HW-SW platform prototypes are to be optimized prior to their inclusion in actual deployments. In this work, the design and implementation of a complete testbed infrastructure as a support tool for improving the effectiveness and the applicability of sensor nodes to real systems is presented, focused on the modular architecture of the Cookie platform and aiming to help developers to integrate and improve the whole WSN operation to final real-world scenarios.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122893616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388589
L. Parrilla, Diego P. Morales, J. A. López-Villanueva, J. A. López-Ramos, J. Álvarez-Bermejo
Security in Wireless Sensor Networks (WSNs) is a major challenge for extending its applications. In this paper, a new protocol for key distribution in WSNs is proposed. The method, based on Elliptic Curve Cryptography, and named ECGDH-1, performs a double round key distribution, sharing a group key among the different nodes. For accelerating the scalar-point operations to be performed in each node, a hardware coprocessor with low power consumption, and 8-bit interface for sensor motes is proposed. The cryptographic processor, named ECCB163sens_bus8 allows completing a scalar-point multiplication in 240us operating at 8MHz, while consuming only 0.028mJ by operation when implemented in a Spartan 6 device.
{"title":"Hardware implementation of a new ECC key distribution protocol for securing Wireless Sensor Networks","authors":"L. Parrilla, Diego P. Morales, J. A. López-Villanueva, J. A. López-Ramos, J. Álvarez-Bermejo","doi":"10.1109/DCIS.2015.7388589","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388589","url":null,"abstract":"Security in Wireless Sensor Networks (WSNs) is a major challenge for extending its applications. In this paper, a new protocol for key distribution in WSNs is proposed. The method, based on Elliptic Curve Cryptography, and named ECGDH-1, performs a double round key distribution, sharing a group key among the different nodes. For accelerating the scalar-point operations to be performed in each node, a hardware coprocessor with low power consumption, and 8-bit interface for sensor motes is proposed. The cryptographic processor, named ECCB163sens_bus8 allows completing a scalar-point multiplication in 240us operating at 8MHz, while consuming only 0.028mJ by operation when implemented in a Spartan 6 device.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125429196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388558
J. Núñez, A. Ginés, E. Peralías, A. Rueda
High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (<; 200fs) are introduced and compared in a 0.18μm commercial CMOS process.
{"title":"Low-jitter differential clock driver circuits for high-performance high-resolution ADCs","authors":"J. Núñez, A. Ginés, E. Peralías, A. Rueda","doi":"10.1109/DCIS.2015.7388558","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388558","url":null,"abstract":"High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (<; 200fs) are introduced and compared in a 0.18μm commercial CMOS process.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121300011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388564
M. Silva Pereira, Joao E. N. Costa, M. Santos, J. Caldinhas Vaz
This paper presents a low-power and a low output voltage CMOS Bandgap Reference Generator topology with high PSRR and a novel temperature curvature compensation method. The proposed design was implemented in a standard 0.13 μm CMOS process. The main circuit is based in an opamp based β-multiplier bandgap circuit with resistive division. The compensation method cancels out up to 2nd order non-linear terms of the BJT voltage by using the MOSFET leakage current effect. The performance of the circuit was verified by post-layout simulations. Simulated results have shown temperature coefficients as low as -4.4 ppm/°C over a temperature range of 140°C (-40°C to 100°C). In addition the circuit demonstrated a PSSR of -100 dB at low frequencies and -73 dB at 1 MHz. The current consumption is 1.1 μA at 27°C.
{"title":"A 1.1 µA voltage reference circuit with high PSRR and temperature compensation","authors":"M. Silva Pereira, Joao E. N. Costa, M. Santos, J. Caldinhas Vaz","doi":"10.1109/DCIS.2015.7388564","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388564","url":null,"abstract":"This paper presents a low-power and a low output voltage CMOS Bandgap Reference Generator topology with high PSRR and a novel temperature curvature compensation method. The proposed design was implemented in a standard 0.13 μm CMOS process. The main circuit is based in an opamp based β-multiplier bandgap circuit with resistive division. The compensation method cancels out up to 2nd order non-linear terms of the BJT voltage by using the MOSFET leakage current effect. The performance of the circuit was verified by post-layout simulations. Simulated results have shown temperature coefficients as low as -4.4 ppm/°C over a temperature range of 140°C (-40°C to 100°C). In addition the circuit demonstrated a PSSR of -100 dB at low frequencies and -73 dB at 1 MHz. The current consumption is 1.1 μA at 27°C.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126048875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388579
M. Arenas, Adam Podhorski, S. Arrizabalaga, Jon Goya, B. Sedano, J. Mendizabal
This paper presents the implementation and validation of a complete AoA (Angle of Arrival) system. The AoA system is typically used together with smart antenna technology. In this paper the AoA system is part of a mobile wireless communication positioning system. The implementation includes the array antenna, the front ends and the AoA estimation block, which uses the MUSIC algorithm. Furthermore, a complete AoA system model has been developed, and used to find the optimum configuration of the AoA system. The AoA system has been validated using the model implemented in MATLAB.
{"title":"Implementation and validation of an Angle of Arrival (AOA) determination system","authors":"M. Arenas, Adam Podhorski, S. Arrizabalaga, Jon Goya, B. Sedano, J. Mendizabal","doi":"10.1109/DCIS.2015.7388579","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388579","url":null,"abstract":"This paper presents the implementation and validation of a complete AoA (Angle of Arrival) system. The AoA system is typically used together with smart antenna technology. In this paper the AoA system is part of a mobile wireless communication positioning system. The implementation includes the array antenna, the front ends and the AoA estimation block, which uses the MUSIC algorithm. Furthermore, a complete AoA system model has been developed, and used to find the optimum configuration of the AoA system. The AoA system has been validated using the model implemented in MATLAB.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124434197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/DCIS.2015.7388609
B. Jacinto, Marcelino B. Santos
This paper presents a fixed frequency Digital implementation of Sliding Mode Control (SMC) for an integrated DC-DC buck converter working in the Continuous Conduction Mode (CCM). The proposed solution uses a single Analog to Digital Converter (ADC) to monitor the error voltage and was designed for low power consumption. A non-linear, tracking, ADC is used and the digital control is event-based. The even based ADC and control allow the minimization of the power required for the operation of the control and improve the converter efficiency even for low output currents. The high performance of the proposed control is clear when compared with other digital and analog state of the art solutions.
{"title":"Digital Sliding Mode Control with non-linear ADC","authors":"B. Jacinto, Marcelino B. Santos","doi":"10.1109/DCIS.2015.7388609","DOIUrl":"https://doi.org/10.1109/DCIS.2015.7388609","url":null,"abstract":"This paper presents a fixed frequency Digital implementation of Sliding Mode Control (SMC) for an integrated DC-DC buck converter working in the Continuous Conduction Mode (CCM). The proposed solution uses a single Analog to Digital Converter (ADC) to monitor the error voltage and was designed for low power consumption. A non-linear, tracking, ADC is used and the digital control is event-based. The even based ADC and control allow the minimization of the power required for the operation of the control and improve the converter efficiency even for low output currents. The high performance of the proposed control is clear when compared with other digital and analog state of the art solutions.","PeriodicalId":191482,"journal":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","volume":"106-107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121486720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：