Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468275
A. Joy, A. Holden, T. Leslie, P. Saul
The potential using the emerging GaAlAs/GaAs heterojunction bipolar transistor (HJBT) technology is all-parallel analog-to-digital (A/D) converters is studied. To put into perspective the HJBT predictions made, a comparison of the ultimate performance levels achievable with contemporary silicon bipolar processes is given. Optimized latched compensators were developed for each technology and simulations on SPICE were carried out to determine the maximum sample rate and large-signal analog bandwidths that would be achieved. As both technologies are produced in-house, models were available for processors in the latter stages of development, namely the standard 1- mu m silicon bipolar process, and the 4- mu m HJBT process, as well as processes at an earlier stage of development, the enhanced 1- mu m silicon bipolar processes and the 2.5- mu m HJBT process. This enabled the trend of performance improvements with time to be compared. >
研究了利用新兴的GaAlAs/GaAs异质结双极晶体管(HJBT)技术实现全并行模数(A/D)转换器的潜力。为了把透视HJBT预测，最终性能水平可实现与当代硅双极工艺的比较给出。针对每种技术开发了优化的锁存补偿器，并在SPICE上进行了仿真，以确定将实现的最大采样率和大信号模拟带宽。由于这两种技术都是内部生产的，因此在后期开发阶段的处理器，即标准的1 μ m硅双极工艺和4 μ m HJBT工艺，以及在早期开发阶段的工艺，增强的1 μ m硅双极工艺和2.5 μ m HJBT工艺，都可以使用模型。这样就可以比较性能随时间的改进趋势。>
{"title":"A Comparison of GaAs HJBT and Silicon Bipolar Technologies For High Speed Analogue to Digital Converters","authors":"A. Joy, A. Holden, T. Leslie, P. Saul","doi":"10.1109/ESSCIRC.1988.5468275","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468275","url":null,"abstract":"The potential using the emerging GaAlAs/GaAs heterojunction bipolar transistor (HJBT) technology is all-parallel analog-to-digital (A/D) converters is studied. To put into perspective the HJBT predictions made, a comparison of the ultimate performance levels achievable with contemporary silicon bipolar processes is given. Optimized latched compensators were developed for each technology and simulations on SPICE were carried out to determine the maximum sample rate and large-signal analog bandwidths that would be achieved. As both technologies are produced in-house, models were available for processors in the latter stages of development, namely the standard 1- mu m silicon bipolar process, and the 4- mu m HJBT process, as well as processes at an earlier stage of development, the enhanced 1- mu m silicon bipolar processes and the 2.5- mu m HJBT process. This enabled the trend of performance improvements with time to be compared. >","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132041693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468446
J. Lammerts, C. Huizer, P. Hynes, M. Lecoutere
{"title":"A 60 MHz parameterizable program code storage element for D.S.P. applications","authors":"J. Lammerts, C. Huizer, P. Hynes, M. Lecoutere","doi":"10.1109/ESSCIRC.1988.5468446","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468446","url":null,"abstract":"","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124042984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468291
P. Saul, C. Powell, G. J. Gardiner, S. M. Jones
This paper describes a high speed driver circuit for GaAs MMIC R.F. switches. The device can switch a 4 pF load through 10 volts in less than 2 ns. A novel output circuit optimises power consumption. The circuit has been realised on the Plessey Three-Five standard production foundry process; circuit performance agrees well with SPICE predictions.
{"title":"A GaAs High Speed Driver Circuit for R.F. Switches","authors":"P. Saul, C. Powell, G. J. Gardiner, S. M. Jones","doi":"10.1109/ESSCIRC.1988.5468291","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468291","url":null,"abstract":"This paper describes a high speed driver circuit for GaAs MMIC R.F. switches. The device can switch a 4 pF load through 10 volts in less than 2 ns. A novel output circuit optimises power consumption. The circuit has been realised on the Plessey Three-Five standard production foundry process; circuit performance agrees well with SPICE predictions.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130801819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468391
W. Deguelle
Possibilities and limitations are considered of realizing integrated analog filters with cut off frequencies below 10 Hz. To arrive at an acceptable low chip-area, electronic multiplication is required to enhance the time-constant(s). It is recognized that for a given supply voltage electronic multiplication reduces the dynamic range because of noise-and DC-offset multiplication. As an example a 10 Hz low-pass filter has been successfully integrated on 0.4 sq. mm of chip area in a BICMOS process.
{"title":"Limitations on the Integration of Analog Filters for Frequencies Below 10 Hz","authors":"W. Deguelle","doi":"10.1109/ESSCIRC.1988.5468391","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468391","url":null,"abstract":"Possibilities and limitations are considered of realizing integrated analog filters with cut off frequencies below 10 Hz. To arrive at an acceptable low chip-area, electronic multiplication is required to enhance the time-constant(s). It is recognized that for a given supply voltage electronic multiplication reduces the dynamic range because of noise-and DC-offset multiplication. As an example a 10 Hz low-pass filter has been successfully integrated on 0.4 sq. mm of chip area in a BICMOS process.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130995167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468306
P. Saul, R. J. Killips, D. G. Taylor
The first attempt at an improved logic form was reported in reference 1. The circuit diagram is shown in figure 1. The chief attribute of this circuit is the use of a junction FET in place of a PNP transistor in an "I2L" - like configuration. This was first demonstrated on a 3-micron fast digital process which did not offer a PNP, but where it was desirable to have high packing density logic. Since this process featured "walled" emitters, it was a relatively easy task to provide an FET by running the emitter implant straight across a p-type resistor. This generates a device which could equally well be described as an FET or as a "pinch" resistor. Although not particularly fast on this process, due to the very low current and the saturation of the NPN transistor in the "on" state, very good power-delay products were recorded for the ring oscillators. This style of gate will be mentioned below in the context of the new process trials. With the advent of a 1-micron based bipolar technology, the requirement for a power efficient logic became more obvious, since the process has a capability for at least 20,000 gates per chip. It would in most cases be impractical on power dissipation grounds to run all these gates at full speed if there was no requirement in the circuit to do so.
{"title":"Low Power Logic for Micron and sub-Micron Bipolar Processes","authors":"P. Saul, R. J. Killips, D. G. Taylor","doi":"10.1109/ESSCIRC.1988.5468306","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468306","url":null,"abstract":"The first attempt at an improved logic form was reported in reference 1. The circuit diagram is shown in figure 1. The chief attribute of this circuit is the use of a junction FET in place of a PNP transistor in an \"I2L\" - like configuration. This was first demonstrated on a 3-micron fast digital process which did not offer a PNP, but where it was desirable to have high packing density logic. Since this process featured \"walled\" emitters, it was a relatively easy task to provide an FET by running the emitter implant straight across a p-type resistor. This generates a device which could equally well be described as an FET or as a \"pinch\" resistor. Although not particularly fast on this process, due to the very low current and the saturation of the NPN transistor in the \"on\" state, very good power-delay products were recorded for the ring oscillators. This style of gate will be mentioned below in the context of the new process trials. With the advent of a 1-micron based bipolar technology, the requirement for a power efficient logic became more obvious, since the process has a capability for at least 20,000 gates per chip. It would in most cases be impractical on power dissipation grounds to run all these gates at full speed if there was no requirement in the circuit to do so.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"387 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468322
P.J. Smith, P. Birdsall, C. Mallett
In many cases long haul optical fibre transmission systems will require buffer stores to reduce the effects of jitter. This paper describes a set of Gallium Arsenide buffer store components designed and manufactured using BTRL's standard digital process for operation at data rates of at least 2 Gbit/s.
{"title":"Gallium Arsenide Buffer Stores for Gbit/s Optical Fibre Transmission Systems","authors":"P.J. Smith, P. Birdsall, C. Mallett","doi":"10.1109/ESSCIRC.1988.5468322","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468322","url":null,"abstract":"In many cases long haul optical fibre transmission systems will require buffer stores to reduce the effects of jitter. This paper describes a set of Gallium Arsenide buffer store components designed and manufactured using BTRL's standard digital process for operation at data rates of at least 2 Gbit/s.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114076058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468432
D. Pedder
This paper reviews the growing interaction between the technologies employed to interconnect and package solid state circuits, the circuit design process and the performance of such circuits in a system or sub-system. The nature of this interaction is discussed at all levels of interconnection and packaging, and examples of new developments are cited which present exciting new opportunities to the circuit designer. Particular attention is given to the emerging Multichip Module Packaging concept, which offers a similar level of circuit complexity and integration to Wafer Scale Integration.
{"title":"Interconnection and Packaging of Solid State Circuits","authors":"D. Pedder","doi":"10.1109/ESSCIRC.1988.5468432","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468432","url":null,"abstract":"This paper reviews the growing interaction between the technologies employed to interconnect and package solid state circuits, the circuit design process and the performance of such circuits in a system or sub-system. The nature of this interaction is discussed at all levels of interconnection and packaging, and examples of new developments are cited which present exciting new opportunities to the circuit designer. Particular attention is given to the emerging Multichip Module Packaging concept, which offers a similar level of circuit complexity and integration to Wafer Scale Integration.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125977249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468251
G. Grocnewold
An eighth order, symmetrical bandpassfliter for IF-filtering purposes is constructed. The intermodulation free dynamic range (IMFDR) is maximized and amounts in theory to 58,5 dB with a single supply voltage of 8V and a total on chip capacitance of 80 pF. Fundamental constraints for the IMFDR are encountered. Some practical results are given to check the theoretical results.
{"title":"Integrated Selectivity for AM-Receivers","authors":"G. Grocnewold","doi":"10.1109/ESSCIRC.1988.5468251","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468251","url":null,"abstract":"An eighth order, symmetrical bandpassfliter for IF-filtering purposes is constructed. The intermodulation free dynamic range (IMFDR) is maximized and amounts in theory to 58,5 dB with a single supply voltage of 8V and a total on chip capacitance of 80 pF. Fundamental constraints for the IMFDR are encountered. Some practical results are given to check the theoretical results.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124908211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468311
A. Delaruelle
PIRAMID [1] is a design system sub-divided into 3 environments: a Synthesis Environment (SE), a Module Generation Environment (MGE), and a Floorplan Environment (FPE). Starting from a high-level language description of an algorithm, a dedicated signal processor is synthesised (SE). The building blocks of that processor are generated by instantiating a library of parametrised module generators (MGE). The layout of a processor is made by placing and routing the module instances in the floorplanning environment (FPE). PIRAMID is a silicon compiler designed to cover a range of applications for which the input data rate is relatively low in comparison with the system clock rate. Parallellism can be introduced within a processor and on processor level itself. Verification is done by simulation at different levels in the design traject. The syndrome generation algorithm, which is used in Compact Disc error correction algorithms, is an example of a number crunching calculation. It served as a first algorithm to be implemented using the PIRAMID design system.
{"title":"Design of a Syndrome Generator Chip using the Piramid Design System","authors":"A. Delaruelle","doi":"10.1109/ESSCIRC.1988.5468311","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468311","url":null,"abstract":"PIRAMID [1] is a design system sub-divided into 3 environments: a Synthesis Environment (SE), a Module Generation Environment (MGE), and a Floorplan Environment (FPE). Starting from a high-level language description of an algorithm, a dedicated signal processor is synthesised (SE). The building blocks of that processor are generated by instantiating a library of parametrised module generators (MGE). The layout of a processor is made by placing and routing the module instances in the floorplanning environment (FPE). PIRAMID is a silicon compiler designed to cover a range of applications for which the input data rate is relatively low in comparison with the system clock rate. Parallellism can be introduced within a processor and on processor level itself. Verification is done by simulation at different levels in the design traject. The syndrome generation algorithm, which is used in Compact Disc error correction algorithms, is an example of a number crunching calculation. It served as a first algorithm to be implemented using the PIRAMID design system.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125196836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468356
R. Costa, F. Curatelli, D. Caviglia, G. M. Bisio
A symbolic cell synthesizer is presented. It accepts a net-list as input and generates a design-rule independent symbolic layout (stick diagram). The user can specify topological constraints on pin and transistor positions, the maximum lengths of poly and diffusion wires, and a preferred layer for each electrical node. Cells are synthesized according to optimization criteria that include not only geometric factors, such as cell area and wire length, but also electrical performance, namely capacitance to the substrate and contact and via minimization.
{"title":"A Symbolic Cell Synthesizer for CMOS IC Design","authors":"R. Costa, F. Curatelli, D. Caviglia, G. M. Bisio","doi":"10.1109/ESSCIRC.1988.5468356","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468356","url":null,"abstract":"A symbolic cell synthesizer is presented. It accepts a net-list as input and generates a design-rule independent symbolic layout (stick diagram). The user can specify topological constraints on pin and transistor positions, the maximum lengths of poly and diffusion wires, and a preferred layer for each electrical node. Cells are synthesized according to optimization criteria that include not only geometric factors, such as cell area and wire length, but also electrical performance, namely capacitance to the substrate and contact and via minimization.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115460277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：