Pub Date : 1988-09-01DOI: 10.1109/esscirc.1988.5468342
P. Dorning
Structured linear functions have been developed that can be modified or replicated whilst maintaining their design validity. Adding compiled logic using advanced C.A.D. tools offers full-custom system design with minimal cost and minimal risk to the user.
{"title":"Structured Linear Functions for Compiled ASIC","authors":"P. Dorning","doi":"10.1109/esscirc.1988.5468342","DOIUrl":"https://doi.org/10.1109/esscirc.1988.5468342","url":null,"abstract":"Structured linear functions have been developed that can be modified or replicated whilst maintaining their design validity. Adding compiled logic using advanced C.A.D. tools offers full-custom system design with minimal cost and minimal risk to the user.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121838158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468326
F. Van Simaeys, J. Adams, D. Rabaey
The S-Interface chip (SIC) is a transceiver circuit able to interface voice/data communication equipment to the 4-wire CCITT S-bus. The device can be configured to operate either in TE (Terminal Equipment), NT (Network Termination) or as a PABX line card device. The 5-volt 22-pin chip is implemented in a 2¿m-CM0S technology. Power consumption is less than 60 mW in active operation and 5 mW in power down mode.
{"title":"An ISDN S-Interface Transceiver for Public and Private Digital Loops","authors":"F. Van Simaeys, J. Adams, D. Rabaey","doi":"10.1109/ESSCIRC.1988.5468326","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468326","url":null,"abstract":"The S-Interface chip (SIC) is a transceiver circuit able to interface voice/data communication equipment to the 4-wire CCITT S-bus. The device can be configured to operate either in TE (Terminal Equipment), NT (Network Termination) or as a PABX line card device. The 5-volt 22-pin chip is implemented in a 2¿m-CM0S technology. Power consumption is less than 60 mW in active operation and 5 mW in power down mode.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"76 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126032908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468412
P. Boutigny, Huy Anh Nguyen, Denis Raoulx
The design and measurement of analog comparators and switch matrix for 8-channel 1GHz acquisition systems are reported. Built with a full-custom GaAs IC, it achieves 1GHz acquisition rate with only 500mW power consumption. The measured input sensitivity is lOmV and the minimum input pulse capture is Ins.
{"title":"1GHz Analog Comparator and Switch Matrix for 8-Channel Analog Data Acquisition System","authors":"P. Boutigny, Huy Anh Nguyen, Denis Raoulx","doi":"10.1109/ESSCIRC.1988.5468412","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468412","url":null,"abstract":"The design and measurement of analog comparators and switch matrix for 8-channel 1GHz acquisition systems are reported. Built with a full-custom GaAs IC, it achieves 1GHz acquisition rate with only 500mW power consumption. The measured input sensitivity is lOmV and the minimum input pulse capture is Ins.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115372513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468397
A. Cremonesi, F. Maloberti, G. Polito
A 6 bit weighted-current-sink video DAC with full scale settling time smaller than 10 nsec, integrated with a double metal 3¿m CMOS technology, is described. Current source matching and differential switch driving aspects are considered.
{"title":"A 100 MHz CMOS DAC Converter for Video-Graphic Systems","authors":"A. Cremonesi, F. Maloberti, G. Polito","doi":"10.1109/ESSCIRC.1988.5468397","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468397","url":null,"abstract":"A 6 bit weighted-current-sink video DAC with full scale settling time smaller than 10 nsec, integrated with a double metal 3¿m CMOS technology, is described. Current source matching and differential switch driving aspects are considered.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114822101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/esscirc.1988.5468302
B. Murari
It is argued that thanks to the development of new power technologies, the separate paths taken by power semiconductors and small signal ICs are converging onto a single discipline: smart power. Integrating high power and high voltage devices plus control circuits on a single chip, smart power ICs bring substantial reduction in cost and enhanced reliability. Moreover, they render feasible solutions that would have been too costly when realized with conventional components. Several different technological approaches to smart power have been explored, but all such technologies share the same basic concept of merging different stcuctures on the same chip, taking advantage of the similarities in processing techniques. Smart power technologies can be classified in a number of ways, the first of which is the isolation technique used: dielectric, junction or self isolation. A further way to classify smart power processes regards the current flow in the power devices. Another fundamental distinction between smart power processes is the nature of the power elements. Two options are available: bipolar and DMOS. Smart power devices can also be divided into single-chip types and single package types.
{"title":"Smart power","authors":"B. Murari","doi":"10.1109/esscirc.1988.5468302","DOIUrl":"https://doi.org/10.1109/esscirc.1988.5468302","url":null,"abstract":"It is argued that thanks to the development of new power technologies, the separate paths taken by power semiconductors and small signal ICs are converging onto a single discipline: smart power. Integrating high power and high voltage devices plus control circuits on a single chip, smart power ICs bring substantial reduction in cost and enhanced reliability. Moreover, they render feasible solutions that would have been too costly when realized with conventional components. Several different technological approaches to smart power have been explored, but all such technologies share the same basic concept of merging different stcuctures on the same chip, taking advantage of the similarities in processing techniques. Smart power technologies can be classified in a number of ways, the first of which is the isolation technique used: dielectric, junction or self isolation. A further way to classify smart power processes regards the current flow in the power devices. Another fundamental distinction between smart power processes is the nature of the power elements. Two options are available: bipolar and DMOS. Smart power devices can also be divided into single-chip types and single package types.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123999517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468425
G. McGonigal, M. Elmasry
A three-dimensional (3D) implementation of the double-lambda-diode SRAM cell is proposed. It is shown that this cell provides greater noise immunity, but requires approximately the same area, as the conventional resistive-load cell.
{"title":"3D Double-Lambda-Diode VLSI SRAM Cells","authors":"G. McGonigal, M. Elmasry","doi":"10.1109/ESSCIRC.1988.5468425","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468425","url":null,"abstract":"A three-dimensional (3D) implementation of the double-lambda-diode SRAM cell is proposed. It is shown that this cell provides greater noise immunity, but requires approximately the same area, as the conventional resistive-load cell.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134039677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/esscirc.1988.5468332
Jesus Pena, Femin Calvo
The IARL is a single VLSI I.C. which does interface between different Modules (minimun growing unit in the System) and the Local Network, allowing direct connectivity or through an Interconnection Network. The I.C. switches between an internal PCM link inside a Module and two PCM links of the Local Network, at a rate of 2.048 Mhz. It also does packet switching using two statistical links, at a frequency of 2.048 Mhz The IARL operates at a frequency of 8.192 Mhz and is implemented with 26000 MOS gates 890000 transistors, 512 × 9 bits of ROM memory and 1632 bits of RAM memory. The I.C. is fabricated in 1.25 microns twin-tub CMOS technology and has dimensions of 370 mils × 380 mils, with nominal power dissipation of 0.5 Watts.
{"title":"Local Nework Access Interface (IARL)","authors":"Jesus Pena, Femin Calvo","doi":"10.1109/esscirc.1988.5468332","DOIUrl":"https://doi.org/10.1109/esscirc.1988.5468332","url":null,"abstract":"The IARL is a single VLSI I.C. which does interface between different Modules (minimun growing unit in the System) and the Local Network, allowing direct connectivity or through an Interconnection Network. The I.C. switches between an internal PCM link inside a Module and two PCM links of the Local Network, at a rate of 2.048 Mhz. It also does packet switching using two statistical links, at a frequency of 2.048 Mhz The IARL operates at a frequency of 8.192 Mhz and is implemented with 26000 MOS gates 890000 transistors, 512 × 9 bits of ROM memory and 1632 bits of RAM memory. The I.C. is fabricated in 1.25 microns twin-tub CMOS technology and has dimensions of 370 mils × 380 mils, with nominal power dissipation of 0.5 Watts.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129089294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468252
P. Frith
A CMOS integrated circuit performing all the necessary analogue signal processing for TACS and NMT cellular telephones is described. Voiceband filtering for transmit and receive signal paths, receive and transmit data filtering, microphone and loudspeaker amplifiers, and expander and compressor functions are all provided on one 7mm × 7mm integrated circuit. The triode transconductor technique used to implement the continuous time filters and non-linear circuits is discussed, and measured results taken from prototype devices are presented.
{"title":"Audio Processor Integrated Circuit for Cellular Radios","authors":"P. Frith","doi":"10.1109/ESSCIRC.1988.5468252","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468252","url":null,"abstract":"A CMOS integrated circuit performing all the necessary analogue signal processing for TACS and NMT cellular telephones is described. Voiceband filtering for transmit and receive signal paths, receive and transmit data filtering, microphone and loudspeaker amplifiers, and expander and compressor functions are all provided on one 7mm × 7mm integrated circuit. The triode transconductor technique used to implement the continuous time filters and non-linear circuits is discussed, and measured results taken from prototype devices are presented.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129000985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468282
X. Arreguit, E. Vittoz
The residual gate effect on the lateral collector current of compatible lateral bipolar transistors is modelled and a novel method for biasing the gate is presented. It is shown that this effect can be used to compensate transistors mismatch in order to enhance the precision of analog CMOS circuits by a factor of 5-10 over a temperature range of 100°K.
{"title":"Performance Enhancement of Compatible Lateral Bipolar Transistors for High-Precision CMOS Analog Design","authors":"X. Arreguit, E. Vittoz","doi":"10.1109/ESSCIRC.1988.5468282","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468282","url":null,"abstract":"The residual gate effect on the lateral collector current of compatible lateral bipolar transistors is modelled and a novel method for biasing the gate is presented. It is shown that this effect can be used to compensate transistors mismatch in order to enhance the precision of analog CMOS circuits by a factor of 5-10 over a temperature range of 100°K.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116295641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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