Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468472
R. Deubert
{"title":"The Mega-Technology, the Driving Force for Digital Signal Processing in Consumer Products","authors":"R. Deubert","doi":"10.1109/ESSCIRC.1988.5468472","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468472","url":null,"abstract":"","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133258296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468433
Qiu Yulin
A new CAM cell has been presented. The cell consists of only 6 MOS transistors and the size of it can be comparable to full CMOS SRAM cell. It can work either statically or dynamically. Hence, it provides a possibility to develop high density CAM chip.
{"title":"Six Most CAM Cell For High Density Array","authors":"Qiu Yulin","doi":"10.1109/ESSCIRC.1988.5468433","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468433","url":null,"abstract":"A new CAM cell has been presented. The cell consists of only 6 MOS transistors and the size of it can be comparable to full CMOS SRAM cell. It can work either statically or dynamically. Hence, it provides a possibility to develop high density CAM chip.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129684342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A single chip system (figure 1) capable of encryption using the Rivest, Shamir and Adleman (RSA) algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 micron technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.
{"title":"A Single Chip Public Key Encryption Sub-System","authors":"P. Ivey, A. Cox, J. Harbridge, J. Oldfield","doi":"10.1109/4.34094","DOIUrl":"https://doi.org/10.1109/4.34094","url":null,"abstract":"A single chip system (figure 1) capable of encryption using the Rivest, Shamir and Adleman (RSA) algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 micron technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131021045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468454
R. Cottrell
Programmable nibble-serial processors are an efficient means of implementation for signal processing algorithms involving the solution of difference equations. The architecture is based on a simple processing element, known as a Signal Processing Element (SPE), of which many could be fabricated on a single VLSI chip. This paper discusses the design of an instruction set for such an SPE, considering in particular the effects of data memory size, and the use of special purpose registers.
{"title":"Instruction Set Design for a Nibble-Serial Signal Processing Element","authors":"R. Cottrell","doi":"10.1109/ESSCIRC.1988.5468454","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468454","url":null,"abstract":"Programmable nibble-serial processors are an efficient means of implementation for signal processing algorithms involving the solution of difference equations. The architecture is based on a simple processing element, known as a Signal Processing Element (SPE), of which many could be fabricated on a single VLSI chip. This paper discusses the design of an instruction set for such an SPE, considering in particular the effects of data memory size, and the use of special purpose registers.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123671344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468286
W. Heimsch, R. Krebs, K. Ziemann, D. Moebus
In this work the driveability of CMOS and BICMOS NOR decoders are investigated. An optimization procedure is used to find out the ideal dimension of the transistors in order to get maximum circuit speed. The BICMOS version shows higher speed even at low capacitive loads and its area consumption nearly remains constant even at high capacitive loads. For a load capacity of 3pF a maximal factor 2 of speed improvement for BICMOS is archieved covering the same area as the appropriate CMOS one. For high capacitive loads (50pF) the BICMOS speed improvement is reduced (factor 1.1), but there is still an advantage of area conservation (factor 7.5).
{"title":"Comparing CMOS And BICMOS NOR Decoder Structures Using A Monte Carlo Optimization Tool","authors":"W. Heimsch, R. Krebs, K. Ziemann, D. Moebus","doi":"10.1109/ESSCIRC.1988.5468286","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468286","url":null,"abstract":"In this work the driveability of CMOS and BICMOS NOR decoders are investigated. An optimization procedure is used to find out the ideal dimension of the transistors in order to get maximum circuit speed. The BICMOS version shows higher speed even at low capacitive loads and its area consumption nearly remains constant even at high capacitive loads. For a load capacity of 3pF a maximal factor 2 of speed improvement for BICMOS is archieved covering the same area as the appropriate CMOS one. For high capacitive loads (50pF) the BICMOS speed improvement is reduced (factor 1.1), but there is still an advantage of area conservation (factor 7.5).","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123823757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468468
R. Wolffenbuttel
Conventional Successive Approximation AD converters consist of a clearly distinguishable DA converter, usually based on a R-2R resistor ladder, in a feedback loop for providing the analog counterpart of the SA register content to the input comparator. In successive conversion steps a refining of the SA register estimate of the input voltage is realised. Starting from the MSB the lesser significant bits are determined after setting of the previous bit in the SA register and comparison of the DA converter output with the actual input voltage. The conversion accuracy is largely determined by the matching of precision components in the DA converter. For this reason the properties of a translinear core are usually not taken into consideration. Nevertheless, such a circuit reveals interesting features for reducing the total circuit complexity of the AD converter, which would allow the circuit to be realised in a bipolar process with conservative design rules instead of a CMOS process. This is an interesting property in smart sensors where process compatibilty with the sensor process is essential, whereas only a moderate resolution is required. In the novel approach presented, a translinear core is employed to serve as both the comparator and the DA converter.
{"title":"Successive Approximation AD Converter using kT/q as an Intermediate","authors":"R. Wolffenbuttel","doi":"10.1109/ESSCIRC.1988.5468468","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468468","url":null,"abstract":"Conventional Successive Approximation AD converters consist of a clearly distinguishable DA converter, usually based on a R-2R resistor ladder, in a feedback loop for providing the analog counterpart of the SA register content to the input comparator. In successive conversion steps a refining of the SA register estimate of the input voltage is realised. Starting from the MSB the lesser significant bits are determined after setting of the previous bit in the SA register and comparison of the DA converter output with the actual input voltage. The conversion accuracy is largely determined by the matching of precision components in the DA converter. For this reason the properties of a translinear core are usually not taken into consideration. Nevertheless, such a circuit reveals interesting features for reducing the total circuit complexity of the AD converter, which would allow the circuit to be realised in a bipolar process with conservative design rules instead of a CMOS process. This is an interesting property in smart sensors where process compatibilty with the sensor process is essential, whereas only a moderate resolution is required. In the novel approach presented, a translinear core is employed to serve as both the comparator and the DA converter.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114845311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468357
C. Meixenberger, B. Goffart, M. Pierre, M. Degrauwe
Basic sizing routines of a synthesis program for MOS analog circuits [1] are presented. A class of routines is given that allows the design of single components as well as basic analog structures for a large domain of operating conditions. These routines can have any of their characteristics imposed as input parameters or output variables. Moreover, a general valid routine useful to size circuits according to 1/f noise, offset and gain specifications is given.
{"title":"Sizing Algorithms for Linear Analog Circuits","authors":"C. Meixenberger, B. Goffart, M. Pierre, M. Degrauwe","doi":"10.1109/ESSCIRC.1988.5468357","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468357","url":null,"abstract":"Basic sizing routines of a synthesis program for MOS analog circuits [1] are presented. A class of routines is given that allows the design of single components as well as basic analog structures for a large domain of operating conditions. These routines can have any of their characteristics imposed as input parameters or output variables. Moreover, a general valid routine useful to size circuits according to 1/f noise, offset and gain specifications is given.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116976534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468366
W. Buttler, B. Hosticka, G. Lutz
Two readout systems for silicon strip detectors (128-and 64-channels) have has been developed in CMOS technology. The readout systems have been designed for a readout pitch of 50¿m and 100¿m, respectively. They provide signal amplification, noise filtering, parallel storage, and serial readout and contain a digital contol for analog switching. Switched-capacitor filters are used in all channels for noise reduction by multi-correlated double sampling. Power consumption is controlled by an external reference voltage thus allowing for optimization of speed and noise behavior versus power consumption for individual use in experiments. Power-down mode for further reduction of power dissipation is available without switching off the supply voltages. A high charge amplification (15mV/fC) and a good noise performance (335 ENC + 30 ENC/pF) have been obtained at a very low power consumption of 2mW per channel.
{"title":"Low Noise - Low Power CMOS Readout Systems for Silicon Strip Detectors","authors":"W. Buttler, B. Hosticka, G. Lutz","doi":"10.1109/ESSCIRC.1988.5468366","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468366","url":null,"abstract":"Two readout systems for silicon strip detectors (128-and 64-channels) have has been developed in CMOS technology. The readout systems have been designed for a readout pitch of 50¿m and 100¿m, respectively. They provide signal amplification, noise filtering, parallel storage, and serial readout and contain a digital contol for analog switching. Switched-capacitor filters are used in all channels for noise reduction by multi-correlated double sampling. Power consumption is controlled by an external reference voltage thus allowing for optimization of speed and noise behavior versus power consumption for individual use in experiments. Power-down mode for further reduction of power dissipation is available without switching off the supply voltages. A high charge amplification (15mV/fC) and a good noise performance (335 ENC + 30 ENC/pF) have been obtained at a very low power consumption of 2mW per channel.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129772769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468411
A. Dubois, M. Le Paih, P. Martin, C. Guiberteau, M. Gloanec, S. Maclman, O. Carl
The sample and hold (S/H) function is an unavoidable building block for high speed analog to digital conversion (ADC) systems. Two types of S/Hs have been developed based on MESFET and diode bridge switches. The diode bridge version features 6 bit-linearity, 0.8 ns ocquisition time at 0.5 Gsps under Nyquist operating conditions. It constitutes the highest performance available catalog product.
{"title":"A 6 Bit-0.5 GHz Full Nyquist GaAs Sample and Hold","authors":"A. Dubois, M. Le Paih, P. Martin, C. Guiberteau, M. Gloanec, S. Maclman, O. Carl","doi":"10.1109/ESSCIRC.1988.5468411","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468411","url":null,"abstract":"The sample and hold (S/H) function is an unavoidable building block for high speed analog to digital conversion (ADC) systems. Two types of S/Hs have been developed based on MESFET and diode bridge switches. The diode bridge version features 6 bit-linearity, 0.8 ns ocquisition time at 0.5 Gsps under Nyquist operating conditions. It constitutes the highest performance available catalog product.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"30 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132679811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-09-01DOI: 10.1109/ESSCIRC.1988.5468377
H. Wallinga
Design choices in CMOS analog signal processing circuits are presented. Special attention is focussed on continuous-time filter technologies. The basics of MOSFET-C continuous-time filters and CMOS Square Law Circuits are explained at the hand of a graphical MOST characteristics representation.
{"title":"CMOS Circuits for Analog Signal Processing","authors":"H. Wallinga","doi":"10.1109/ESSCIRC.1988.5468377","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1988.5468377","url":null,"abstract":"Design choices in CMOS analog signal processing circuits are presented. Special attention is focussed on continuous-time filter technologies. The basics of MOSFET-C continuous-time filters and CMOS Square Law Circuits are explained at the hand of a graphical MOST characteristics representation.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131228816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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