Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866177
Z. Z. Yu, T. Harvey
The CompactPCI standard was developed originally by Ziatech. It provides a way to combine the performance and the low cost of the PCI (Peripheral Component Interconnection) standard with a small, rugged computer form factor ideal for embedded applications. It functions as a 6U CompactPCI peripheral processor in a CompactPCI multiprocessing system (CompactPCI/MP), and operates in a peripheral slot, while the system CPU master operates in the system slot. The ZT 5540 is an ideal solution for telecommunication applications, such as pre-processor or protocol converter functions. The board occupies one or two CompactPCI slots depending on the configuration. A 14-watt processor module for the CompactPCI needs a proper thermal management solution under its thermal specifications. The challenge of the thermal management solution includes both thermal and mechanical design. Heat pipes are passive devices with high reliability and low cost. They have been widely used in electronic cooling. Transferring the heat load from the heat source to another location where the space is available for the heat sink is one of the major advantages of the heat pipe. With the special features of the heat pipe, both thermal and mechanical challenges of the thermal management solution can be achieved. The thermal analysis on the design is presented and subsequently verified by the test data.
{"title":"The precision-engineered heat pipe for cooling Pentium II in CompactPCI design","authors":"Z. Z. Yu, T. Harvey","doi":"10.1109/ITHERM.2000.866177","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866177","url":null,"abstract":"The CompactPCI standard was developed originally by Ziatech. It provides a way to combine the performance and the low cost of the PCI (Peripheral Component Interconnection) standard with a small, rugged computer form factor ideal for embedded applications. It functions as a 6U CompactPCI peripheral processor in a CompactPCI multiprocessing system (CompactPCI/MP), and operates in a peripheral slot, while the system CPU master operates in the system slot. The ZT 5540 is an ideal solution for telecommunication applications, such as pre-processor or protocol converter functions. The board occupies one or two CompactPCI slots depending on the configuration. A 14-watt processor module for the CompactPCI needs a proper thermal management solution under its thermal specifications. The challenge of the thermal management solution includes both thermal and mechanical design. Heat pipes are passive devices with high reliability and low cost. They have been widely used in electronic cooling. Transferring the heat load from the heat source to another location where the space is available for the heat sink is one of the major advantages of the heat pipe. With the special features of the heat pipe, both thermal and mechanical challenges of the thermal management solution can be achieved. The thermal analysis on the design is presented and subsequently verified by the test data.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126828598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866829
A. Aranyosi, A. Ortega, J. Evans, T. Tarter, J. Pursel, J. Radhakrishnan
A methodology for creating compact thermal models of a single-chip CPGA package was developed and rigorously evaluated. Detailed package thermal models were exposed to a set of "hard" boundary conditions representing directional cooling scenarios. Studies were performed to compare the predicted temperature distributions in the package first when the metallic/ceramic sub-layers of the substrate and each pin in the array were individually modeled and secondly by combining the sub-layers as well as the pins and interstitial air into smeared layers. The smeared layer approach was found to be quite reasonable The detailed model was experimentally validated using a novel apparatus that allowed imposing temperature boundary conditions on the pin grid array and on the other surfaces, one at a time. Thermal response data were generated with the experimentally validated detailed model for a set of eight boundary conditions that were derived from a design of experiments approach using the minimum and maximum values of average heat transfer prevailing on the package external surfaces. Compact models of three different network topologies were generated utilizing a nonlinear programming algorithm. The simplest, five-resistor star-shaped network was unable to capture either the junction temperatures or the heat flows leaving the prime lumped areas within the required accuracy. Shunted networks with and without a floating node were also optimized, both topologies yielding good accuracy for both the junction temperatures and heat flows.
{"title":"Development of compact thermal models for advanced electronic packaging: methodology and experimental validation for a single-chip CPGA package","authors":"A. Aranyosi, A. Ortega, J. Evans, T. Tarter, J. Pursel, J. Radhakrishnan","doi":"10.1109/ITHERM.2000.866829","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866829","url":null,"abstract":"A methodology for creating compact thermal models of a single-chip CPGA package was developed and rigorously evaluated. Detailed package thermal models were exposed to a set of \"hard\" boundary conditions representing directional cooling scenarios. Studies were performed to compare the predicted temperature distributions in the package first when the metallic/ceramic sub-layers of the substrate and each pin in the array were individually modeled and secondly by combining the sub-layers as well as the pins and interstitial air into smeared layers. The smeared layer approach was found to be quite reasonable The detailed model was experimentally validated using a novel apparatus that allowed imposing temperature boundary conditions on the pin grid array and on the other surfaces, one at a time. Thermal response data were generated with the experimentally validated detailed model for a set of eight boundary conditions that were derived from a design of experiments approach using the minimum and maximum values of average heat transfer prevailing on the package external surfaces. Compact models of three different network topologies were generated utilizing a nonlinear programming algorithm. The simplest, five-resistor star-shaped network was unable to capture either the junction temperatures or the heat flows leaving the prime lumped areas within the required accuracy. Shunted networks with and without a floating node were also optimized, both topologies yielding good accuracy for both the junction temperatures and heat flows.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126390945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866174
D. Wheeler, C. Bailey
This paper describes modelling technology and its use in providing data governing the assembly of flip-chip components. Details are given on the reflow and curing stages as well as the prediction of solder joint shapes. The reflow process involves the attachment of a die to a board via solder joints. After a reflow process, underfill material is placed between the die and the substrate where it is heated and cured. Upon cooling the thermal mismatch between the die, underfill, solder bumps, and substrate will result in a nonuniform deformation profile across the assembly and hence stress. Shape predictions then thermal solidification and stress prediction are undertaken on solder joints during the reflow process. Both thermal and stress calculations are undertaken to predict phenomena occurring during the curing of the underfill material. These stresses may result in delamination between the underfill and its surrounding materials leading to a subsequent reduction in component performance and lifetime. Comparisons between simulations and experiments for die curvature will be given for the reflow and curing process.
{"title":"Modelling technology to predict flip-chip assembly","authors":"D. Wheeler, C. Bailey","doi":"10.1109/ITHERM.2000.866174","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866174","url":null,"abstract":"This paper describes modelling technology and its use in providing data governing the assembly of flip-chip components. Details are given on the reflow and curing stages as well as the prediction of solder joint shapes. The reflow process involves the attachment of a die to a board via solder joints. After a reflow process, underfill material is placed between the die and the substrate where it is heated and cured. Upon cooling the thermal mismatch between the die, underfill, solder bumps, and substrate will result in a nonuniform deformation profile across the assembly and hence stress. Shape predictions then thermal solidification and stress prediction are undertaken on solder joints during the reflow process. Both thermal and stress calculations are undertaken to predict phenomena occurring during the curing of the underfill material. These stresses may result in delamination between the underfill and its surrounding materials leading to a subsequent reduction in component performance and lifetime. Comparisons between simulations and experiments for die curvature will be given for the reflow and curing process.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121910728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866842
T. M. Ying, K. Toh
The electronic package structure often comprises of materials that occur in thin layers. In many instances, these materials are lumped. Together as a simplified compact model to represent their thermal performance enabling parametric studies of the package structure. This new compact structure will have a new set of thermal properties that differs from its constituent components. Their combined material properties often display anisotropic thermal conductivity because layers of conductive and less conductive materials results in an orthogonal heat transfer behavior. This paper addresses the analytical and numerical studies of heat spreading in an anisotropic conductivity material with particular reference to the printed circuit boards (PCB). The PCB is considered to be a single material with highly anisotropic thermal conductivity, depending on the distribution of copper planes and thermal vias. The motivation for this study is to determine an appropriate anisotropic spreading resistance formulation that can be used in compact models of electronic packages.
{"title":"A heat spreading resistance model for anisotropic thermal conductivity materials in electronic packaging","authors":"T. M. Ying, K. Toh","doi":"10.1109/ITHERM.2000.866842","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866842","url":null,"abstract":"The electronic package structure often comprises of materials that occur in thin layers. In many instances, these materials are lumped. Together as a simplified compact model to represent their thermal performance enabling parametric studies of the package structure. This new compact structure will have a new set of thermal properties that differs from its constituent components. Their combined material properties often display anisotropic thermal conductivity because layers of conductive and less conductive materials results in an orthogonal heat transfer behavior. This paper addresses the analytical and numerical studies of heat spreading in an anisotropic conductivity material with particular reference to the printed circuit boards (PCB). The PCB is considered to be a single material with highly anisotropic thermal conductivity, depending on the distribution of copper planes and thermal vias. The motivation for this study is to determine an appropriate anisotropic spreading resistance formulation that can be used in compact models of electronic packages.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123604260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866816
A. Mirza
This paper reviews the essential MEMS (Microelectromechanical Systems) silicon wafer processes that are needed for wafer-level packaging. Precision aligned wafer bonding is the key enabling technology for high-volume, low cost packaging of MEMS devices. State-of-the-art aligned silicon wafer bonding can provide not only basic MEMS device functionality, but also first-level assembly or packaging solutions for many MEMS devices. Numerous examples of high-volume production applications for wafer-level bonding will be described.
{"title":"Wafer-level packaging technology for MEMS","authors":"A. Mirza","doi":"10.1109/ITHERM.2000.866816","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866816","url":null,"abstract":"This paper reviews the essential MEMS (Microelectromechanical Systems) silicon wafer processes that are needed for wafer-level packaging. Precision aligned wafer bonding is the key enabling technology for high-volume, low cost packaging of MEMS devices. State-of-the-art aligned silicon wafer bonding can provide not only basic MEMS device functionality, but also first-level assembly or packaging solutions for many MEMS devices. Numerous examples of high-volume production applications for wafer-level bonding will be described.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131340395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866811
Bin Lian, T. Dishongh, D. Pullen, Hongfei Yan, J. Chen
Modern microelectronics, especially high performance microprocessors need to go through rigorous test and stressing to identify infant mortality failure. One of the stressing procedures is performed by running the devices at elevated temperature for prolonged period of time. With the ever faster microprocessor speed and device power, current burn-in solutions will not be enough to accommodate future generation of products. This study investigated the enhancement of local heat transfer by restricting open flow paths and redirection of cooling flow to the burn-in devices, through flow analysis with Flow Network Modeling software. A hierarchical modeling approach was used in which the flow characteristics of burn-in socket were derived, from which the burn-in board model was built, and a system level model was eventually assembled. Case study for a 3/spl times/5 burn-in board was conducted using Flow Network Modeling software and numerical results are presented.
{"title":"Flow network modeling for improving flow distribution of microelectronics burn-in oven","authors":"Bin Lian, T. Dishongh, D. Pullen, Hongfei Yan, J. Chen","doi":"10.1109/ITHERM.2000.866811","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866811","url":null,"abstract":"Modern microelectronics, especially high performance microprocessors need to go through rigorous test and stressing to identify infant mortality failure. One of the stressing procedures is performed by running the devices at elevated temperature for prolonged period of time. With the ever faster microprocessor speed and device power, current burn-in solutions will not be enough to accommodate future generation of products. This study investigated the enhancement of local heat transfer by restricting open flow paths and redirection of cooling flow to the burn-in devices, through flow analysis with Flow Network Modeling software. A hierarchical modeling approach was used in which the flow characteristics of burn-in socket were derived, from which the burn-in board model was built, and a system level model was eventually assembled. Case study for a 3/spl times/5 burn-in board was conducted using Flow Network Modeling software and numerical results are presented.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866184
R. Zeighami, D. Laser, P. Zhou, M. Asheghi, S. Devasenathipathy, T. Kenny, J. Santiago, K. Goodson
Microchannel heat sinks are promising for cooling applications in advanced electronic systems. More research is needed to understand microchannel flow regimes. Recent pressure drop data in microchannels with hydraulic diameters between 50 and 300 /spl mu/m suggest that the transition to turbulence may occur at lower than expected values of the Reynolds number. This work studies turbulent transition in microchannels using micron-resolution particle imaging velocimetry (/spl mu/PIV) with epifluorescent microscopy of 950 nm particles. Silicon channels with dimensions 150 /spl mu/m/spl times/100 /spl mu/m/spl times/1 cm are fabricated using deep reactive ion etching and sealed using a glass plate. Velocity field data for 200Re>1600, which is lower than values near 2200 measured previously for larger channels with similar shapes. This discrepancy may be caused by wall roughness, viscous heat generation, or electrokinetic effects. The experimental approach developed here provides the groundwork for a detailed study of turbulence transition in microchannels.
{"title":"Experimental investigation of flow transition in microchannels using micron-resolution particle image velocimetry","authors":"R. Zeighami, D. Laser, P. Zhou, M. Asheghi, S. Devasenathipathy, T. Kenny, J. Santiago, K. Goodson","doi":"10.1109/ITHERM.2000.866184","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866184","url":null,"abstract":"Microchannel heat sinks are promising for cooling applications in advanced electronic systems. More research is needed to understand microchannel flow regimes. Recent pressure drop data in microchannels with hydraulic diameters between 50 and 300 /spl mu/m suggest that the transition to turbulence may occur at lower than expected values of the Reynolds number. This work studies turbulent transition in microchannels using micron-resolution particle imaging velocimetry (/spl mu/PIV) with epifluorescent microscopy of 950 nm particles. Silicon channels with dimensions 150 /spl mu/m/spl times/100 /spl mu/m/spl times/1 cm are fabricated using deep reactive ion etching and sealed using a glass plate. Velocity field data for 200Re>1600, which is lower than values near 2200 measured previously for larger channels with similar shapes. This discrepancy may be caused by wall roughness, viscous heat generation, or electrokinetic effects. The experimental approach developed here provides the groundwork for a detailed study of turbulence transition in microchannels.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134303908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866810
A. Minichiello
Fortunately for engineers responsible for thermal management of today's electronic systems, many tools exist that provide for efficient, comprehensive thermal design. These tools, including heat transfer correlations, Computational Fluid Dynamics (CFD) solvers, and Flow Network Modeling (FNM) techniques, assist engineers in answering complex layout questions and proposing thermally feasible design alternatives quickly. This paper presents the use of FNM as proposed by G. Ellison (1984), to perform a first order thermal analysis on a next-generation mid-range computer design. Ellison's method is used to predict system level pressure drops and air-mover performance in the complex computer system prior to building hardware, performing sub-system flow measurements or completing system level CFD analyses. In this application, the use of FNM allowed a small design team to sufficiently validate the system layout early in the product's design cycle, enabling continued sub-system layout, detailed design; and prototype production within the constraints of the project's aggressive schedule. Results of the Ellison based approach are compared with those of a commercially available FNM software package and with data taken from a system prototype. Comparison shows that the results agree well, validating the use of FNM as an aid in developing thermally feasible computer designs.
{"title":"Flow network modeling: a case study in expedient system prototyping","authors":"A. Minichiello","doi":"10.1109/ITHERM.2000.866810","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866810","url":null,"abstract":"Fortunately for engineers responsible for thermal management of today's electronic systems, many tools exist that provide for efficient, comprehensive thermal design. These tools, including heat transfer correlations, Computational Fluid Dynamics (CFD) solvers, and Flow Network Modeling (FNM) techniques, assist engineers in answering complex layout questions and proposing thermally feasible design alternatives quickly. This paper presents the use of FNM as proposed by G. Ellison (1984), to perform a first order thermal analysis on a next-generation mid-range computer design. Ellison's method is used to predict system level pressure drops and air-mover performance in the complex computer system prior to building hardware, performing sub-system flow measurements or completing system level CFD analyses. In this application, the use of FNM allowed a small design team to sufficiently validate the system layout early in the product's design cycle, enabling continued sub-system layout, detailed design; and prototype production within the constraints of the project's aggressive schedule. Results of the Ellison based approach are compared with those of a commercially available FNM software package and with data taken from a system prototype. Comparison shows that the results agree well, validating the use of FNM as an aid in developing thermally feasible computer designs.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130126054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866179
M. Zaghdoudi, C. Tantolin, C. Godet
This study reports on the effects of transient acceleration forces with constant input power on the thermal performance of copper/water flat heat pipe. Transient accelerations are generated using a centrifuge table to simulate acceleration forces typifying high performance aircraft maneuvering. These transients consist of three acceleration forces types: a single waveform with a peak value of 10 g with a duration of about 190 seconds, step changes with peak value of 10 g with a duration of about 300 seconds, and step changes of 1 g magnitude after thermal stabilization in the heat pipe operation. Partial depriming of the heat pipe and pooling of the working fluid are found to have an impact on the heat transport capability and transient behavior of the heat pipe. Repriming of the heat pipe under thermal load while being subjected to transient accelerations is also demonstrated.
{"title":"Flat heat pipes thermal performance in body force environment","authors":"M. Zaghdoudi, C. Tantolin, C. Godet","doi":"10.1109/ITHERM.2000.866179","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866179","url":null,"abstract":"This study reports on the effects of transient acceleration forces with constant input power on the thermal performance of copper/water flat heat pipe. Transient accelerations are generated using a centrifuge table to simulate acceleration forces typifying high performance aircraft maneuvering. These transients consist of three acceleration forces types: a single waveform with a peak value of 10 g with a duration of about 190 seconds, step changes with peak value of 10 g with a duration of about 300 seconds, and step changes of 1 g magnitude after thermal stabilization in the heat pipe operation. Partial depriming of the heat pipe and pooling of the working fluid are found to have an impact on the heat transport capability and transient behavior of the heat pipe. Repriming of the heat pipe under thermal load while being subjected to transient accelerations is also demonstrated.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114581498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866855
T. B. Thompson, Ganesh Subbarayan, R. James, F. P. Renken
The goals of the present paper are to demonstrate a methodology for studying the effect of printed circuit board (PCB) warpage and volume variation on the final equilibrium configuration of area-array packages. Although the eventual goal is the development of a predictive methodology for the reliability impact of circuit board and component warpage, the present study is limited to an assessment of solder joint shape in the presence of PCB warpage and volume variation. The effect of warpage is analyzed using a two-step procedure in the present paper. In the first step, the restoring forces and moments (in the molten state of solder droplet) that result from a given solder joint height, solder material volume, pad diameter, and pad tilt are predicted using the surface tension theory. In the second step of the analysis, the forces and moments at individual solder joints caused by varying solder heights, pad tilts, and solder volume are combined using an optimization procedure to predict the equilibrium configuration of the package. The developed procedure is demonstrated on a hypothetical area-array package with nine solder joints. Through an analysis of two scenarios, (1) constant solder volume with symmetric and non-symmetric package warpage, and (2) linearly distributed solder volume without warpage, it is shown that printed circuit board warpage can cause electronic packages to tilt during solder reflow resulting in variations in solder joint heights and pad tilts.
{"title":"A model for assessing the shape of solder joints in the presence of board warpage and volume variation in area-array packages","authors":"T. B. Thompson, Ganesh Subbarayan, R. James, F. P. Renken","doi":"10.1109/ITHERM.2000.866855","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866855","url":null,"abstract":"The goals of the present paper are to demonstrate a methodology for studying the effect of printed circuit board (PCB) warpage and volume variation on the final equilibrium configuration of area-array packages. Although the eventual goal is the development of a predictive methodology for the reliability impact of circuit board and component warpage, the present study is limited to an assessment of solder joint shape in the presence of PCB warpage and volume variation. The effect of warpage is analyzed using a two-step procedure in the present paper. In the first step, the restoring forces and moments (in the molten state of solder droplet) that result from a given solder joint height, solder material volume, pad diameter, and pad tilt are predicted using the surface tension theory. In the second step of the analysis, the forces and moments at individual solder joints caused by varying solder heights, pad tilts, and solder volume are combined using an optimization procedure to predict the equilibrium configuration of the package. The developed procedure is demonstrated on a hypothetical area-array package with nine solder joints. Through an analysis of two scenarios, (1) constant solder volume with symmetric and non-symmetric package warpage, and (2) linearly distributed solder volume without warpage, it is shown that printed circuit board warpage can cause electronic packages to tilt during solder reflow resulting in variations in solder joint heights and pad tilts.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128433950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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