Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866175
J. Parry, C. Bailey, C. Aldham
The future of many companies will depend to a large extent on their ability to initiate techniques that bring schedules, performance, tests, support, production, life-cycle-costs, reliability prediction and quality control into the earliest stages of the product creation process. Important questions for an engineer who is responsible for the quality of electronic parts such as printed circuit boards (PCBs) during design, production, assembly and after-sales support are: What is the impact of temperature? What is the impact of this temperature on the stress produced in the components? What is the electromagnetic compatibility (EMC) associated with such a design? At present, thermal, stress and EMC calculations are undertaken using different software tools that each require model build and meshing. This leads to a large investment in time, and hence cost, to undertake each of these simulations. This paper discusses the progression towards a fully integrated software environment, based on a common data model and user interface, having the capability to predict temperature, stress and EMC fields in a coupled manner. Such a modelling environment used early within the design stage of an electronic product will provide engineers with fast solutions to questions regarding thermal, stress and EMC issues. The paper concentrates on recent developments in creating such an integrated modeling environment with preliminary results from the analyses conducted. Further research into the thermal and stress related aspects of the paper is being conducted under a nationally funded project, while their application in reliability prediction will be addressed in a new European project called PROFIT.
{"title":"Multiphysics modelling for electronics design","authors":"J. Parry, C. Bailey, C. Aldham","doi":"10.1109/ITHERM.2000.866175","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866175","url":null,"abstract":"The future of many companies will depend to a large extent on their ability to initiate techniques that bring schedules, performance, tests, support, production, life-cycle-costs, reliability prediction and quality control into the earliest stages of the product creation process. Important questions for an engineer who is responsible for the quality of electronic parts such as printed circuit boards (PCBs) during design, production, assembly and after-sales support are: What is the impact of temperature? What is the impact of this temperature on the stress produced in the components? What is the electromagnetic compatibility (EMC) associated with such a design? At present, thermal, stress and EMC calculations are undertaken using different software tools that each require model build and meshing. This leads to a large investment in time, and hence cost, to undertake each of these simulations. This paper discusses the progression towards a fully integrated software environment, based on a common data model and user interface, having the capability to predict temperature, stress and EMC fields in a coupled manner. Such a modelling environment used early within the design stage of an electronic product will provide engineers with fast solutions to questions regarding thermal, stress and EMC issues. The paper concentrates on recent developments in creating such an integrated modeling environment with preliminary results from the analyses conducted. Further research into the thermal and stress related aspects of the paper is being conducted under a nationally funded project, while their application in reliability prediction will be addressed in a new European project called PROFIT.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121606410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866185
W. Nakayama, M. Behnia, D. Soodphakdee
The paper describes a novel approach to solving heat transfer problems in geometrically complex systems. In the present approach, instead of simulating the detailed complex geometry, templates of components and devices are assumed rather than working on actual components. By varying the template dimensions a systematic study on the effects of geometrical configurations on cooling airflow and heat transfer is made possible. The application of the approach is illustrated drawing examples from cases of heat spreader designs and heat transfer analysis of portable computers. The purpose of the study is to develop a methodology whereby the packaging designer is freed from the task of performing detailed numerical analysis. Currently available numerical analysis tools such as computational fluid dynamics (CFD) codes are given a role in an undertaking to create databases from which fast design formulas are developed.
{"title":"A novel approach to the design of complex heat transfer systems: heat spreader and portable computer design-case studies","authors":"W. Nakayama, M. Behnia, D. Soodphakdee","doi":"10.1109/ITHERM.2000.866185","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866185","url":null,"abstract":"The paper describes a novel approach to solving heat transfer problems in geometrically complex systems. In the present approach, instead of simulating the detailed complex geometry, templates of components and devices are assumed rather than working on actual components. By varying the template dimensions a systematic study on the effects of geometrical configurations on cooling airflow and heat transfer is made possible. The application of the approach is illustrated drawing examples from cases of heat spreader designs and heat transfer analysis of portable computers. The purpose of the study is to develop a methodology whereby the packaging designer is freed from the task of performing detailed numerical analysis. Currently available numerical analysis tools such as computational fluid dynamics (CFD) codes are given a role in an undertaking to create databases from which fast design formulas are developed.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123488883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866833
M.R. Jouppi, R. Mason
The current-carrying capacity of printed wiring board (PWB) electrical conductors in a space environment (i.e. vacuum with radiation) has previously not been quantified. The results from this paper help to characterize the temperature response of PWB conductors as a function of current and cross-sectional area. This paper documents PWB internal conductor temperatures as a function of current and cross-sectional area in vacuum/space environments. It also shows the influence of an internal 2-ounce copper plane on internal conductor temperatures. A series of tests were performed to collect PWB conductor temperatures as a function of current in vacuum environments. Tests were performed following ANSI standard ANSI C83.59-1971, Reference 1. This standard describes a methodology for testing PWB conductors. Additional configuration tests were done to show the influence on conductor temperatures from the presence of an internal copper plane within the PWB. The results are for electrical circuit conductors in printed wiring boards constructed with a space applicable polyimide board material. Results are shown for internal conductors of varying conductor widths and thickness. The conductor temperature rise for various current levels is presented with respect to conductor cross-sectional area. The tests were performed in vacuum to simulate a space environment. IPC-2221, Reference 2, contains design standards for sizing electrical conductors in printed wiring boards. Test results are presented and compared with the IPC standard. These results show as much as 60% margin exists in the current-carrying capacity of internal conductors in a bare (no internal copper plane) polyimide board with only traces. Then, margins as high as 200% are observed in a board with a 2 ounce internal copper plane.
{"title":"Current-carrying capacity of PWB internal conductors in space environments","authors":"M.R. Jouppi, R. Mason","doi":"10.1109/ITHERM.2000.866833","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866833","url":null,"abstract":"The current-carrying capacity of printed wiring board (PWB) electrical conductors in a space environment (i.e. vacuum with radiation) has previously not been quantified. The results from this paper help to characterize the temperature response of PWB conductors as a function of current and cross-sectional area. This paper documents PWB internal conductor temperatures as a function of current and cross-sectional area in vacuum/space environments. It also shows the influence of an internal 2-ounce copper plane on internal conductor temperatures. A series of tests were performed to collect PWB conductor temperatures as a function of current in vacuum environments. Tests were performed following ANSI standard ANSI C83.59-1971, Reference 1. This standard describes a methodology for testing PWB conductors. Additional configuration tests were done to show the influence on conductor temperatures from the presence of an internal copper plane within the PWB. The results are for electrical circuit conductors in printed wiring boards constructed with a space applicable polyimide board material. Results are shown for internal conductors of varying conductor widths and thickness. The conductor temperature rise for various current levels is presented with respect to conductor cross-sectional area. The tests were performed in vacuum to simulate a space environment. IPC-2221, Reference 2, contains design standards for sizing electrical conductors in printed wiring boards. Test results are presented and compared with the IPC standard. These results show as much as 60% margin exists in the current-carrying capacity of internal conductors in a bare (no internal copper plane) polyimide board with only traces. Then, margins as high as 200% are observed in a board with a 2 ounce internal copper plane.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124900636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866172
Hua Lu, C. Bailey
This paper describes how modeling technology has been used in providing fatigue life time data of two flip-chip models. Full-scale three-dimensional modeling of flip-chips under cyclic thermal loading has been combined with solder joint stand-off height prediction to analyze the stress and strain conditions in the two models. The Coffin-Manson empirical relationship is employed to predict the fatigue life times of the solder interconnects. In order to help designers in selecting the underfill material and the printed circuit board, the Young's modulus and the coefficient of thermal expansion of the underfill, as well as the thickness of the printed circuit boards are treated as variable parameters. Fatigue life times are therefore calculated over a range of these material and geometry parameters. In this paper we will also describe how the use of micro-via technology may affect fatigue life.
{"title":"Material properties, geometry and their effect on the fatigue life of two flip-chip models","authors":"Hua Lu, C. Bailey","doi":"10.1109/ITHERM.2000.866172","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866172","url":null,"abstract":"This paper describes how modeling technology has been used in providing fatigue life time data of two flip-chip models. Full-scale three-dimensional modeling of flip-chips under cyclic thermal loading has been combined with solder joint stand-off height prediction to analyze the stress and strain conditions in the two models. The Coffin-Manson empirical relationship is employed to predict the fatigue life times of the solder interconnects. In order to help designers in selecting the underfill material and the printed circuit board, the Young's modulus and the coefficient of thermal expansion of the underfill, as well as the thickness of the printed circuit boards are treated as variable parameters. Fatigue life times are therefore calculated over a range of these material and geometry parameters. In this paper we will also describe how the use of micro-via technology may affect fatigue life.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128661572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866827
S. Narasimhan, Kuan-Lin Chen, Frank Stenger
Different kind of numerical approaches have been used in the past to solve the complete set of Navier Stokes equations. The traditional methods that have been used in the past are the finite-difference method, finite-element method and the boundary element method. Multigrid methods have been used recently for solving these complete set of Navier Stokes equations and they help in obtaining a faster rate of convergence of the residual for the solution of these equations. Some of the problems that are faced in the world of numerical methods today are the capacity to handle singularities that occur within or at the boundaries of a computational domain and also the capacity to handle semi-infinite and infinite domains. Sine numerical method has the advantage of handling singularities and semi-infinite domains very effectively. It also provides an exponential convergence rate. This study involves a first step in applying the sine numerical method to the flow within a driven cavity, which requires the solution of the complete two-dimensional Navier Stokes equations. The sine collocation method was applied to the driven cavity problem. The Navier Stokes equations were solved by means of two dimensional sine collocation using the primitive variables method. Simulations were also carried out with the finite-difference method for the same problem and the results were matched with the sine collocation method. Simulations were also carried out by using the commercial CFD code FLUENT. It was seen that the profiles compared well between the different methods.
{"title":"The solution of incompressible Navier Stokes equations using the sine collocation method","authors":"S. Narasimhan, Kuan-Lin Chen, Frank Stenger","doi":"10.1109/ITHERM.2000.866827","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866827","url":null,"abstract":"Different kind of numerical approaches have been used in the past to solve the complete set of Navier Stokes equations. The traditional methods that have been used in the past are the finite-difference method, finite-element method and the boundary element method. Multigrid methods have been used recently for solving these complete set of Navier Stokes equations and they help in obtaining a faster rate of convergence of the residual for the solution of these equations. Some of the problems that are faced in the world of numerical methods today are the capacity to handle singularities that occur within or at the boundaries of a computational domain and also the capacity to handle semi-infinite and infinite domains. Sine numerical method has the advantage of handling singularities and semi-infinite domains very effectively. It also provides an exponential convergence rate. This study involves a first step in applying the sine numerical method to the flow within a driven cavity, which requires the solution of the complete two-dimensional Navier Stokes equations. The sine collocation method was applied to the driven cavity problem. The Navier Stokes equations were solved by means of two dimensional sine collocation using the primitive variables method. Simulations were also carried out with the finite-difference method for the same problem and the results were matched with the sine collocation method. Simulations were also carried out by using the commercial CFD code FLUENT. It was seen that the profiles compared well between the different methods.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130198478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866812
S.S. Kang
This paper describes the air flow design of a computer system using commercially available flow network modeling (FNM) and computational fluid dynamics (CFD) software and proposes a new Hybrid approach that combines the best features of both. The basis of the proposed approach lies in the recognition that air flow within different regions of a computer system can be divided into two categories. One category, consisting of regions or subsystems through which the flow direction is well defined (e.g. Channels formed between card arrays, power supplies, an array of disk drives etc.) is well modeled using a flow impedance component in a FNM representation whereas the second type of region where the flow pattern is poorly defined (e.g. Air flow plenums) and highly dependent on the characteristics of adjoining subsystems requires CFD to model adequately. The FNM model of the sample design problem provides quick results and allows many design alternatives to be assessed but at the inevitable cost of oversimplifying the second type of region. The full system CFD model is large in size, requires a large computational time and significant post processing effort to understand the results. These issues are addressed by the Hybrid method whose key attributes and implementation within FNM and CFD codes is described. A CFD model is used to illustrate the proposed approach and demonstrate that, for the specific design problem used here, the method yields good accuracy while achieving 14/spl times/ reduction in model size and 30/spl times/ reduction in simulation time compared to the full CFD model.
{"title":"Application of flow network modeling and CFD to computer system design","authors":"S.S. Kang","doi":"10.1109/ITHERM.2000.866812","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866812","url":null,"abstract":"This paper describes the air flow design of a computer system using commercially available flow network modeling (FNM) and computational fluid dynamics (CFD) software and proposes a new Hybrid approach that combines the best features of both. The basis of the proposed approach lies in the recognition that air flow within different regions of a computer system can be divided into two categories. One category, consisting of regions or subsystems through which the flow direction is well defined (e.g. Channels formed between card arrays, power supplies, an array of disk drives etc.) is well modeled using a flow impedance component in a FNM representation whereas the second type of region where the flow pattern is poorly defined (e.g. Air flow plenums) and highly dependent on the characteristics of adjoining subsystems requires CFD to model adequately. The FNM model of the sample design problem provides quick results and allows many design alternatives to be assessed but at the inevitable cost of oversimplifying the second type of region. The full system CFD model is large in size, requires a large computational time and significant post processing effort to understand the results. These issues are addressed by the Hybrid method whose key attributes and implementation within FNM and CFD codes is described. A CFD model is used to illustrate the proposed approach and demonstrate that, for the specific design problem used here, the method yields good accuracy while achieving 14/spl times/ reduction in model size and 30/spl times/ reduction in simulation time compared to the full CFD model.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125338040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866851
R. Raghunathan, S. Sitaraman
With the continued demand for miniaturization, with the advent of new materials and processes, and with increased demand for better performance and lower cost, reliability of microelectronic devices continues to be a major concern. As microelectronic packages are used in a wide range of applications from automotive to aerospace to telecommunications to biomedical devices, there is a need for developing suitable qualification standards for these application domains. The ongoing work at Georgia Tech aims to develop a comprehensive virtual qualification system taking into consideration the process mechanics of substrate fabrication and component assembly, time- and temperature-dependent material behavior, process-induced defects, and critical geometric features of the assembly. The objective of this paper is to present one such virtual qualification technique for microelectronic packages used in automotive applications. Numerical models have been developed that take into account the creep behavior of the solder joints, the viscoelastic behavior of the underfill and the temperature-dependent orthotropic properties of the substrate. The models account for the solder reflow process and underfill cure process. They also account for multiple reflow and burn-in testing of the devices. Based on the information collected in terms of weather, underhood conditions, and driving profiles, qualification temperature cycling guidelines have been developed for automotive devices. The possibility of backside die cracking due to tensile stresses has also been investigated. The results from the models are being compared against experimental data from in-house as well as industrial sources.
{"title":"Qualification guidelines for automotive packaging devices","authors":"R. Raghunathan, S. Sitaraman","doi":"10.1109/ITHERM.2000.866851","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866851","url":null,"abstract":"With the continued demand for miniaturization, with the advent of new materials and processes, and with increased demand for better performance and lower cost, reliability of microelectronic devices continues to be a major concern. As microelectronic packages are used in a wide range of applications from automotive to aerospace to telecommunications to biomedical devices, there is a need for developing suitable qualification standards for these application domains. The ongoing work at Georgia Tech aims to develop a comprehensive virtual qualification system taking into consideration the process mechanics of substrate fabrication and component assembly, time- and temperature-dependent material behavior, process-induced defects, and critical geometric features of the assembly. The objective of this paper is to present one such virtual qualification technique for microelectronic packages used in automotive applications. Numerical models have been developed that take into account the creep behavior of the solder joints, the viscoelastic behavior of the underfill and the temperature-dependent orthotropic properties of the substrate. The models account for the solder reflow process and underfill cure process. They also account for multiple reflow and burn-in testing of the devices. Based on the information collected in terms of weather, underhood conditions, and driving profiles, qualification temperature cycling guidelines have been developed for automotive devices. The possibility of backside die cracking due to tensile stresses has also been investigated. The results from the models are being compared against experimental data from in-house as well as industrial sources.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126674069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866213
Y. Zhao, C. Basaran, A. Cartwright, T. Dishongh
Recent trends in reliability and fatigue life analysis of electronic devices have involved developing structural integrity models for predicting the operating lifetime under vibratory and thermal environmental exposure. Solder joint reliability is the most critical issue for the structural integrity of surface mounted electronics. Extensive research has been done on thermal behavior of solder joints, however, dynamic loading effects on solder joint fatigue life have not been thoroughly investigated. The physics of solder joint failure under vibration is still not very clear. This paper presents a test program which was performed to study inelastic behavior of solder joints of BGA packages. A concurrent loading unit is used which consists of a thermal environmental chamber and an electrodynamic shaker. Laser Moire Interferometry was used to measure the whole deformation field of the prepared specimen surface. The corresponding inelastic strain field is then calculated. It is found that at elevated temperature, vibration and shock can cause the accumulation of inelastic strains and damage in solder joints. In this paper, contrary to the popular belief that all vibration-induced strains are elastic, it is shown that vibration can cause significant inelastic strains.
{"title":"Thermomechanical behavior of BGA solder joints under vibrations: an experimental observation","authors":"Y. Zhao, C. Basaran, A. Cartwright, T. Dishongh","doi":"10.1109/ITHERM.2000.866213","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866213","url":null,"abstract":"Recent trends in reliability and fatigue life analysis of electronic devices have involved developing structural integrity models for predicting the operating lifetime under vibratory and thermal environmental exposure. Solder joint reliability is the most critical issue for the structural integrity of surface mounted electronics. Extensive research has been done on thermal behavior of solder joints, however, dynamic loading effects on solder joint fatigue life have not been thoroughly investigated. The physics of solder joint failure under vibration is still not very clear. This paper presents a test program which was performed to study inelastic behavior of solder joints of BGA packages. A concurrent loading unit is used which consists of a thermal environmental chamber and an electrodynamic shaker. Laser Moire Interferometry was used to measure the whole deformation field of the prepared specimen surface. The corresponding inelastic strain field is then calculated. It is found that at elevated temperature, vibration and shock can cause the accumulation of inelastic strains and damage in solder joints. In this paper, contrary to the popular belief that all vibration-induced strains are elastic, it is shown that vibration can cause significant inelastic strains.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132166128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866192
E. Ong, A. Tay, J.H. Wu
This paper describes a study of the effects of a delamination at the silicon/underfill interface on the fatigue life of the solder joints of a flip chip. It was first shown that it is important to consider creep deformation during the ramp times, in order to capture the deformation of the solder joints correctly. The effect of the size and location of typical delaminations in a flip chip assembly was then studied. A total of seven cases were simulated using three-dimensional finite element models. These consist of a baseline case with no delamination, and six other cases with different delamination sizes and locations. The fatigue life of the most critical solder joint was found to vary nonlinearly with delamination size and exponentially with distance between delamination and solder joint. It has been established in the literature that the most critical solder joint in a flip chip assembly is the outermost one. However, it was found in this study that the presence of a delamination near another solder joint can cause that particular solder joint to become the most critical one in the flip chip assembly.
{"title":"Effect of delamination on the thermal fatigue of solder joints in flip chips","authors":"E. Ong, A. Tay, J.H. Wu","doi":"10.1109/ITHERM.2000.866192","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866192","url":null,"abstract":"This paper describes a study of the effects of a delamination at the silicon/underfill interface on the fatigue life of the solder joints of a flip chip. It was first shown that it is important to consider creep deformation during the ramp times, in order to capture the deformation of the solder joints correctly. The effect of the size and location of typical delaminations in a flip chip assembly was then studied. A total of seven cases were simulated using three-dimensional finite element models. These consist of a baseline case with no delamination, and six other cases with different delamination sizes and locations. The fatigue life of the most critical solder joint was found to vary nonlinearly with delamination size and exponentially with distance between delamination and solder joint. It has been established in the literature that the most critical solder joint in a flip chip assembly is the outermost one. However, it was found in this study that the presence of a delamination near another solder joint can cause that particular solder joint to become the most critical one in the flip chip assembly.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131262533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-05-23DOI: 10.1109/ITHERM.2000.866165
H. Iwasaki, M. Ishizuka
Three-dimensional laminar flow simulation was carried out in order to investigate forced convection air cooling characteristics of compact plate fin arrays expected to be used for cooling notebook personal computers under the condition for which the fin tips were shrouded and no spanwise space around the fins was provided. The numerical simulation was performed by considering a conjugate problem which solved both flow and heat transfer in air stream and heat conduction in the fins and fin bases. Numerical results showed that the average heat transfer coefficient of the fin base was approximately one half of that of the fin. Based on the results of computation, some empirical equations for average Nusselt number of the fins and the fin bases and the friction factor were proposed as a function of Reynolds number. Using the fin efficiency calculated on the basis of the conventional conduction fin model, the thermal resistance of the plate fins could be estimated easily on the basis of the above-mentioned equations within an error level of 5% compared with the numerical results. The results also led to an important finding that there existed an optimum fin spacing fora given heat flux which could minimize blowing power.
{"title":"Forced convection air cooling characteristics of plate fins for notebook personal computers","authors":"H. Iwasaki, M. Ishizuka","doi":"10.1109/ITHERM.2000.866165","DOIUrl":"https://doi.org/10.1109/ITHERM.2000.866165","url":null,"abstract":"Three-dimensional laminar flow simulation was carried out in order to investigate forced convection air cooling characteristics of compact plate fin arrays expected to be used for cooling notebook personal computers under the condition for which the fin tips were shrouded and no spanwise space around the fins was provided. The numerical simulation was performed by considering a conjugate problem which solved both flow and heat transfer in air stream and heat conduction in the fins and fin bases. Numerical results showed that the average heat transfer coefficient of the fin base was approximately one half of that of the fin. Based on the results of computation, some empirical equations for average Nusselt number of the fins and the fin bases and the friction factor were proposed as a function of Reynolds number. Using the fin efficiency calculated on the basis of the conventional conduction fin model, the thermal resistance of the plate fins could be estimated easily on the basis of the above-mentioned equations within an error level of 5% compared with the numerical results. The results also led to an important finding that there existed an optimum fin spacing fora given heat flux which could minimize blowing power.","PeriodicalId":201262,"journal":{"name":"ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133472772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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