Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644883
Joachim Meyer, M. Dreschmann, D. Karnick, P. Schindler, W. Freude, J. Leuthold, J. Becker
In this paper the authors describe a novel system on chip (SoC) that is especially developed for digital signal processing of high-speed orthogonal frequency division multiplexing (OFDM) signals with data rates up to gigabits per second. Besides offering a new degree of freedom for the tradeoff between flexibility and performance during runtime, the modular concept of the SoC also allows a tradeoff between performance and costs during design time. The flexibility to adapt the OFDM system parameters by software enables even system designers without a good knowledge of hardware design to implement high-speed OFDM systems. An example configuration of the architecture was implemented on a Virtex-6 FPGA in order to set up a software-defined OFDM transmitter, achieving data rates of several gigabits per second. The paper closes with implementation and performance results of experiments using the developed transmitter and an optical transmission of the generated OFDM signals.
{"title":"A novel system on chip for software-defined, high-speed OFDM signal processing","authors":"Joachim Meyer, M. Dreschmann, D. Karnick, P. Schindler, W. Freude, J. Leuthold, J. Becker","doi":"10.1109/SBCCI.2013.6644883","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644883","url":null,"abstract":"In this paper the authors describe a novel system on chip (SoC) that is especially developed for digital signal processing of high-speed orthogonal frequency division multiplexing (OFDM) signals with data rates up to gigabits per second. Besides offering a new degree of freedom for the tradeoff between flexibility and performance during runtime, the modular concept of the SoC also allows a tradeoff between performance and costs during design time. The flexibility to adapt the OFDM system parameters by software enables even system designers without a good knowledge of hardware design to implement high-speed OFDM systems. An example configuration of the architecture was implemented on a Virtex-6 FPGA in order to set up a software-defined OFDM transmitter, achieving data rates of several gigabits per second. The paper closes with implementation and performance results of experiments using the developed transmitter and an optical transmission of the generated OFDM signals.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131576559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644863
Alberto Wiltgen, Kim A. Escobar, A. Reis, R. Ribas
This paper addresses the power consumption in CMOS logic gates through a study that considers the transistor network arrangement and the advance of the technology node. The relationship between charge/discharge and short-circuit dynamic power components are investigated through electrical simulations (SPICE). The static power dissipation is also analyzed. Experimental results demonstrate that dynamic power still remains the main source of consumption in standard cell designs, although the short-circuit component seems to decrease at the advancing of CMOS fabrication processes. The static power, on the other hand, keeps growing at each new technology node, becoming even more a critical challenge in VLSI design.
{"title":"Power consumption analysis in static CMOS gates","authors":"Alberto Wiltgen, Kim A. Escobar, A. Reis, R. Ribas","doi":"10.1109/SBCCI.2013.6644863","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644863","url":null,"abstract":"This paper addresses the power consumption in CMOS logic gates through a study that considers the transistor network arrangement and the advance of the technology node. The relationship between charge/discharge and short-circuit dynamic power components are investigated through electrical simulations (SPICE). The static power dissipation is also analyzed. Experimental results demonstrate that dynamic power still remains the main source of consumption in standard cell designs, although the short-circuit component seems to decrease at the advancing of CMOS fabrication processes. The static power, on the other hand, keeps growing at each new technology node, becoming even more a critical challenge in VLSI design.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127510741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644864
F. Marranghello, A. Reis, R. Ribas
This paper presents a novel approach for delay modeling of CMOS complex gates, containing series and parallel transistor arrangements. The model uses a charge based approach instead of evaluating voltages as function of time. The impact of input transition time, input-to-output coupling capacitance and short-channel effects, such as drain-induced barrier lowering (DIBL) and velocity saturation, are taken into account. The only empirical parameters are those required to calibrate the transistor model. Analytical results are in good agreement with HSPICE simulation data, based on BSIM4 transistor model, over a wide range of input slopes and output loads. Additionally, model accuracy has been improved when compared to previous related work.
{"title":"Delay model for static CMOS complex gates","authors":"F. Marranghello, A. Reis, R. Ribas","doi":"10.1109/SBCCI.2013.6644864","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644864","url":null,"abstract":"This paper presents a novel approach for delay modeling of CMOS complex gates, containing series and parallel transistor arrangements. The model uses a charge based approach instead of evaluating voltages as function of time. The impact of input transition time, input-to-output coupling capacitance and short-channel effects, such as drain-induced barrier lowering (DIBL) and velocity saturation, are taken into account. The only empirical parameters are those required to calibrate the transistor model. Analytical results are in good agreement with HSPICE simulation data, based on BSIM4 transistor model, over a wide range of input slopes and output loads. Additionally, model accuracy has been improved when compared to previous related work.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"2004 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125790920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644870
W. R. A. Dias, E. Moreno, Isaac Nattan Palmeira
This paper proposes a new method of code compression for embedded systems called by us as CC-MLD (Compressed Code using Huffman-Based Multi-Level Dictionary). This method applies two compression techniques and it uses the Huffman code compression algorithm. A single dictionary is divided into two levels and it is shared by both techniques. We performed simulations using applications from MiBench and we have used four embedded processors (ARM, MIPS, PowerPC and SPARC). Our method reduces code size up to 30.6% (including all extra costs for these four platforms). We have implemented the decompressor using VHDL and FPGA and we obtained only one clock from decompression process.
本文提出了一种新的嵌入式系统代码压缩方法，我们称之为CC-MLD (Compressed code using Huffman-Based Multi-Level Dictionary)。该方法采用了两种压缩技术，并采用了霍夫曼码压缩算法。一本字典被分为两个级别，并且被两种技术共享。我们使用MiBench的应用程序进行了模拟，我们使用了四个嵌入式处理器(ARM, MIPS, PowerPC和SPARC)。我们的方法将代码大小减少了30.6%(包括这四个平台的所有额外成本)。我们利用VHDL和FPGA实现了该解压缩器，在解压缩过程中只得到一个时钟。
{"title":"A new code compression algorithm and its decompressor in FPGA-based hardware","authors":"W. R. A. Dias, E. Moreno, Isaac Nattan Palmeira","doi":"10.1109/SBCCI.2013.6644870","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644870","url":null,"abstract":"This paper proposes a new method of code compression for embedded systems called by us as CC-MLD (Compressed Code using Huffman-Based Multi-Level Dictionary). This method applies two compression techniques and it uses the Huffman code compression algorithm. A single dictionary is divided into two levels and it is shared by both techniques. We performed simulations using applications from MiBench and we have used four embedded processors (ARM, MIPS, PowerPC and SPARC). Our method reduces code size up to 30.6% (including all extra costs for these four platforms). We have implemented the decompressor using VHDL and FPGA and we obtained only one clock from decompression process.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114658986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644871
Augusto Neutzling, Mayler G. A. Martins, R. Ribas, A. Reis
In this paper, a novel method to identify threshold logic functions (TLF) is proposed. Threshold logic is a promising alternative to conventional Boolean logic that has been recently revisited due to the suitability to emerging technologies, such as QCA, RTD, SET, TPL and spintronics. Identification and synthesis of TLF are fundamental tasks for the development of circuit design flow based on such logic style. The proposed method exploits both the order of Chow parameters and the system of inequalities, extracted from a function, to assign optimal variable weights and optimal threshold value. It is the first heuristic algorithm that does not uses integer linear programming (ILP) able to identify all threshold functions with up to five variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is higher than five. The proposed algorithm is scalable, since the average execution time is less than 1 ms per function. Furthermore, the method always assigns the minimum weights, resulting in circuits with minimum area.
{"title":"Synthesis of threshold logic gates to nanoelectronics","authors":"Augusto Neutzling, Mayler G. A. Martins, R. Ribas, A. Reis","doi":"10.1109/SBCCI.2013.6644871","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644871","url":null,"abstract":"In this paper, a novel method to identify threshold logic functions (TLF) is proposed. Threshold logic is a promising alternative to conventional Boolean logic that has been recently revisited due to the suitability to emerging technologies, such as QCA, RTD, SET, TPL and spintronics. Identification and synthesis of TLF are fundamental tasks for the development of circuit design flow based on such logic style. The proposed method exploits both the order of Chow parameters and the system of inequalities, extracted from a function, to assign optimal variable weights and optimal threshold value. It is the first heuristic algorithm that does not uses integer linear programming (ILP) able to identify all threshold functions with up to five variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is higher than five. The proposed algorithm is scalable, since the average execution time is less than 1 ms per function. Furthermore, the method always assigns the minimum weights, resulting in circuits with minimum area.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128690199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644851
Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum
Three-dimension Multiprocessors System-on-Chip (3D-MPSoCs) hold promises to allow the development of compact and efficient devices. By means of such technology, multiple applications are supported on the same chip, which can be mapped dynamically during the execution time. This flexibility offered by the 3D technology, also represents vulnerability, turning the 3D-MPSoC security into a challenging task. 3D communication structures (3D-HoCs), which combine buses and network-on-chip can be used to efficiently overcome the present 3D-MPSoC vulnerabilities. 3D-HoCs can be used to implement different security services, monitor the data exchange and isolate dangerous IPs. In this paper, we implement Quality of Security Service (QoSS) in 3D-HoC to efficiently detect and prevent attacks by means of agile and dynamic security firewalls. Such a method takes advantage of the 3D-HoC wide system visibility and critical role in enabling system operation. We evaluate the effectiveness of our approach over several 3D-MPSoCs attack scenarios and estimate their impact on the overall performance. Results show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies.
{"title":"Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection","authors":"Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum","doi":"10.1109/SBCCI.2013.6644851","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644851","url":null,"abstract":"Three-dimension Multiprocessors System-on-Chip (3D-MPSoCs) hold promises to allow the development of compact and efficient devices. By means of such technology, multiple applications are supported on the same chip, which can be mapped dynamically during the execution time. This flexibility offered by the 3D technology, also represents vulnerability, turning the 3D-MPSoC security into a challenging task. 3D communication structures (3D-HoCs), which combine buses and network-on-chip can be used to efficiently overcome the present 3D-MPSoC vulnerabilities. 3D-HoCs can be used to implement different security services, monitor the data exchange and isolate dangerous IPs. In this paper, we implement Quality of Security Service (QoSS) in 3D-HoC to efficiently detect and prevent attacks by means of agile and dynamic security firewalls. Such a method takes advantage of the 3D-HoC wide system visibility and critical role in enabling system operation. We evaluate the effectiveness of our approach over several 3D-MPSoCs attack scenarios and estimate their impact on the overall performance. Results show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117348972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644879
L. Severo, A. Girardi
This paper presents an automatic sizing methodology for CMOS operational amplifiers considering process parameter variations in submicron technologies. These circuits are very sensitive to process variations, which cause mismatch. The proposed methodology comprises simultaneous optimization of power dissipation, gate area and yield prediction, exploring effectively the design space in all transistor operation regions. Yield is estimated by Monte Carlo analysis, which is performed only for the best solutions candidates in the optimization procedure. A Miller OTA and a folded cascode amplifier are designed in 0.18μm technology using the proposed methodology. Results show the increase in the circuit yield comparing to the same design without yield prediction, while keeping the power and area budget and a reasonable computational time.
{"title":"A methodology for the automatic design of operational amplifiers including yield optimization","authors":"L. Severo, A. Girardi","doi":"10.1109/SBCCI.2013.6644879","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644879","url":null,"abstract":"This paper presents an automatic sizing methodology for CMOS operational amplifiers considering process parameter variations in submicron technologies. These circuits are very sensitive to process variations, which cause mismatch. The proposed methodology comprises simultaneous optimization of power dissipation, gate area and yield prediction, exploring effectively the design space in all transistor operation regions. Yield is estimated by Monte Carlo analysis, which is performed only for the best solutions candidates in the optimization procedure. A Miller OTA and a folded cascode amplifier are designed in 0.18μm technology using the proposed methodology. Results show the increase in the circuit yield comparing to the same design without yield prediction, while keeping the power and area budget and a reasonable computational time.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134228522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644875
Edson Sorato, Eduardo P. Fronza, Paulo R. F. M. M. Barbosa, José Luís Almada Güntzel, Adalbery R. Castro, A. Klautau
In this paper we investigate the use of the Support Vector Machine (SVM) approach to develop simple and efficient VLSI architectures for real-time digital modulation classification. Such simplicity and efficiency arise from the adoption of a front end block that is based on histograms. Particularly, we compare two decision schemes to solve the multiclass classification problem with linear SVMs, Pairwise and One Against the Rest (OAR), and propose an enhanced OAR scheme to improve the hit rate for low SNR values. Dedicated VLSI architectures for the three schemes were developed and logically synthesized with an industrial standard-cell flow for a 90 nm library. Functional simulation results show that the Enhanced-OAR verifier achieves up to 76% of hit rate in the 0 to 5 dB range, which corresponds to accuracy improvements of up to 162% over the OAR classifier. Synthesis results indicate a 21.8% of area overhead and 2% of power and energy increases. The results also pointed out that the Enhanced-OAR classifier is 14.1% smaller, consumes 30.1% less power and is 30.2% more energy-efficient than the Pairwise classifier, while providing up to 58.3% of accuracy improvements.
在本文中，我们研究了使用支持向量机(SVM)方法来开发用于实时数字调制分类的简单高效的VLSI架构。这种简单性和效率源于采用了基于直方图的前端模块。特别地，我们比较了线性支持向量机解决多类分类问题的两种决策方案，Pairwise和One Against the Rest (OAR)，并提出了一种增强的OAR方案，以提高低信噪比值的命中率。为这三种方案开发了专用的VLSI架构，并根据90纳米库的工业标准单元流程进行了逻辑合成。功能仿真结果表明，增强的OAR验证器在0 ~ 5 dB范围内达到76%的命中率，与OAR分类器相比，准确率提高了162%。综合结果表明，面积开销增加21.8%，功率和能量增加2%。结果还指出，Enhanced-OAR分类器比Pairwise分类器小14.1%，功耗减少30.1%，能效提高30.2%，准确率提高58.3%。
{"title":"Real-time digital modulation classification based on Support Vector Machines","authors":"Edson Sorato, Eduardo P. Fronza, Paulo R. F. M. M. Barbosa, José Luís Almada Güntzel, Adalbery R. Castro, A. Klautau","doi":"10.1109/SBCCI.2013.6644875","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644875","url":null,"abstract":"In this paper we investigate the use of the Support Vector Machine (SVM) approach to develop simple and efficient VLSI architectures for real-time digital modulation classification. Such simplicity and efficiency arise from the adoption of a front end block that is based on histograms. Particularly, we compare two decision schemes to solve the multiclass classification problem with linear SVMs, Pairwise and One Against the Rest (OAR), and propose an enhanced OAR scheme to improve the hit rate for low SNR values. Dedicated VLSI architectures for the three schemes were developed and logically synthesized with an industrial standard-cell flow for a 90 nm library. Functional simulation results show that the Enhanced-OAR verifier achieves up to 76% of hit rate in the 0 to 5 dB range, which corresponds to accuracy improvements of up to 162% over the OAR classifier. Synthesis results indicate a 21.8% of area overhead and 2% of power and energy increases. The results also pointed out that the Enhanced-OAR classifier is 14.1% smaller, consumes 30.1% less power and is 30.2% more energy-efficient than the Pairwise classifier, while providing up to 58.3% of accuracy improvements.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122364392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644853
Christoph Roth, Harald Bucher, Simon Reder, Florian Buciuman, O. Sander, J. Becker
Due to the growing complexity of embedded systems, simulation becomes an increasingly time-consuming task. Especially detailed simulation of so called Multi-Processor System-on-Chips (MPSoCs) is afflicted with extremely long runtimes and makes verification and debugging extraordinary expensive. In this work, a SystemC/TLM based methodology for accelerating simulation of NoC-based MPSoCs is presented that combines advantages of both, multi-abstraction level modeling and parallel execution on multi-core hosts. It integrates a parallel discrete event modeling paradigm with the concept of lightweight schedulers. The approach is evaluated on different host platforms by means of a realistic model. Results demonstrate that the approach can provide significant speedups of two orders of magnitude versus sequential RTL simulation, while preserving analyzability and exhibiting a moderate loss accuracy.
{"title":"A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation","authors":"Christoph Roth, Harald Bucher, Simon Reder, Florian Buciuman, O. Sander, J. Becker","doi":"10.1109/SBCCI.2013.6644853","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644853","url":null,"abstract":"Due to the growing complexity of embedded systems, simulation becomes an increasingly time-consuming task. Especially detailed simulation of so called Multi-Processor System-on-Chips (MPSoCs) is afflicted with extremely long runtimes and makes verification and debugging extraordinary expensive. In this work, a SystemC/TLM based methodology for accelerating simulation of NoC-based MPSoCs is presented that combines advantages of both, multi-abstraction level modeling and parallel execution on multi-core hosts. It integrates a parallel discrete event modeling paradigm with the concept of lightweight schedulers. The approach is evaluated on different host platforms by means of a realistic model. Results demonstrate that the approach can provide significant speedups of two orders of magnitude versus sequential RTL simulation, while preserving analyzability and exhibiting a moderate loss accuracy.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133005295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644885
A. Aita, C. Rodrigues
Proportional to Absolute Temperature (PTAT) CMOS current sources are widely used in temperature sensors, bandgap references, and other temperature-compensating circuits. Most of these applications strongly rely on the accuracy of a current ratio m established with a set of 1+m PTAT current sources. However, a PTAT CMOS current source has a temperature-dependent bias point, which in turn, has a well-known effect on the mismatch of CMOS current sources. This paper analyzes the mismatching properties of PTAT current sources due to variation of the current-sources bias point (gm/IDS) with temperature, from -55°C to 125°C. After the analysis, the paper shows measurements of a precision temperature sensor without mismatch compensation to corroborate the analysis developed.
{"title":"PTAT CMOS current sources mismatch over temperature","authors":"A. Aita, C. Rodrigues","doi":"10.1109/SBCCI.2013.6644885","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644885","url":null,"abstract":"Proportional to Absolute Temperature (PTAT) CMOS current sources are widely used in temperature sensors, bandgap references, and other temperature-compensating circuits. Most of these applications strongly rely on the accuracy of a current ratio m established with a set of 1+m PTAT current sources. However, a PTAT CMOS current source has a temperature-dependent bias point, which in turn, has a well-known effect on the mismatch of CMOS current sources. This paper analyzes the mismatching properties of PTAT current sources due to variation of the current-sources bias point (gm/IDS) with temperature, from -55°C to 125°C. After the analysis, the paper shows measurements of a precision temperature sensor without mismatch compensation to corroborate the analysis developed.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"3 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131844811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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