Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644886
Tony Forzley, R. Mason
This paper presents a dynamically latched threshold configurable comparator to eliminate the DAC in conventional SAR ADC designs. The comparator uses intentional circuit asymmetry to generate precise threshold or offset voltages. Four offset stages with resolutions of 15.5 μV, 316 μV, 7.9 mV and 29.85 mV are superimposed to yield a 282.6 mVpp tuning range. The high resolution is obtained by exploiting submicron deviations in device dimensions. The comparator has been designed and tested in 0.13 μm digital CMOS. DC measurements yield 14 bit resolution with 0.38 INL and 0.41 DNL. AC measurements at 6.25 MHz correlate well with the DC measurements. Noise is bandlimited to allow for sampling up to 50 MHz.
{"title":"A 14b threshold configurable dynamically latched comparator for SAR ADCs","authors":"Tony Forzley, R. Mason","doi":"10.1109/SBCCI.2013.6644886","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644886","url":null,"abstract":"This paper presents a dynamically latched threshold configurable comparator to eliminate the DAC in conventional SAR ADC designs. The comparator uses intentional circuit asymmetry to generate precise threshold or offset voltages. Four offset stages with resolutions of 15.5 μV, 316 μV, 7.9 mV and 29.85 mV are superimposed to yield a 282.6 mVpp tuning range. The high resolution is obtained by exploiting submicron deviations in device dimensions. The comparator has been designed and tested in 0.13 μm digital CMOS. DC measurements yield 14 bit resolution with 0.38 INL and 0.41 DNL. AC measurements at 6.25 MHz correlate well with the DC measurements. Noise is bandlimited to allow for sampling up to 50 MHz.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129939000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644862
V. Callegaro, Mayler G. A. Martins, R. Ribas, A. Reis
Efficient exact factoring algorithms are limited to read-once (RO) functions, where each variable appears once in the final Boolean expression. However, these algorithms present two important constraints: (1) they do not consider incompletely specified Boolean functions (ISF); and (2) they are not suitable for binate functions. To overcome the first drawback, an algorithm that finds RO expressions for ISF, whenever possible, is proposed. With respect to the second limitation, we propose a domain transformation that splits existing binate variables into two independent unate variables. Such domain transformation leads to ISF, which can be efficiently factored by applying the proposed algorithm. The combination of both contributions gives optimal results for a novel broader class of Boolean functions called read-polarity-once (RPO) functions, where each polarity (positive and negative) of a variable appears at most once in the factored form. Experimental results carried out over ISCAS'85 benchmark circuits have shown that RPO functions are significantly more frequent than RO functions.
{"title":"Read-polarity-once Boolean functions","authors":"V. Callegaro, Mayler G. A. Martins, R. Ribas, A. Reis","doi":"10.1109/SBCCI.2013.6644862","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644862","url":null,"abstract":"Efficient exact factoring algorithms are limited to read-once (RO) functions, where each variable appears once in the final Boolean expression. However, these algorithms present two important constraints: (1) they do not consider incompletely specified Boolean functions (ISF); and (2) they are not suitable for binate functions. To overcome the first drawback, an algorithm that finds RO expressions for ISF, whenever possible, is proposed. With respect to the second limitation, we propose a domain transformation that splits existing binate variables into two independent unate variables. Such domain transformation leads to ISF, which can be efficiently factored by applying the proposed algorithm. The combination of both contributions gives optimal results for a novel broader class of Boolean functions called read-polarity-once (RPO) functions, where each polarity (positive and negative) of a variable appears at most once in the factored form. Experimental results carried out over ISCAS'85 benchmark circuits have shown that RPO functions are significantly more frequent than RO functions.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122393165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644869
E. Ishibe, J. Navarro
A bandgap reference source with a temperature coefficient adjustment block was proposed. The topology employs current summation and the circuit was designed through a metaheuristic algorithm in an AMS 0.35-um CMOS technology and BSIM3V3 model. Monte Carlo simulations show that the designed circuit has an average temperature coefficient of 27 ppm/0C, average line regulation of 324 ppm/V, and average current consumption of 3.1 uA in a 1 V power supply. The 3-bit temperature adjustment block allowed a maximum temperature coefficient of 26.6 ppm/0C for 90% of the circuits without interfering in the reference voltage output or the line regulation.
提出了一种带温度系数调节块的带隙参考源。该拓扑结构采用电流求和，电路设计采用元启发式算法，采用AMS 0.35 um CMOS技术和BSIM3V3模型。蒙特卡罗仿真表明，所设计电路在1v电源下的平均温度系数为27 ppm/0C，平均线路稳压为324 ppm/V，平均电流消耗为3.1 uA。3位温度调节块允许90%电路的最大温度系数为26.6 ppm/0C，而不会干扰参考电压输出或线路调节。
{"title":"A CMOS bandgap reference circuit with a temperature coefficient adjustment block","authors":"E. Ishibe, J. Navarro","doi":"10.1109/SBCCI.2013.6644869","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644869","url":null,"abstract":"A bandgap reference source with a temperature coefficient adjustment block was proposed. The topology employs current summation and the circuit was designed through a metaheuristic algorithm in an AMS 0.35-um CMOS technology and BSIM3V3 model. Monte Carlo simulations show that the designed circuit has an average temperature coefficient of 27 ppm/0C, average line regulation of 324 ppm/V, and average current consumption of 3.1 uA in a 1 V power supply. The 3-bit temperature adjustment block allowed a maximum temperature coefficient of 26.6 ppm/0C for 90% of the circuits without interfering in the reference voltage output or the line regulation.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133598322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644855
Fabrício G. S. Silva, R. N. Lima, R. Freire
In this paper, the concept of block reuse is applied to design a dual-band power amplifier. The amplification cell is shared for each frequency band and the impedance matching networks are designed making use of switchless multiresonant circuits. The target frequencies are those of the ISM band, 433 and 915 MHz. In order to obtain a good compromise between linearity and efficiency, a class AB operation is adopted. The performance of amplifier was evaluated using post layout simulation. The results have shown 44.4 % and 44.8 % PAE peak efficiency at 29.0 dBm and 29.8 dBm output power, respectively, in the target frequencies.
{"title":"A 433/915-MHz class AB discrete power amplifier based on multiresonant circuits","authors":"Fabrício G. S. Silva, R. N. Lima, R. Freire","doi":"10.1109/SBCCI.2013.6644855","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644855","url":null,"abstract":"In this paper, the concept of block reuse is applied to design a dual-band power amplifier. The amplification cell is shared for each frequency band and the impedance matching networks are designed making use of switchless multiresonant circuits. The target frequencies are those of the ISM band, 433 and 915 MHz. In order to obtain a good compromise between linearity and efficiency, a class AB operation is adopted. The performance of amplifier was evaluated using post layout simulation. The results have shown 44.4 % and 44.8 % PAE peak efficiency at 29.0 dBm and 29.8 dBm output power, respectively, in the target frequencies.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132775920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644856
I. A. C. Gomes, F. Kastensmidt
The use of Triple Modular Redundancy (TMR) with majority voters can guarantee full single fault masking coverage for a given circuit against transient faults but it has a high area overhead. In order to reduce area overhead without compromising the fault making coverage, TMR can use approximated circuits approach to generate redundant modules that are optimized compared to the original module. Initial study of this technique has shown that it is possible to reach a good balance between fault coverage and area overhead cost, making this technique a good solution for some cases. In this work, we do a further analysis of this approach by using complex gates and employing different transistor topologies and inputs permutation. Results show that area overhead can be reduced to 150% with fault coverage close to 99%.
{"title":"Reducing TMR overhead by combining approximate circuit, transistor topology and input permutation approaches","authors":"I. A. C. Gomes, F. Kastensmidt","doi":"10.1109/SBCCI.2013.6644856","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644856","url":null,"abstract":"The use of Triple Modular Redundancy (TMR) with majority voters can guarantee full single fault masking coverage for a given circuit against transient faults but it has a high area overhead. In order to reduce area overhead without compromising the fault making coverage, TMR can use approximated circuits approach to generate redundant modules that are optimized compared to the original module. Initial study of this technique has shown that it is possible to reach a good balance between fault coverage and area overhead cost, making this technique a good solution for some cases. In this work, we do a further analysis of this approach by using complex gates and employing different transistor topologies and inputs permutation. Results show that area overhead can be reduced to 150% with fault coverage close to 99%.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123993205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644872
Caio G. P. Alegretti, V. D. Bem, R. Ribas, A. Reis
This paper presents a gate sizing method which formulates minimum active area solutions under delay constraints. The method is based on the logical effort delay model. The minimization of transistor widths has direct impact on the power consumption and circuit area reduction. The analytical formulation of the method takes into account the maximum input capacitance, the load to be driven, and the given timing constraint. Electrical simulations show that the proposed method is very precise for a first order approach, as it presents small average errors of 1.48% in power dissipation, 2.28% in delay propagation, and 6.5% in transistor sizes.
{"title":"Analytical logical effort formulation for minimum active area under delay constraints","authors":"Caio G. P. Alegretti, V. D. Bem, R. Ribas, A. Reis","doi":"10.1109/SBCCI.2013.6644872","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644872","url":null,"abstract":"This paper presents a gate sizing method which formulates minimum active area solutions under delay constraints. The method is based on the logical effort delay model. The minimization of transistor widths has direct impact on the power consumption and circuit area reduction. The analytical formulation of the method takes into account the maximum input capacitance, the load to be driven, and the given timing constraint. Electrical simulations show that the proposed method is very precise for a first order approach, as it presents small average errors of 1.48% in power dissipation, 2.28% in delay propagation, and 6.5% in transistor sizes.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125065952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644878
T. Weber, Sergio Chaparro, W. Noije
This paper presents the accurate synthesis of a narrow-band CMOS Low Noise Amplifier (LNA) using an optimization-based approach. Multi-objective information and the corners of the fabrication process are used in the synthesizer to simultaneously optimize impedance matching, performance parameters and circuit robustness. The synthesis approach combines the Simulated Annealing algorithm with the crossover operator and an automatic weight adjustment technique. This combination allows the optimizer to escape local minimums and therefore successfully achieve the LNA specifications. Two solutions of the synthesis are presented and the performance is verified through simulations using a 180 nm CMOS process. The first 2.45 GHz LNA solution achieved a Noise Figure of 1.95 dB, a S21 of 13.6 dB, a S11 of -17 dB, draining a 4.6 mA current. The second solution, which starts from the final first solution and adds a linearity constraint, achieved a Noise Figure of 2.04 dB, a S21 of 12.89 dB, a S11 of -25 dB, a PIIP3 of -7.8 dBm with a current of 4.1 mA. The results indicate the efficiency of the technique to synthesize LNAs, providing solutions comparable to similar presented in the literature.
{"title":"Synthesis of a narrow-band Low Noise Amplifier in a 180 nm CMOS technology using Simulated Annealing with crossover operator","authors":"T. Weber, Sergio Chaparro, W. Noije","doi":"10.1109/SBCCI.2013.6644878","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644878","url":null,"abstract":"This paper presents the accurate synthesis of a narrow-band CMOS Low Noise Amplifier (LNA) using an optimization-based approach. Multi-objective information and the corners of the fabrication process are used in the synthesizer to simultaneously optimize impedance matching, performance parameters and circuit robustness. The synthesis approach combines the Simulated Annealing algorithm with the crossover operator and an automatic weight adjustment technique. This combination allows the optimizer to escape local minimums and therefore successfully achieve the LNA specifications. Two solutions of the synthesis are presented and the performance is verified through simulations using a 180 nm CMOS process. The first 2.45 GHz LNA solution achieved a Noise Figure of 1.95 dB, a S21 of 13.6 dB, a S11 of -17 dB, draining a 4.6 mA current. The second solution, which starts from the final first solution and adds a linearity constraint, achieved a Noise Figure of 2.04 dB, a S21 of 12.89 dB, a S11 of -25 dB, a PIIP3 of -7.8 dBm with a current of 4.1 mA. The results indicate the efficiency of the technique to synthesize LNAs, providing solutions comparable to similar presented in the literature.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"2 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120973382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644859
F. S. Campos, J. Ulson, J. Swart, M. Deen, O. Marinov, D. Karam
Image sensors in standard CMOS technology are increasing used for consumer, industrial and scientific applications due to their low cost, high level of integration and low power consumption. Further, image sensors in mainstream complementary metal-oxide-semiconductor (CMOS) technology are preferred because they are the lowest cost and easiest/fastest option to implement. For CMOS image sensors, a key issue is their noise behavior. Therefore, we have studied the noise characteristics of CMOS image sensors operating in time domain. Two important noise sources are the reset noise and integration noise. The reset noise is due to the reset in CMOS image sensors operating in voltage domain. The integration noise is that accumulated during light integration and was found to be the constant, independent of light intensity. Our circuit analysis shows that the signal-to-noise ratio (SNR) is also constant and independent of light intensity. At low light levels the constant SNR is higher compared to others CMOS image sensors presented in the literature. We have implemented a time domain CMOS image sensor in AMS CMOS 0.35um technology. Our measurements results show that the SNR level is approximately constant to 43dB.
{"title":"Temporal noise analysis and measurements of CMOS active pixel sensor operating in time domain","authors":"F. S. Campos, J. Ulson, J. Swart, M. Deen, O. Marinov, D. Karam","doi":"10.1109/SBCCI.2013.6644859","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644859","url":null,"abstract":"Image sensors in standard CMOS technology are increasing used for consumer, industrial and scientific applications due to their low cost, high level of integration and low power consumption. Further, image sensors in mainstream complementary metal-oxide-semiconductor (CMOS) technology are preferred because they are the lowest cost and easiest/fastest option to implement. For CMOS image sensors, a key issue is their noise behavior. Therefore, we have studied the noise characteristics of CMOS image sensors operating in time domain. Two important noise sources are the reset noise and integration noise. The reset noise is due to the reset in CMOS image sensors operating in voltage domain. The integration noise is that accumulated during light integration and was found to be the constant, independent of light intensity. Our circuit analysis shows that the signal-to-noise ratio (SNR) is also constant and independent of light intensity. At low light levels the constant SNR is higher compared to others CMOS image sensors presented in the literature. We have implemented a time domain CMOS image sensor in AMS CMOS 0.35um technology. Our measurements results show that the SNR level is approximately constant to 43dB.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"123 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114010182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644880
Ismael Seidel, Bruno George de Moraes, André Beims Bräscher, José Luís Almada Güntzel
As the number of pixels per frame tends to increase in new high definition video coding standards such as HEVC, pel decimation appears as a viable means of increasing the energy efficiency of Sum of Absolute Differences (SAD) calculation. This paper presents a VLSI architecture that can be configured to compute the SAD of 4×4 pixel blocks with no subsampling or with 2:1 or 4:1 subsampling (pel decimation). The proposed architecture was synthesized for 130nm, 90nm, 65nm and 45nm standard cell libraries assuming both nominal and Low-Vdd/High-Vt (LH) cases for maximum and a given target throughput. The impacts of subsampling and Low-Vdd/High-Vt on delay, power and energy efficiency are analyzed. In a total of 16 syntheses, the 45nm/LH configurable SAD architecture achieved the highest energy efficiency for target frequency when operating in pel decimation 4:1, spending only 2.19pJ for each 4×4 block, which corresponds to about 20.64 times less energy than the 130nm/nominal configurable architecture operating in full SAD mode. Aside the improvements achieved by using LH, pel decimation solely was responsible for energy reductions of 40% and 60% when 2:1 and 4:1 subsamplings are chosen, respectively, in the configurable architecture.
{"title":"On the impacts of pel decimation and High-Vt/Low-Vdd on SAD calculation","authors":"Ismael Seidel, Bruno George de Moraes, André Beims Bräscher, José Luís Almada Güntzel","doi":"10.1109/SBCCI.2013.6644880","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644880","url":null,"abstract":"As the number of pixels per frame tends to increase in new high definition video coding standards such as HEVC, pel decimation appears as a viable means of increasing the energy efficiency of Sum of Absolute Differences (SAD) calculation. This paper presents a VLSI architecture that can be configured to compute the SAD of 4×4 pixel blocks with no subsampling or with 2:1 or 4:1 subsampling (pel decimation). The proposed architecture was synthesized for 130nm, 90nm, 65nm and 45nm standard cell libraries assuming both nominal and Low-Vdd/High-Vt (LH) cases for maximum and a given target throughput. The impacts of subsampling and Low-Vdd/High-Vt on delay, power and energy efficiency are analyzed. In a total of 16 syntheses, the 45nm/LH configurable SAD architecture achieved the highest energy efficiency for target frequency when operating in pel decimation 4:1, spending only 2.19pJ for each 4×4 block, which corresponds to about 20.64 times less energy than the 130nm/nominal configurable architecture operating in full SAD mode. Aside the improvements achieved by using LH, pel decimation solely was responsible for energy reductions of 40% and 60% when 2:1 and 4:1 subsamplings are chosen, respectively, in the configurable architecture.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127634762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644865
Julian J. H. Pontes, Ney Laert Vilar Calazans, P. Vivet
One of the next challenges for asynchronous communication architectures is reliability, in the form of robustness to single event effects, when under the impact of particles generated by ionizing radiation. This occurs because technology down-scaling continuously increases the logic sensitivity of silicon devices to such effects. Contrary to what happens in synchronous circuits, delay variations induced by radiation usually have no impact on asynchronous quasi-delay insensitive (QDI) combinational logic blocks, but in case of storage logic, bit flips may corrupt the circuit state with no recovery solution, even when using asynchronous circuits. This work proposes a new set of hardening techniques against single event effects applicable to asynchronous networks-on-chip. It presents practical case studies of use for these techniques and evaluates them in close to real life situations. Obtained results show that the achieved increase in asynchronous network-on-chip robustness has the potential to leverage this communication architecture solution as the main choice for the next generations of complex silicon devices on advanced nodes technologies such as 32 nm, 28 nm and below.
{"title":"H2A: A hardened asynchronous network on chip","authors":"Julian J. H. Pontes, Ney Laert Vilar Calazans, P. Vivet","doi":"10.1109/SBCCI.2013.6644865","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644865","url":null,"abstract":"One of the next challenges for asynchronous communication architectures is reliability, in the form of robustness to single event effects, when under the impact of particles generated by ionizing radiation. This occurs because technology down-scaling continuously increases the logic sensitivity of silicon devices to such effects. Contrary to what happens in synchronous circuits, delay variations induced by radiation usually have no impact on asynchronous quasi-delay insensitive (QDI) combinational logic blocks, but in case of storage logic, bit flips may corrupt the circuit state with no recovery solution, even when using asynchronous circuits. This work proposes a new set of hardening techniques against single event effects applicable to asynchronous networks-on-chip. It presents practical case studies of use for these techniques and evaluates them in close to real life situations. Obtained results show that the achieved increase in asynchronous network-on-chip robustness has the potential to leverage this communication architecture solution as the main choice for the next generations of complex silicon devices on advanced nodes technologies such as 32 nm, 28 nm and below.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122855179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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