Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644858
J. P. M. Brito, A. Rabaeijs
This paper presents an overview of the capabilities and different architectures for integrated temperature sensors in RFID tags using CMOS technology. A feasibility study for the integration of temperature sensors in RFID tags is described. The study focuses on four topologies to make temperature measurements and compare them regarding power, temperature range, accuracy, resolution and technology node. Measurement results of a test structure based on a potential proportional to absolute temperature (Vptat) fabricated in deep-submicron CMOS technology is presented and discussed.
{"title":"CMOS smart temperature sensors for RFID applications","authors":"J. P. M. Brito, A. Rabaeijs","doi":"10.1109/SBCCI.2013.6644858","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644858","url":null,"abstract":"This paper presents an overview of the capabilities and different architectures for integrated temperature sensors in RFID tags using CMOS technology. A feasibility study for the integration of temperature sensors in RFID tags is described. The study focuses on four topologies to make temperature measurements and compare them regarding power, temperature range, accuracy, resolution and technology node. Measurement results of a test structure based on a potential proportional to absolute temperature (Vptat) fabricated in deep-submicron CMOS technology is presented and discussed.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124032373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644889
L. Nunes, R. Reis
This work presents two techniques to define and treat areas that have high interconnection demand in the design of VLSI circuits, during global routing. These techniques are applied in two steps over all global routing flow. The first technique is executed in the pre-routing phase, where are identified regions with a high interconnection density, (there is a large number of sources or destinations reducing its ability to allocate interconnections); the second technique is applied in the iterative routing phase, identifying and protecting those regions from having high congestion, by cost pre-allocation techniques. Three cost pre-allocation parameters were identified and their values are defined on-the-fly, by functions, described in this paper. These techniques were included in an existing global routing flow, called GR-WL, to validate the impact of its implementation, through the extraction of three global routing metrics: wirelength, total value of maximum overflow (TOF) and maximum obtained overflow (MOF). By running experiments using these techniques, total congestion reduction was up to 16%. The results are more relevant when using benchmark circuits for which there is still no valid solutions in the literature. Furthermore, the running times achieved were up to 30% faster when compared to the reference implementation, with a maximum impact of 1.39% in the total wirelength.
{"title":"Global routing congestion reduction with cost allocation look-ahead","authors":"L. Nunes, R. Reis","doi":"10.1109/SBCCI.2013.6644889","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644889","url":null,"abstract":"This work presents two techniques to define and treat areas that have high interconnection demand in the design of VLSI circuits, during global routing. These techniques are applied in two steps over all global routing flow. The first technique is executed in the pre-routing phase, where are identified regions with a high interconnection density, (there is a large number of sources or destinations reducing its ability to allocate interconnections); the second technique is applied in the iterative routing phase, identifying and protecting those regions from having high congestion, by cost pre-allocation techniques. Three cost pre-allocation parameters were identified and their values are defined on-the-fly, by functions, described in this paper. These techniques were included in an existing global routing flow, called GR-WL, to validate the impact of its implementation, through the extraction of three global routing metrics: wirelength, total value of maximum overflow (TOF) and maximum obtained overflow (MOF). By running experiments using these techniques, total congestion reduction was up to 16%. The results are more relevant when using benchmark circuits for which there is still no valid solutions in the literature. Furthermore, the running times achieved were up to 30% faster when compared to the reference implementation, with a maximum impact of 1.39% in the total wirelength.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130970136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644873
Mayler G. A. Martins, F. Marranghello, J. Friedman, A. Sahakian, R. Ribas, A. Reis
This paper proposes an algorithm to synthesize combinational circuits based on spin diode logic technology. Spin diode is a magnetoresistive semiconductor heterojunction device which allows for a binary current based logic. The proposed algorithm takes the advantages of the functional composition (FC) approach to obtain fanout free network implementations with the minimum number of spin diodes. Experimental results have shown that the new proposal obtains better results when compared to the state-of-the-art algorithms that focus on traditional CMOS technology adapted to this new approach.
{"title":"Spin diode network synthesis using functional composition","authors":"Mayler G. A. Martins, F. Marranghello, J. Friedman, A. Sahakian, R. Ribas, A. Reis","doi":"10.1109/SBCCI.2013.6644873","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644873","url":null,"abstract":"This paper proposes an algorithm to synthesize combinational circuits based on spin diode logic technology. Spin diode is a magnetoresistive semiconductor heterojunction device which allows for a binary current based logic. The proposed algorithm takes the advantages of the functional composition (FC) approach to obtain fanout free network implementations with the minimum number of spin diodes. Experimental results have shown that the new proposal obtains better results when compared to the state-of-the-art algorithms that focus on traditional CMOS technology adapted to this new approach.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121502176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644857
Jan Heisswolf, Simon Bischof, Michael Rückauer, J. Becker
Networks on Chip (NoC) have emerged as a promising interconnection technology for scalable many-core architectures. Proposed NoC-architectures and topologies often assume uniform distribution of traffic, where all tiles produce and consume the same amount of data. However, even in homogeneous many-core architectures the Network on Chip is used to access peripheral buses and memory controllers for off-chip memory access. These components can consume and generate a significant part of the overall traffic, thus having higher bandwidth requirements than processing tiles. In this work we propose High Bandwidth Routers replacing conventional routers within the NoC at the positions, where components with high bandwidth requirements are attached. A High Bandwidth Router design is proposed and investigated with respect to performance and implementation costs. The position of memory nodes within a tiled architecture is analyzed. The results show a significant improvement of throughput and reduction of latency for memory communication, with moderate additional implementation costs.
{"title":"Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers","authors":"Jan Heisswolf, Simon Bischof, Michael Rückauer, J. Becker","doi":"10.1109/SBCCI.2013.6644857","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644857","url":null,"abstract":"Networks on Chip (NoC) have emerged as a promising interconnection technology for scalable many-core architectures. Proposed NoC-architectures and topologies often assume uniform distribution of traffic, where all tiles produce and consume the same amount of data. However, even in homogeneous many-core architectures the Network on Chip is used to access peripheral buses and memory controllers for off-chip memory access. These components can consume and generate a significant part of the overall traffic, thus having higher bandwidth requirements than processing tiles. In this work we propose High Bandwidth Routers replacing conventional routers within the NoC at the positions, where components with high bandwidth requirements are attached. A High Bandwidth Router design is proposed and investigated with respect to performance and implementation costs. The position of memory nodes within a tiled architecture is analyzed. The results show a significant improvement of throughput and reduction of latency for memory communication, with moderate additional implementation costs.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128309698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644874
Pedro F. G. da Silva, E. G. Lima
Crest factor reduction (CFR) is a technique that is commonly used for the linearization of power amplifiers (PAs) for mobile communication systems. In published works containing the use of CFR, it is assumed a priori that the inclusion of CFR will be beneficial, and the main objective is to achieve improvements in the processes of parameter identification or technique implementation. The main contribution of this work is to consolidate a criterion to determine whether is positive or not to linearize a PA through the use of CFR based on a hard clipping limiter followed by a filter. The criterion is then validated through computational simulations performed on a PA modeled by a Wiener cascade and excited by a 3GPP WCDMA signal having a PAPR of 12 dB. It is verified that, in this example, the criterion indicates that the application of CFR is beneficial, which is confirmed by an increase of 1.8 dB in average output power.
{"title":"Design of crest factor reduction techniques based on clipping and filtering for wireless communications systems","authors":"Pedro F. G. da Silva, E. G. Lima","doi":"10.1109/SBCCI.2013.6644874","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644874","url":null,"abstract":"Crest factor reduction (CFR) is a technique that is commonly used for the linearization of power amplifiers (PAs) for mobile communication systems. In published works containing the use of CFR, it is assumed a priori that the inclusion of CFR will be beneficial, and the main objective is to achieve improvements in the processes of parameter identification or technique implementation. The main contribution of this work is to consolidate a criterion to determine whether is positive or not to linearize a PA through the use of CFR based on a hard clipping limiter followed by a filter. The criterion is then validated through computational simulations performed on a PA modeled by a Wiener cascade and excited by a 3GPP WCDMA signal having a PAPR of 12 dB. It is verified that, in this example, the criterion indicates that the application of CFR is beneficial, which is confirmed by an increase of 1.8 dB in average output power.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127741268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644850
Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum
Three dimensional Multiprocessor System-on-Chip (3D-MPSoC) adoption. It is characterized by the integration of a large amount of hardware components on a single multilayer chip. However, heating is one of the major pitfalls of the 3D-MPSoCs. Three dimensional Network-on-Chip (3D-NoC) is used as the communication structure of 3D-MPSoCs. Its main role in system operation and performance makes the optimal 3D-NoC design a critical task. Final 3D-NoC configuration must fulfill all the application requirements and heating constraints of the system. Topology and mapping are some of the most critical parameters in 3D-NoC design, strongly influencing the 3D-MPSoC performance and cost. 3D-NoC topology and mapping has been solved for single application systems on homogeneous 3D-NoCs using single and multi-objective optimization algorithms. In this paper we use a multi-objective immune algorithm (MIA), to solve the multi-application 3D-NoC topology and mapping problems. Latency and power consumption are adopted as the target multi-objective functions constrained by the heating function. Our strategy has been applied on 8 3D-MPSoC benchmarks. Their final 3D-NoC configurations have up to 73% power and 42% latency enhancement when compared to previous reported results.
{"title":"An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs","authors":"Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum","doi":"10.1109/SBCCI.2013.6644850","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644850","url":null,"abstract":"Three dimensional Multiprocessor System-on-Chip (3D-MPSoC) adoption. It is characterized by the integration of a large amount of hardware components on a single multilayer chip. However, heating is one of the major pitfalls of the 3D-MPSoCs. Three dimensional Network-on-Chip (3D-NoC) is used as the communication structure of 3D-MPSoCs. Its main role in system operation and performance makes the optimal 3D-NoC design a critical task. Final 3D-NoC configuration must fulfill all the application requirements and heating constraints of the system. Topology and mapping are some of the most critical parameters in 3D-NoC design, strongly influencing the 3D-MPSoC performance and cost. 3D-NoC topology and mapping has been solved for single application systems on homogeneous 3D-NoCs using single and multi-objective optimization algorithms. In this paper we use a multi-objective immune algorithm (MIA), to solve the multi-application 3D-NoC topology and mapping problems. Latency and power consumption are adopted as the target multi-objective functions constrained by the heating function. Our strategy has been applied on 8 3D-MPSoC benchmarks. Their final 3D-NoC configurations have up to 73% power and 42% latency enhancement when compared to previous reported results.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122423934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644866
L. Z. Pieper, E. Costa, J. Monteiro
This paper addresses the design of efficient 2's complement 64-bit array multipliers. We propose the combination of radix-2m dedicated multiplier blocks and adder compressors that leads to the reduction of partial product lines, and hence to the higher performance and least power consumption. The flexibility of the architecture allows for the easy construction of multipliers for different values of m. With the use of optimized radix-2m dedicated multiplication blocks the multiplication can be naturally extended up for radix-256 multiplication. Since in the radix-2m multiplier the number of partial lines is reduced, by the multiplication of m bits at a time, we have used a combination of 4:2, 8:2 and 16:2 adder compressors in order to speed-up the addition of the simultaneous operands. We present results of area, delay and power consumption by using SIS and SLS (Switch Level Simulator) tools. The results show that combining the use of dedicated multiplier modules with adder compressors the radix-2m array multipliers are more efficient in terms of delay and power consumption when compared with both a Radix-2m array multiplier with Ripple Carry Adders (RCA) in the partial product lines, previously presented in literature, and the Modified Booth multiplier.
{"title":"Combination of radix-2m multiplier blocks and adder compressors for the design of efficient 2's complement 64-bit array multipliers","authors":"L. Z. Pieper, E. Costa, J. Monteiro","doi":"10.1109/SBCCI.2013.6644866","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644866","url":null,"abstract":"This paper addresses the design of efficient 2's complement 64-bit array multipliers. We propose the combination of radix-2m dedicated multiplier blocks and adder compressors that leads to the reduction of partial product lines, and hence to the higher performance and least power consumption. The flexibility of the architecture allows for the easy construction of multipliers for different values of m. With the use of optimized radix-2m dedicated multiplication blocks the multiplication can be naturally extended up for radix-256 multiplication. Since in the radix-2m multiplier the number of partial lines is reduced, by the multiplication of m bits at a time, we have used a combination of 4:2, 8:2 and 16:2 adder compressors in order to speed-up the addition of the simultaneous operands. We present results of area, delay and power consumption by using SIS and SLS (Switch Level Simulator) tools. The results show that combining the use of dedicated multiplier modules with adder compressors the radix-2m array multipliers are more efficient in terms of delay and power consumption when compared with both a Radix-2m array multiplier with Ripple Carry Adders (RCA) in the partial product lines, previously presented in literature, and the Modified Booth multiplier.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128090995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644867
A. L. P. Marciano, Andre B. Oliveira, J. Nacif, O. V. Neto
This paper describes the complete implementation of an efficient FPGA in quantum-dot cellular automata (QCA). FPGAs are reconfigurable digital devices which are extensively used in a wide range of industry applications. QCA is a promising nanotechnology able to overcome the limits of current CMOS technology. QCA technology consists of a group of cells which, when combined and arranged in a particular way, are able to perform computational functions. QCA technology transfers information by means of the polarization state of various cells in contrast to traditional computers, which use the flow of electrical current to transfer information. We propose an area efficient 4×1 multiplex-based Configurable Logic Block (CLB). We also propose a novel routing technique that is able to connect CLBs located at three different range groups. The proposed CLB and routing elements can be externally programmable by the user, giving rise to the desired digital circuit. We present QCADesigner simulation results for a 2×2 CLB FPGA.
{"title":"An efficient FPGA implementation in quantum-dot cellular automata","authors":"A. L. P. Marciano, Andre B. Oliveira, J. Nacif, O. V. Neto","doi":"10.1109/SBCCI.2013.6644867","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644867","url":null,"abstract":"This paper describes the complete implementation of an efficient FPGA in quantum-dot cellular automata (QCA). FPGAs are reconfigurable digital devices which are extensively used in a wide range of industry applications. QCA is a promising nanotechnology able to overcome the limits of current CMOS technology. QCA technology consists of a group of cells which, when combined and arranged in a particular way, are able to perform computational functions. QCA technology transfers information by means of the polarization state of various cells in contrast to traditional computers, which use the flow of electrical current to transfer information. We propose an area efficient 4×1 multiplex-based Configurable Logic Block (CLB). We also propose a novel routing technique that is able to connect CLBs located at three different range groups. The proposed CLB and routing elements can be externally programmable by the user, giving rise to the desired digital circuit. We present QCADesigner simulation results for a 2×2 CLB FPGA.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128374863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644890
Guilherme H. K. Martini, J. A. Fabro
This paper presents a digital hybrid filter which can be applied to power electronics control systems. The filter suppresses high-frequency noises while still providing a fast step response, its weighting algorithm is based on an open-loop criteria that analyses the discrepancy between an Infinite Impulse Response (IIR) and a Moving Average (MA) filter. The filter performance is compared to classical implementations through a step response and a Signal-to-Noise Ratio (SNR) analysis. The computational cost is also evaluated to verify its use on hard realtime systems. To evaluate the proposed filter, experiments were made on a microcontroller-based high-power frequency inverter with hard-time constraints, ensuring its applicability.
{"title":"Hybrid filter for high-power converter systems","authors":"Guilherme H. K. Martini, J. A. Fabro","doi":"10.1109/SBCCI.2013.6644890","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644890","url":null,"abstract":"This paper presents a digital hybrid filter which can be applied to power electronics control systems. The filter suppresses high-frequency noises while still providing a fast step response, its weighting algorithm is based on an open-loop criteria that analyses the discrepancy between an Infinite Impulse Response (IIR) and a Moving Average (MA) filter. The filter performance is compared to classical implementations through a step response and a Signal-to-Noise Ratio (SNR) analysis. The computational cost is also evaluated to verify its use on hard realtime systems. To evaluate the proposed filter, experiments were made on a microcontroller-based high-power frequency inverter with hard-time constraints, ensuring its applicability.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"347 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133154208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-10-24DOI: 10.1109/SBCCI.2013.6644887
Kim A. Escobar, R. Ribas
Quantum-dot cellular automata (QCA) represents a very promising emerging technology, which has been claimed to be faster and smaller than the most traditional CMOS technology. In the last years, important advances have been made in QCA designs, since the introduction of basic logic gates until the insertion of more complex circuits, like adders. However, new paradigms and challenges have emerged in this sense. The implementation of the basic blocks necessary to build parallel prefix adders (PPAs) is presented in this work. These blocks have been evaluated and validated through the construction of a 4-bit PPA. The proposed adder implementation is compared to other QCA adders available in the literature.
{"title":"Parallel prefix adder design using quantum-dot cellular automata","authors":"Kim A. Escobar, R. Ribas","doi":"10.1109/SBCCI.2013.6644887","DOIUrl":"https://doi.org/10.1109/SBCCI.2013.6644887","url":null,"abstract":"Quantum-dot cellular automata (QCA) represents a very promising emerging technology, which has been claimed to be faster and smaller than the most traditional CMOS technology. In the last years, important advances have been made in QCA designs, since the introduction of basic logic gates until the insertion of more complex circuits, like adders. However, new paradigms and challenges have emerged in this sense. The implementation of the basic blocks necessary to build parallel prefix adders (PPAs) is presented in this work. These blocks have been evaluated and validated through the construction of a 4-bit PPA. The proposed adder implementation is compared to other QCA adders available in the literature.","PeriodicalId":203604,"journal":{"name":"2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132357453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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