Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398200
K. Wong, V. P. Singh, J.S. Rustagi
The application of design of experiments in manufacturing has been proposed and developed by Genichi Taguchi for quality improvement. An automated design of experiment package (ADOE) has been developed for this purpose. The scope and application of ADOE in manufacturing development and research, particularly for high technology industries are described. This package differs from other available packages in that it deals with both classical and Taguchi methods for quality improvements. Experimental data can be analyzed in several alternative ways, including graphical techniques. The extension of Taguchi's signal-to-noise ratio has been made for experiments, with several responses having different performance objectives. The package allows the engineer to bypass analysis, if so desired, for obtaining decisions for process optimization.<>
{"title":"Statistical methods in manufacturing","authors":"K. Wong, V. P. Singh, J.S. Rustagi","doi":"10.1109/IEMT.1993.398200","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398200","url":null,"abstract":"The application of design of experiments in manufacturing has been proposed and developed by Genichi Taguchi for quality improvement. An automated design of experiment package (ADOE) has been developed for this purpose. The scope and application of ADOE in manufacturing development and research, particularly for high technology industries are described. This package differs from other available packages in that it deals with both classical and Taguchi methods for quality improvements. Experimental data can be analyzed in several alternative ways, including graphical techniques. The extension of Taguchi's signal-to-noise ratio has been made for experiments, with several responses having different performance objectives. The package allows the engineer to bypass analysis, if so desired, for obtaining decisions for process optimization.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117067365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398199
P. Nixon, J. Conway, J. Maimon
The requirements of semiconductor device manufacturing and defense industry needs are continually demanding tighter process control and reduced levels of defects. Statistical process control (SPC) techniques are required to meet these requirements. The VLSI pilot line has implemented SPC control in manufacturing on all products. Online charts are used to identify and correct problems as quickly as possible and capability indices are used to drive continuous improvement.<>
{"title":"Statistical process control and the drive for six sigma in a VLSI pilot line","authors":"P. Nixon, J. Conway, J. Maimon","doi":"10.1109/IEMT.1993.398199","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398199","url":null,"abstract":"The requirements of semiconductor device manufacturing and defense industry needs are continually demanding tighter process control and reduced levels of defects. Statistical process control (SPC) techniques are required to meet these requirements. The VLSI pilot line has implemented SPC control in manufacturing on all products. Online charts are used to identify and correct problems as quickly as possible and capability indices are used to drive continuous improvement.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121431612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398159
K. Tai
Summary form only given. As the design rule gap between VLSI and packaging technology widens, the mismatch of the electrical environments between on-chip and off-chip becomes more and more serious. Multichip module (MCM) technology has the potential to address these issues. The key focus is to bring chips close together, so that the on-chip electrical environment can be preserved in the inter-chip interconnection. The combination of flip-chip attachment and the fine line interconnection is the best way to achieve this. By connecting chips in compact modules, with new chip I/O design to fit the new interconnection environment, this technology can dramatically improve system speeds. It can also provide the high interconnect density to support highly parallel architectures and drastically reduce power requirements and size to support miniaturization for portable electronics.<>
{"title":"Low cost, high volume applications to drive high performance Si-on-Si MCM","authors":"K. Tai","doi":"10.1109/IEMT.1993.398159","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398159","url":null,"abstract":"Summary form only given. As the design rule gap between VLSI and packaging technology widens, the mismatch of the electrical environments between on-chip and off-chip becomes more and more serious. Multichip module (MCM) technology has the potential to address these issues. The key focus is to bring chips close together, so that the on-chip electrical environment can be preserved in the inter-chip interconnection. The combination of flip-chip attachment and the fine line interconnection is the best way to achieve this. By connecting chips in compact modules, with new chip I/O design to fit the new interconnection environment, this technology can dramatically improve system speeds. It can also provide the high interconnect density to support highly parallel architectures and drastically reduce power requirements and size to support miniaturization for portable electronics.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"117 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127413009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398213
H. Katô, K. Ikuzaki, M. Tsujita, K. Nakata, T. Kobayashi, Y. Sano
A new method for measuring the tin content of flip-chip solder bumps is described. This method uses a combination of gravimetric analysis and fluorescent X-ray spectrometry, which allows it to measure low Sn ratio of less than 2%. It also improves the repeatability to 0.2% compared with 4.3% for conventional methods that use integrated circuit piezoelectric (ICP) atomic emission spectrometry. This method also reduces the measurement time by 75%.<>
{"title":"A new method for measuring the tin content of flip-chip solder bumps","authors":"H. Katô, K. Ikuzaki, M. Tsujita, K. Nakata, T. Kobayashi, Y. Sano","doi":"10.1109/IEMT.1993.398213","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398213","url":null,"abstract":"A new method for measuring the tin content of flip-chip solder bumps is described. This method uses a combination of gravimetric analysis and fluorescent X-ray spectrometry, which allows it to measure low Sn ratio of less than 2%. It also improves the repeatability to 0.2% compared with 4.3% for conventional methods that use integrated circuit piezoelectric (ICP) atomic emission spectrometry. This method also reduces the measurement time by 75%.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398184
P. Raulefs, R. Bhatt, R. Culley, William Guyon, N. Hakim, G. Kumar, G. Scott, D. Sikka
Managing a manufacturing process involves monitoring, diagnosis, and control. An architecture that merges existing data collection and analysis systems with AI-based pattern-detection, interpretation, and decision-making facilities is described. Functions are performed by agents that distribute tasks and control in a way that can be closely tailored to the manufacturing environment. Technical principles and the development strategy are discussed, together with experiences on already operating components.<>
{"title":"Integrated computer-assisted process management","authors":"P. Raulefs, R. Bhatt, R. Culley, William Guyon, N. Hakim, G. Kumar, G. Scott, D. Sikka","doi":"10.1109/IEMT.1993.398184","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398184","url":null,"abstract":"Managing a manufacturing process involves monitoring, diagnosis, and control. An architecture that merges existing data collection and analysis systems with AI-based pattern-detection, interpretation, and decision-making facilities is described. Functions are performed by agents that distribute tasks and control in a way that can be closely tailored to the manufacturing environment. Technical principles and the development strategy are discussed, together with experiences on already operating components.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123388437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398175
K. Sakakibara, T. Mikazuki
A board for measuring the properties of noise in the power/ground plane of high-speed system is described. By using this board it is found that one can quantitatively evaluate the noise diffused from a noise source, but one can estimate the effects of simultaneous switching noise by superimposing the noise from each of the devices, and that the speed of noise propagation depends on the impedance of the ground plane.<>
{"title":"Switching noise in power and ground planes with ECL logic","authors":"K. Sakakibara, T. Mikazuki","doi":"10.1109/IEMT.1993.398175","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398175","url":null,"abstract":"A board for measuring the properties of noise in the power/ground plane of high-speed system is described. By using this board it is found that one can quantitatively evaluate the noise diffused from a noise source, but one can estimate the effects of simultaneous switching noise by superimposing the noise from each of the devices, and that the speed of noise propagation depends on the impedance of the ground plane.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123657598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398179
C. Narayan, S. Purushothaman
A highly flexible and cost competitive method to fabricate microelectronic packages that require thin film interconnections is described. The method involves fabricating thin film metal/polymer structures multi-up on a reusable temporary glass carrier and later transferring the thin film stack onto product substrates of choice. The final product substrate can be silicon, co-fired alumina or glass-ceramic, aluminum nitride, diamond or a printed wiring board. Optionally, one can also use the released thin film decal as a flexible high wireability interconnect by itself, as an interposer, or in applications like wafer level testing for known good die (KGD). The thin film wiring structure can be fabricated multi-up on large area glass plates using large format tools to significantly reduce cost.<>
{"title":"Thin film transfer process for low cost MCM's","authors":"C. Narayan, S. Purushothaman","doi":"10.1109/IEMT.1993.398179","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398179","url":null,"abstract":"A highly flexible and cost competitive method to fabricate microelectronic packages that require thin film interconnections is described. The method involves fabricating thin film metal/polymer structures multi-up on a reusable temporary glass carrier and later transferring the thin film stack onto product substrates of choice. The final product substrate can be silicon, co-fired alumina or glass-ceramic, aluminum nitride, diamond or a printed wiring board. Optionally, one can also use the released thin film decal as a flexible high wireability interconnect by itself, as an interposer, or in applications like wafer level testing for known good die (KGD). The thin film wiring structure can be fabricated multi-up on large area glass plates using large format tools to significantly reduce cost.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122960388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398207
R. Olson, J. Yira
Parylene coating tests of circuits produced with various no-clean soldering fluxes are conducted to determine the impact of no-clean circuit processing on the Parylene coatability of these boards. The properties and characteristics of Parylene conformal coating are described. Surface insulation resistance test procedures and results for no-clean flux/no-clean soldered and Parylene coated circuit samples are summarized.<>
{"title":"Relative compatibility of Parylene conformal coatings with no-clean flux residues","authors":"R. Olson, J. Yira","doi":"10.1109/IEMT.1993.398207","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398207","url":null,"abstract":"Parylene coating tests of circuits produced with various no-clean soldering fluxes are conducted to determine the impact of no-clean circuit processing on the Parylene coatability of these boards. The properties and characteristics of Parylene conformal coating are described. Surface insulation resistance test procedures and results for no-clean flux/no-clean soldered and Parylene coated circuit samples are summarized.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126226735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398168
C.E. Yeh, J.C. Cheng, Kwan Y. Wong
A real-time feedback control system is being developed in a wafer fabrication line at IBM's San Jose plant. The goal of the system is to minimize the alignment drifts, and hence to increase wafer yields and chip quality, by automatically adjusting the set points of the exposure machines. The major challenges of implementing the feedback control system are: (1) no modification on the existing equipment, (2) minimum interruptions to the production operation, (3) asynchronous operations and communications of multiple computers, (4) computational algorithm of new set points, (5) large volume of data, (6) data grouping, and (7) data filtering. These challenges and the methods taken to address them are discussed.<>
{"title":"Implementation challenges of a feedback control system for wafer fabrication","authors":"C.E. Yeh, J.C. Cheng, Kwan Y. Wong","doi":"10.1109/IEMT.1993.398168","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398168","url":null,"abstract":"A real-time feedback control system is being developed in a wafer fabrication line at IBM's San Jose plant. The goal of the system is to minimize the alignment drifts, and hence to increase wafer yields and chip quality, by automatically adjusting the set points of the exposure machines. The major challenges of implementing the feedback control system are: (1) no modification on the existing equipment, (2) minimum interruptions to the production operation, (3) asynchronous operations and communications of multiple computers, (4) computational algorithm of new set points, (5) large volume of data, (6) data grouping, and (7) data filtering. These challenges and the methods taken to address them are discussed.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"33 1-2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116716845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398206
J. A. Steele, K. B. Gould, D.G. Siden, H. Simmons
The qualification of a no-clean solder paste eliminate the use of chlorofluorocarbons (CFCs) in semiconductor manufacturing. The no-clean also reduces chemical usage and capital equipment needs. The no-clean paste selection process proves successful. Qualification by comparison provides an effective way to ensure the needed reliability.<>
{"title":"Chlorinated solvent elimination in chip capacitor attach using qualification by comparison","authors":"J. A. Steele, K. B. Gould, D.G. Siden, H. Simmons","doi":"10.1109/IEMT.1993.398206","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398206","url":null,"abstract":"The qualification of a no-clean solder paste eliminate the use of chlorofluorocarbons (CFCs) in semiconductor manufacturing. The no-clean also reduces chemical usage and capital equipment needs. The no-clean paste selection process proves successful. Qualification by comparison provides an effective way to ensure the needed reliability.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128186300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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