Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398161
P. Clot
The author explains how two original designs using chip-on-board technology have been completed and pushed into production. Both are made on the same kind of modified multilayer glass epoxy. One is equipped with J lead output pins, allowing the mounting of silicon dice on both faces of the printed circuit board; the second supports dice on the top only, the bottom face being reserved for direct surface mount device (SMD) soldering carefully prepared for this purpose. Design rules, dimensions regarding Jedec standard, mounting procedures as well as qualification program and test approach are described. Considerations on the choice of dice epoxy coatings are explained. Dispensing and machining are defined to allow pick and place handling by automatic machine.<>
{"title":"Low cost multi-chip modules based on single and double sided chip-on-board modules following Jedec standard specifications","authors":"P. Clot","doi":"10.1109/IEMT.1993.398161","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398161","url":null,"abstract":"The author explains how two original designs using chip-on-board technology have been completed and pushed into production. Both are made on the same kind of modified multilayer glass epoxy. One is equipped with J lead output pins, allowing the mounting of silicon dice on both faces of the printed circuit board; the second supports dice on the top only, the bottom face being reserved for direct surface mount device (SMD) soldering carefully prepared for this purpose. Design rules, dimensions regarding Jedec standard, mounting procedures as well as qualification program and test approach are described. Considerations on the choice of dice epoxy coatings are explained. Dispensing and machining are defined to allow pick and place handling by automatic machine.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"22 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122219787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398194
Mario Villacourt, M. Mahaney
The Bayesian Reliability Testing method is used for the estimation of the shape and scale parameters of an inverted gamma prior distribution of the mean time between failures (MTBF) for equipment having an exponential time to failure distribution. This method allows the use of existing failure data of the equipment in question, provided certain conditions are satisfied. The Bayesian method is usable to update the prior distribution as new failure data becomes available. Through this updating process, confidence is built in to reliability demonstrations.<>
{"title":"Designing a reliability demonstration test on a lithography expose tool using Bayesian techniques","authors":"Mario Villacourt, M. Mahaney","doi":"10.1109/IEMT.1993.398194","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398194","url":null,"abstract":"The Bayesian Reliability Testing method is used for the estimation of the shape and scale parameters of an inverted gamma prior distribution of the mean time between failures (MTBF) for equipment having an exponential time to failure distribution. This method allows the use of existing failure data of the equipment in question, provided certain conditions are satisfied. The Bayesian method is usable to update the prior distribution as new failure data becomes available. Through this updating process, confidence is built in to reliability demonstrations.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128617449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398158
P.E. Rogren
Laminate technology has progressed to the point where it is capable of producing multichip module (MCM) substrates that can compete favorably with both cofire ceramic and thin film. By virtue of the properties of the materials set and flexibility of the process, laminate based MCM offer superior electrical performance. Laminates can be expected to be faster than either cofire ceramic or thin film and will be significantly less noise than ceramic based MCMs. In terms of thermal performance, several levels of thermal enhancements available on laminate substrates keep pace with similar methods available for ceramic or metal packages.<>
{"title":"The current state of laminate based, molded MCM technology","authors":"P.E. Rogren","doi":"10.1109/IEMT.1993.398158","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398158","url":null,"abstract":"Laminate technology has progressed to the point where it is capable of producing multichip module (MCM) substrates that can compete favorably with both cofire ceramic and thin film. By virtue of the properties of the materials set and flexibility of the process, laminate based MCM offer superior electrical performance. Laminates can be expected to be faster than either cofire ceramic or thin film and will be significantly less noise than ceramic based MCMs. In terms of thermal performance, several levels of thermal enhancements available on laminate substrates keep pace with similar methods available for ceramic or metal packages.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133377494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398166
N. Godfrey, Hua Li, W. Marcy
In the semiconductor manufacturing industry, many systems to be controlled are highly nonlinear and dynamic. A demonstration project, real-time control of a beam balancing system based on fuzzy logic, is described. This prototyping system can be operated automatically by the execution of a fuzzy control algorithm. Unlike most of the conventional and optimal control algorithms, this fuzzy logic controller requires no explicit system parameters. It is characterized by its simplicity and robustness.<>
{"title":"A demonstration system based on a fuzzy logic controller","authors":"N. Godfrey, Hua Li, W. Marcy","doi":"10.1109/IEMT.1993.398166","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398166","url":null,"abstract":"In the semiconductor manufacturing industry, many systems to be controlled are highly nonlinear and dynamic. A demonstration project, real-time control of a beam balancing system based on fuzzy logic, is described. This prototyping system can be operated automatically by the execution of a fuzzy control algorithm. Unlike most of the conventional and optimal control algorithms, this fuzzy logic controller requires no explicit system parameters. It is characterized by its simplicity and robustness.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128532188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398195
Udi Efrat
Wafer dicing is one of the critical elements of the IC assembly process where improvements can make a major contribution to yield. Chipping (damage along the cut line inherent to the wafer dicing operation) has been identified by semiconductor manufacturers as a relevant area for improvement. A study of process factors that affect the magnitude of the chipping phenomenon is described. The goal is to explore the limits of the current equipment. Cursory experiments are conducted to zero-in on significant factors. During this phase, several factors that were considered major causes for chipping, are found to have no significant effect. A set of designed experiments is run. It identifies chipping sensitivity to process parameters and points at an operating window that improves cut quality. Field tests in production environment confirm the experimental results.<>
{"title":"Optimizing the wafer dicing process","authors":"Udi Efrat","doi":"10.1109/IEMT.1993.398195","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398195","url":null,"abstract":"Wafer dicing is one of the critical elements of the IC assembly process where improvements can make a major contribution to yield. Chipping (damage along the cut line inherent to the wafer dicing operation) has been identified by semiconductor manufacturers as a relevant area for improvement. A study of process factors that affect the magnitude of the chipping phenomenon is described. The goal is to explore the limits of the current equipment. Cursory experiments are conducted to zero-in on significant factors. During this phase, several factors that were considered major causes for chipping, are found to have no significant effect. A set of designed experiments is run. It identifies chipping sensitivity to process parameters and points at an operating window that improves cut quality. Field tests in production environment confirm the experimental results.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128826604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398208
S.M. Scheifers, C. Raleigh
A no clean flux process for flip chip on board is characterized for ionic flux residue and board contamination using a new cleanliness testing system. The benchmarking procedure establishes a correlation of flux residue to thermal shock reliability. Speciation and quantitation of ionic printed wiring board (PWB) constituents permits segregation of incoming board contamination from that caused by the flux. A process window to minimize defects and maximize reliability performance is developed. Methods for performing similar characterization and benchmarking of processes are presented.<>
{"title":"Flip chip on board (FCOB) process characterization","authors":"S.M. Scheifers, C. Raleigh","doi":"10.1109/IEMT.1993.398208","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398208","url":null,"abstract":"A no clean flux process for flip chip on board is characterized for ionic flux residue and board contamination using a new cleanliness testing system. The benchmarking procedure establishes a correlation of flux residue to thermal shock reliability. Speciation and quantitation of ionic printed wiring board (PWB) constituents permits segregation of incoming board contamination from that caused by the flux. A process window to minimize defects and maximize reliability performance is developed. Methods for performing similar characterization and benchmarking of processes are presented.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114635568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398174
S. Yamaguchi, Y. Ohno, H. Tomimuro
The authors describe a multichip module (MCM) having a copper-polyimide thin-film multilayer substrate that overcomes the problems of increased transmission loss at high frequencies maintaining crosstalk noise low, and the increased simultaneous switching noise with a larger number of LSI chips. The conductors are designed to be 10-/spl mu/m thick and 25-/spl mu/m wide to enable the transmission of high speed pulses at several Gb/s without decreasing the interconnection density while maintaining crosstalk noise as low as -30 dB. The dielectric thickness between the power and ground layers making up the current loop in the ceramic substrate is designed to be 50/spl mu/m, which gives rise to a low effective inductance.<>
作者描述了一种多芯片模块(MCM)，它具有铜聚酰亚胺薄膜多层衬底，克服了高频传输损耗增加的问题，保持了较低的串扰噪声，以及大量LSI芯片同时增加的开关噪声。导线设计为10-/spl mu/m厚，25-/spl mu/m宽，可以在不降低互连密度的情况下传输数Gb/s的高速脉冲，同时保持串扰噪声低至-30 dB。在陶瓷基板中，构成电流回路的功率层和接地层之间的介电厚度被设计为50/spl μ m /m，这导致有效电感较低。
{"title":"Packaging technology for high-speed multichip module using copper-polyimide thin film multilayer substrate [for B-ISDN]","authors":"S. Yamaguchi, Y. Ohno, H. Tomimuro","doi":"10.1109/IEMT.1993.398174","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398174","url":null,"abstract":"The authors describe a multichip module (MCM) having a copper-polyimide thin-film multilayer substrate that overcomes the problems of increased transmission loss at high frequencies maintaining crosstalk noise low, and the increased simultaneous switching noise with a larger number of LSI chips. The conductors are designed to be 10-/spl mu/m thick and 25-/spl mu/m wide to enable the transmission of high speed pulses at several Gb/s without decreasing the interconnection density while maintaining crosstalk noise as low as -30 dB. The dielectric thickness between the power and ground layers making up the current loop in the ceramic substrate is designed to be 50/spl mu/m, which gives rise to a low effective inductance.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125351921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398189
D. Solomon, R. Adams, M. Lanka, K. Berry, S. El-Kilani
The performance of thin film interconnects is dependent upon successful interaction between design and the fabrication process. The functional verification of process tolerances to achieve the originally simulated design requirements is addressed. Variational analysis results about the nominal design value are presented and compared with initial simulation results. Interconnect capacitance and impedance variations as a function of conductor and dielectric geometry are shown. The analysis shows that the process is capable of giving an impedance within 10% of the nominal design value.<>
{"title":"The effects of process variations on the performance of MCM-D interconnects","authors":"D. Solomon, R. Adams, M. Lanka, K. Berry, S. El-Kilani","doi":"10.1109/IEMT.1993.398189","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398189","url":null,"abstract":"The performance of thin film interconnects is dependent upon successful interaction between design and the fabrication process. The functional verification of process tolerances to achieve the originally simulated design requirements is addressed. Variational analysis results about the nominal design value are presented and compared with initial simulation results. Interconnect capacitance and impedance variations as a function of conductor and dielectric geometry are shown. The analysis shows that the process is capable of giving an impedance within 10% of the nominal design value.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126113325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398201
M. Sanderson, M. Shelton, S. Mulligan
The efforts of IBM Austin Industrial Business Center (AIBC) to adopt total productive maintenance (TPM) as the process for improving quality, increasing production and eliminating waste on the pull production lines (PPLs) are described. Over-all equipment effectiveness (OEE) is seen as the measurement for AIBC improvement activities. The initial introductory conversations with management and early pilot measurement activities are described. The data collection tools used and the resulting analysis of the data collected are shown. The initial benchmark activities are described. The authors describe how they obtained the necessary top-down commitment from management by showing the faults of pilot measurements.<>
{"title":"IBM Austin Industrial Business Center total productive maintenance - The beginning","authors":"M. Sanderson, M. Shelton, S. Mulligan","doi":"10.1109/IEMT.1993.398201","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398201","url":null,"abstract":"The efforts of IBM Austin Industrial Business Center (AIBC) to adopt total productive maintenance (TPM) as the process for improving quality, increasing production and eliminating waste on the pull production lines (PPLs) are described. Over-all equipment effectiveness (OEE) is seen as the measurement for AIBC improvement activities. The initial introductory conversations with management and early pilot measurement activities are described. The data collection tools used and the resulting analysis of the data collected are shown. The initial benchmark activities are described. The authors describe how they obtained the necessary top-down commitment from management by showing the faults of pilot measurements.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126360439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398190
T. Chung, J. Chang, A. Emamjomeh
Tape automated bonding (TAB) is an integrated circuit (IC) chip-level interconnect technology. An in-depth overview of TAB chip on board technology and related applications is presented. Key considerations of design, materials, assembly, and equipment for TAB chip on multichip module (MCM)-D are discussed in detail. The issues, pros and cons, problems and solutions, and guidelines are provided to examine a variety of applications. Examples of both face-up and flipped TAB chip on MCM-D applications are presented and discussed. Future trends of TAB technology are also discussed.<>
{"title":"Tape automated bonded chip on MCM-D","authors":"T. Chung, J. Chang, A. Emamjomeh","doi":"10.1109/IEMT.1993.398190","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398190","url":null,"abstract":"Tape automated bonding (TAB) is an integrated circuit (IC) chip-level interconnect technology. An in-depth overview of TAB chip on board technology and related applications is presented. Key considerations of design, materials, assembly, and equipment for TAB chip on multichip module (MCM)-D are discussed in detail. The issues, pros and cons, problems and solutions, and guidelines are provided to examine a variety of applications. Examples of both face-up and flipped TAB chip on MCM-D applications are presented and discussed. Future trends of TAB technology are also discussed.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126277465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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