Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398186
W. Trybula
The manufacturing community reacts to crises, directives from upper management and late orders by issuing "hot orders". This method of operating increases the priority for a particular product and expedites its flow through the factory. However, the impact of the schedule disruption on the remainder of the products' scheduled is unknown. A simulation of a medium sized electronics factory provides an opportunity to analyze the impact of this procedure on the jobs being processed. The effect of increasing the percentage of "hot" jobs on the remainder of the jobs being produced is examined. The results indicate that as the percentage of "hot" jobs increases, the time to process normal orders also increases. The establishment of an upper limit on "hot" orders will permit a factory to operate effectively and minimize disruptions.<>
{"title":"\"Hot\" jobs, bane or boon","authors":"W. Trybula","doi":"10.1109/IEMT.1993.398186","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398186","url":null,"abstract":"The manufacturing community reacts to crises, directives from upper management and late orders by issuing \"hot orders\". This method of operating increases the priority for a particular product and expedites its flow through the factory. However, the impact of the schedule disruption on the remainder of the products' scheduled is unknown. A simulation of a medium sized electronics factory provides an opportunity to analyze the impact of this procedure on the jobs being processed. The effect of increasing the percentage of \"hot\" jobs on the remainder of the jobs being produced is examined. The results indicate that as the percentage of \"hot\" jobs increases, the time to process normal orders also increases. The establishment of an upper limit on \"hot\" orders will permit a factory to operate effectively and minimize disruptions.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130575525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398162
D. Bender, A. M. Ferreira
Design guidelines, process steps and test results from fabrication of two 40-mm multichip module (MCM)-Cs using the latest thick materials and printing techniques are discussed. Two two LIC (line interface controller) modules are designed with two large ASICs (plus memory) and prototyped using thick film gold conductors with 3 mil line/space and 6 mil via criteria. The second prototype of the LIC module utilizes silver conductors at 5 mil line and gap to further reduce cost. The second module design uses more bare die (field programmable gate arrays and memory) for a much higher interconnect density but still uses existing design guidelines. It is believed that 4 mil vias can be achieved in production and will be developed for future designs require higher density. Diffusion patterning allows a 50% reduction (4-6 mil) in via size versus traditional printed vias (10-20 mil).<>
{"title":"Higher density using diffusion patterned vias and fine line printing","authors":"D. Bender, A. M. Ferreira","doi":"10.1109/IEMT.1993.398162","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398162","url":null,"abstract":"Design guidelines, process steps and test results from fabrication of two 40-mm multichip module (MCM)-Cs using the latest thick materials and printing techniques are discussed. Two two LIC (line interface controller) modules are designed with two large ASICs (plus memory) and prototyped using thick film gold conductors with 3 mil line/space and 6 mil via criteria. The second prototype of the LIC module utilizes silver conductors at 5 mil line and gap to further reduce cost. The second module design uses more bare die (field programmable gate arrays and memory) for a much higher interconnect density but still uses existing design guidelines. It is believed that 4 mil vias can be achieved in production and will be developed for future designs require higher density. Diffusion patterning allows a 50% reduction (4-6 mil) in via size versus traditional printed vias (10-20 mil).<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132873701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398171
L. Roszel
An existing dual C40 multichip module (MCM) design, constructed in thin film HDI on ceramic is compared with the design converted to a laminate interconnect. The resulting design combines the low cost laminate substrate with increased power distribution and fine interconnect geometries.<>
{"title":"Laminate substrates for high speed interconnect","authors":"L. Roszel","doi":"10.1109/IEMT.1993.398171","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398171","url":null,"abstract":"An existing dual C40 multichip module (MCM) design, constructed in thin film HDI on ceramic is compared with the design converted to a laminate interconnect. The resulting design combines the low cost laminate substrate with increased power distribution and fine interconnect geometries.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116109300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398180
K. Banerjee, S. Natarajan, B. Connor, J. Wittrock
From first principles a generic model which can be applied to a variety of problems associated with placement errors, which are not limited to overlapping features alone is generated. The same model with minor changes is used to predict what the tolerances on a die and bond stage should be, such that the die edge does not interfere with the edges of the cavity of the bond stage when it is placed in the stage. The model is verified with actual data, and proves to be quite accurate.<>
{"title":"A generic tolerance analysis model with illustrations for TAB bonding","authors":"K. Banerjee, S. Natarajan, B. Connor, J. Wittrock","doi":"10.1109/IEMT.1993.398180","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398180","url":null,"abstract":"From first principles a generic model which can be applied to a variety of problems associated with placement errors, which are not limited to overlapping features alone is generated. The same model with minor changes is used to predict what the tolerances on a die and bond stage should be, such that the die edge does not interfere with the edges of the cavity of the bond stage when it is placed in the stage. The model is verified with actual data, and proves to be quite accurate.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125129929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398204
Samuel H. Huang, Hongchao Zhang
Information about neural networks in manufacturing, which will provide some guidelines and references for the research and implementation is presented. The basic concepts of neural networks are briefly introduced. A survey of neural network applications in manufacturing is provided. The projection of future trends is given to help make decisions concerning neural networks implementation in manufacturing today and to aid in guiding research for tomorrow.<>
{"title":"Neural networks in manufacturing: A survey","authors":"Samuel H. Huang, Hongchao Zhang","doi":"10.1109/IEMT.1993.398204","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398204","url":null,"abstract":"Information about neural networks in manufacturing, which will provide some guidelines and references for the research and implementation is presented. The basic concepts of neural networks are briefly introduced. A survey of neural network applications in manufacturing is provided. The projection of future trends is given to help make decisions concerning neural networks implementation in manufacturing today and to aid in guiding research for tomorrow.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114776577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398221
J. Lau, J. Miremadi, J. Gleason, R. Haven, S. Ottoboni, S. Mimura
A no clean mass reflow process for 396-pin, 324-pin, and 225-pin over molded plastic pad array carriers (OMPAC) is presented. Emphasis is placed on the OMPAC assembly parameters, such as the design, material, and process of the packages and printed circuit board (PCB), solder paste, stencil design, printing technology, pick and place, mass reflow, and inspection. Cross sections and the "popcorn" effect of the OMPAC assembly are discussed.<>
{"title":"No clean mass reflow of large over molded plastic pad array carriers (OMPAC)","authors":"J. Lau, J. Miremadi, J. Gleason, R. Haven, S. Ottoboni, S. Mimura","doi":"10.1109/IEMT.1993.398221","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398221","url":null,"abstract":"A no clean mass reflow process for 396-pin, 324-pin, and 225-pin over molded plastic pad array carriers (OMPAC) is presented. Emphasis is placed on the OMPAC assembly parameters, such as the design, material, and process of the packages and printed circuit board (PCB), solder paste, stencil design, printing technology, pick and place, mass reflow, and inspection. Cross sections and the \"popcorn\" effect of the OMPAC assembly are discussed.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125867157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398197
A. Hu, Z. Zhang, E. Sachs, P. Renteln
The Run by Run (RbR) controller, combining the advantages both statistical process control (SPC) and automatic process control (APC) has been applied successfully to a technically mature epitaxy processes and is now being applied on the chemical-mechanical planarization (CMP process). Three quality metrics are defined and used as measurements of process improvement. The application procedure is divided into five stages, of which the implementation stages one and two have been performed. The data show that a system can be described by an equilibrium state, a transition period responsive to shifts in the input, but exhibiting substantial hysteresis. A transition period between different equilibrium states is clearly observable. The memory that the pad has due to previous recipe is also clearly demonstrated.<>
RbR (Run - by - Run)控制器结合了统计过程控制(SPC)和自动过程控制(APC)的优点，已成功应用于技术成熟的外延工艺，目前正应用于化学-机械平面化(CMP)工艺。定义了三个质量度量标准，并将其用作过程改进的度量。申请程序分为五个阶段，其中实施阶段一和实施阶段二已经完成。数据表明，系统可以用平衡状态来描述，这是一个响应输入位移的过渡期，但表现出明显的滞后。在不同的平衡状态之间有一个过渡时期，是可以清楚地观察到的。由于之前的配方，pad的内存也被清楚地展示出来。
{"title":"Application of Run by Run controller to the chemical-mechanical planarization process. I","authors":"A. Hu, Z. Zhang, E. Sachs, P. Renteln","doi":"10.1109/IEMT.1993.398197","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398197","url":null,"abstract":"The Run by Run (RbR) controller, combining the advantages both statistical process control (SPC) and automatic process control (APC) has been applied successfully to a technically mature epitaxy processes and is now being applied on the chemical-mechanical planarization (CMP process). Three quality metrics are defined and used as measurements of process improvement. The application procedure is divided into five stages, of which the implementation stages one and two have been performed. The data show that a system can be described by an equilibrium state, a transition period responsive to shifts in the input, but exhibiting substantial hysteresis. A transition period between different equilibrium states is clearly observable. The memory that the pad has due to previous recipe is also clearly demonstrated.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125645449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398220
K. Pearsall, R. Raines, M. Schoellmann
Component end users want a high quality, reliable part. However, the expected failure rate, cost etc. may vary from one customer to the next. The amount of control that a packaging vendor is expected to put in place so that he can meet those requirements can be assessed through the implementation of QFD (quality function deployment). One such work effort that strives to use this technique for the definition and subsequent optimization of these controls for delivering high quality PQFP's (plastic quad flat packs) is described.<>
{"title":"Obtaining high quality VLSI packages with QFD","authors":"K. Pearsall, R. Raines, M. Schoellmann","doi":"10.1109/IEMT.1993.398220","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398220","url":null,"abstract":"Component end users want a high quality, reliable part. However, the expected failure rate, cost etc. may vary from one customer to the next. The amount of control that a packaging vendor is expected to put in place so that he can meet those requirements can be assessed through the implementation of QFD (quality function deployment). One such work effort that strives to use this technique for the definition and subsequent optimization of these controls for delivering high quality PQFP's (plastic quad flat packs) is described.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"42 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120925512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398228
C. Neubauer, R. Hanke
For six sigma quality in printed circuit board (PCB)-production, X-ray inspection of solder joints is a powerful method to assure a high standard in fabrication. Neural network classifiers are able to adapt inspection tasks by presentation of typical training patterns. Neural networks are integrated into a X-ray inspection system both to increase defect recognition accuracy, as well as to minimize manual adjustments of the system. The experiments carried out on different surface mount technology (SMT) device types prove the capability of neural-network-based approaches to correctly segment objects (solder joints etc.), and to detect defects (solder voids etc.).<>
{"title":"Improving X-ray inspection of printed circuit boards by integration of neural network classifiers","authors":"C. Neubauer, R. Hanke","doi":"10.1109/IEMT.1993.398228","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398228","url":null,"abstract":"For six sigma quality in printed circuit board (PCB)-production, X-ray inspection of solder joints is a powerful method to assure a high standard in fabrication. Neural network classifiers are able to adapt inspection tasks by presentation of typical training patterns. Neural networks are integrated into a X-ray inspection system both to increase defect recognition accuracy, as well as to minimize manual adjustments of the system. The experiments carried out on different surface mount technology (SMT) device types prove the capability of neural-network-based approaches to correctly segment objects (solder joints etc.), and to detect defects (solder voids etc.).<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124146466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1993-10-04DOI: 10.1109/IEMT.1993.398173
S. Sasaki, T. Kishimoto
A high-density high-pin-count flexible surface mount device (SMD) connector used for high-speed data buses between multichip modules (MCMs) or daughter boards is described. This connector consists of flexible film cable interconnection that has accurately controlled characteristic impedance and contact housing composed of double-line contacts and SMT type leads. It has 98 contacts each with a pitch of 0.4 mm. This connector mounting area is 6-mm wide and 23-mm long. The flexible cable has a double-sided tri-plate micro strip-line structure with insertion force of less than 3.9 kg and characteristic impedance of 48 to 50 /spl Omega/. Insertion loss is -0.5 dB at 600 MHz and crosstalk noise is less than 110 mV at 250 ps rising time. This connector can be applied for high-speed data transmission of up to 300 ps rising time.<>
{"title":"High-density and high-pin count flexible SMD connector for high-speed data bus","authors":"S. Sasaki, T. Kishimoto","doi":"10.1109/IEMT.1993.398173","DOIUrl":"https://doi.org/10.1109/IEMT.1993.398173","url":null,"abstract":"A high-density high-pin-count flexible surface mount device (SMD) connector used for high-speed data buses between multichip modules (MCMs) or daughter boards is described. This connector consists of flexible film cable interconnection that has accurately controlled characteristic impedance and contact housing composed of double-line contacts and SMT type leads. It has 98 contacts each with a pitch of 0.4 mm. This connector mounting area is 6-mm wide and 23-mm long. The flexible cable has a double-sided tri-plate micro strip-line structure with insertion force of less than 3.9 kg and characteristic impedance of 48 to 50 /spl Omega/. Insertion loss is -0.5 dB at 600 MHz and crosstalk noise is less than 110 mV at 250 ps rising time. This connector can be applied for high-speed data transmission of up to 300 ps rising time.<<ETX>>","PeriodicalId":206206,"journal":{"name":"Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127853742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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