Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664945
Retaj Yousri, Mahmoud Elbayoumi, A. Moawad, M. Darweesh, A. Soltan
Power management and saving in energy harvesting-based biomedical wearable devices are mandatory to ensure prolonged and stable operation under a stringent power budget. Thus, power-aware task scheduling can play a key role in minimizing energy consumption to improve system durability while maintaining device functionality. This paper proposes a novel biosensor task scheduling for optimizing energy consumption through wearable biomedical devices. The proposed approach is based on Flower Pollination Algorithm (FPA). The biomedical functionality constraints are enforced with a Hamming-based Tikhonov regularization. We proposed a greedy approach to compute the Tikhonov regularization term efficiently. The algorithm has been tested for scheduling the tasks of two biosensors: a heart rate sensor and a temperature sensor on a lab-based biomedical device.
{"title":"A Novel Power-Aware Task Scheduling for Energy Harvesting-Based Wearable Biomedical Devices Using FPA","authors":"Retaj Yousri, Mahmoud Elbayoumi, A. Moawad, M. Darweesh, A. Soltan","doi":"10.1109/ICM52667.2021.9664945","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664945","url":null,"abstract":"Power management and saving in energy harvesting-based biomedical wearable devices are mandatory to ensure prolonged and stable operation under a stringent power budget. Thus, power-aware task scheduling can play a key role in minimizing energy consumption to improve system durability while maintaining device functionality. This paper proposes a novel biosensor task scheduling for optimizing energy consumption through wearable biomedical devices. The proposed approach is based on Flower Pollination Algorithm (FPA). The biomedical functionality constraints are enforced with a Hamming-based Tikhonov regularization. We proposed a greedy approach to compute the Tikhonov regularization term efficiently. The algorithm has been tested for scheduling the tasks of two biosensors: a heart rate sensor and a temperature sensor on a lab-based biomedical device.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128239670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664920
Muhammad Sarg, A. Khalil, H. Mostafa
Convolutional Neural Networks (CNNs) have achieved high accuracy in many applications such as image recognition and classification. However, due to their large amount of parameters and intensive required operations, general purpose processors cannot achieve the desired inference performance levels. Recently, various hardware accelerators for deep CNNs have been carried out to enhance the throughput of CNNs. Among these accelerators, field programmable gate array (FPGA)-based ones have gained a lot of interest due to their high performance, low power consumption, high reconfigurability, and fast development cycle. Furthermore, the availability of high-level synthesis (HLS) tools lowers the programming burden and increases the productivity of the FPGA-based accelerator designers. In this paper, a C++ HLS implementation for FPGA-based accelerator for the convolutional layers of CNNs is proposed. As a case study, we evaluate the proposed accelerator using Resnet50 CNN on Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation board using SDSoC development environment, achieving up to 339x inference speedup.
{"title":"Efficient HLS Implementation for Convolutional Neural Networks Accelerator on an SoC","authors":"Muhammad Sarg, A. Khalil, H. Mostafa","doi":"10.1109/ICM52667.2021.9664920","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664920","url":null,"abstract":"Convolutional Neural Networks (CNNs) have achieved high accuracy in many applications such as image recognition and classification. However, due to their large amount of parameters and intensive required operations, general purpose processors cannot achieve the desired inference performance levels. Recently, various hardware accelerators for deep CNNs have been carried out to enhance the throughput of CNNs. Among these accelerators, field programmable gate array (FPGA)-based ones have gained a lot of interest due to their high performance, low power consumption, high reconfigurability, and fast development cycle. Furthermore, the availability of high-level synthesis (HLS) tools lowers the programming burden and increases the productivity of the FPGA-based accelerator designers. In this paper, a C++ HLS implementation for FPGA-based accelerator for the convolutional layers of CNNs is proposed. As a case study, we evaluate the proposed accelerator using Resnet50 CNN on Xilinx Zynq UltraScale+ MPSoC ZCU104 evaluation board using SDSoC development environment, achieving up to 339x inference speedup.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130690822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664957
Mohamed H. Abdulmonem, Ahmed K. Ismail, H. Mostafa
FPGA implementation is attained through either the traditional Register Transfer Level (RTL) flow or High-Level Synthesis (HLS) flow. The Consultative Committee for Space Data Systems (CCSDS) has recommended a standard for security algorithms for space missions. Authenticated encryption, the most important of those algorithms, can be achieved by either cipher-based or hash-based algorithms. In this paper, firstly, a brief explanation of the CCSDS standard authenticated encryption algorithms of both types is provided. Secondly, the algorithms are implemented in both RTL and HLS flows to measure and quantify the gap between the two design flows. Results show that the HLS modules utilize 44% more LUTs and consume an average of 40.8% more power than the RTL ones. In addition, the RTL modules demonstrated 28 times higher throughput than that of the HLS ones. Therefore, it is recommended to use the traditional RTL approach over the HLS one and the cipher-based module over the hash-based one at the expense of longer time-to-market for the RTL design. Additionally, the cipher-based module when compared to the hash-based one has proven higher efficiency utilizing 12% less area, achieving 35% higher throughput, and consuming 17% less energy per bit.
{"title":"Design and Implementation of Authenticated Encryption Co-Processors for Satellite Hardware Security","authors":"Mohamed H. Abdulmonem, Ahmed K. Ismail, H. Mostafa","doi":"10.1109/ICM52667.2021.9664957","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664957","url":null,"abstract":"FPGA implementation is attained through either the traditional Register Transfer Level (RTL) flow or High-Level Synthesis (HLS) flow. The Consultative Committee for Space Data Systems (CCSDS) has recommended a standard for security algorithms for space missions. Authenticated encryption, the most important of those algorithms, can be achieved by either cipher-based or hash-based algorithms. In this paper, firstly, a brief explanation of the CCSDS standard authenticated encryption algorithms of both types is provided. Secondly, the algorithms are implemented in both RTL and HLS flows to measure and quantify the gap between the two design flows. Results show that the HLS modules utilize 44% more LUTs and consume an average of 40.8% more power than the RTL ones. In addition, the RTL modules demonstrated 28 times higher throughput than that of the HLS ones. Therefore, it is recommended to use the traditional RTL approach over the HLS one and the cipher-based module over the hash-based one at the expense of longer time-to-market for the RTL design. Additionally, the cipher-based module when compared to the hash-based one has proven higher efficiency utilizing 12% less area, achieving 35% higher throughput, and consuming 17% less energy per bit.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130845442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664958
G. C. Souza, R. Moreno, T. Pimenta
Newcomb-Benford Law or Benford Law (BL) is a simple and powerful tool to identifying potencial anomalies in supposedly natural phenomena. BL works by comparing the frequency of the first digits acquired from an event with a pattern empirically established by Benford. The behavior described by Benford is typical in many natural processes and, therefore, several studies use the technique to try to identify anomalies that might suggest fraud in some data sets. Another trend is the use of tools that use artificial intelligence to support auditing. Considering that a COVID-19 pandemic is a natural event, it is possible to establish criteria for comparing the numbers released by governments and their relationship with BL. This research models Support Vector Machines (SVM) according to BL and makes a reliability analysis of the numbers of new cases and deaths, considering the pandemic scenario in 11 countries. Then, the work makes a statistical analysis according to BL and compares it to the results predicted by the algorithm. The results show that the network was able to make predictions that reinforce the BL results. Only two countries (Germany and Japan) presented results fully adherent to BL, either by statistical treatment or SVM prediction in all scenarios. The article used the data provided by Johns Hopkins University.
{"title":"Benford’s Law and Artificial Intelligence Applied to COVID-19","authors":"G. C. Souza, R. Moreno, T. Pimenta","doi":"10.1109/ICM52667.2021.9664958","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664958","url":null,"abstract":"Newcomb-Benford Law or Benford Law (BL) is a simple and powerful tool to identifying potencial anomalies in supposedly natural phenomena. BL works by comparing the frequency of the first digits acquired from an event with a pattern empirically established by Benford. The behavior described by Benford is typical in many natural processes and, therefore, several studies use the technique to try to identify anomalies that might suggest fraud in some data sets. Another trend is the use of tools that use artificial intelligence to support auditing. Considering that a COVID-19 pandemic is a natural event, it is possible to establish criteria for comparing the numbers released by governments and their relationship with BL. This research models Support Vector Machines (SVM) according to BL and makes a reliability analysis of the numbers of new cases and deaths, considering the pandemic scenario in 11 countries. Then, the work makes a statistical analysis according to BL and compares it to the results predicted by the algorithm. The results show that the network was able to make predictions that reinforce the BL results. Only two countries (Germany and Japan) presented results fully adherent to BL, either by statistical treatment or SVM prediction in all scenarios. The article used the data provided by Johns Hopkins University.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125686261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664956
A. A. A. El-Maksoud, Amr Gamal, A. Hesham, G. Saied, Mennat-Allah Ayman, Omnia Essam, Sara M. Mohamed, Eman El Mandouh, Ziad Ibrahim, Sara Mohamed, H. Mostafa
Convolutional neural network is a class of deep neural networks that has made a great breakthrough in image recognition. CNNs are commonly used to detect and classify visual applications so that they are frequently embedded in image classification tasks. The common trend nowadays is to accelerate the processing of CNNs in order to use them in real-time applications such as image classification and object recognition. This paper presents the implementation of ZynqNet CNN architecture on FPGA. The full ZynqNet CNN layers are implemented on FPGA to reach the max acceleration and make full use of all DSP units. Several optimizations techniques are used in different design phases to improve processing speed, utilized area, and power consumption. In addition, the proposed hardware accelerator achieves 15.6 fps for ZynqNet CNN at maximum frequency. The proposed architecture runs at two different frequencies of 100MHz and 125MHz, and is implemented on Virtex-7 FPGA.
{"title":"Hardware-Accelerated ZYNQ-NET Convolutional Neural Networks on Virtex-7 FPGA","authors":"A. A. A. El-Maksoud, Amr Gamal, A. Hesham, G. Saied, Mennat-Allah Ayman, Omnia Essam, Sara M. Mohamed, Eman El Mandouh, Ziad Ibrahim, Sara Mohamed, H. Mostafa","doi":"10.1109/ICM52667.2021.9664956","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664956","url":null,"abstract":"Convolutional neural network is a class of deep neural networks that has made a great breakthrough in image recognition. CNNs are commonly used to detect and classify visual applications so that they are frequently embedded in image classification tasks. The common trend nowadays is to accelerate the processing of CNNs in order to use them in real-time applications such as image classification and object recognition. This paper presents the implementation of ZynqNet CNN architecture on FPGA. The full ZynqNet CNN layers are implemented on FPGA to reach the max acceleration and make full use of all DSP units. Several optimizations techniques are used in different design phases to improve processing speed, utilized area, and power consumption. In addition, the proposed hardware accelerator achieves 15.6 fps for ZynqNet CNN at maximum frequency. The proposed architecture runs at two different frequencies of 100MHz and 125MHz, and is implemented on Virtex-7 FPGA.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116556996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664909
Shahenda M. Abdelhafiz, A. M. Abdelaty, M. Fouda, A. Radwan
Parameter identification of Li-ion battery models is important for efficiently charge and discharge the most widely used energy storage devices. In this work, we propose a simplified battery model with a parameter identification method for time-domain charging and discharging. Staircase PotentioElectrochemical Impedance Spectroscopy technique (SPEIS) is chosen to characterize the batteries during charging and discharging cycles at different voltage steps values. Marine Predator Algorithm (MPA) is used to identify the proposed model parameters on two commercial Li-ion coin-shaped batteries. The proposed model shows very good matching with the experiments with absolute current error less than 10 4. Hence, the proposed model can be used for real-time applications to predict the battery’s behavior under different operating conditions.
{"title":"Time-domain Li-ion Battery Modeling Under Staircase Charging and Discharging","authors":"Shahenda M. Abdelhafiz, A. M. Abdelaty, M. Fouda, A. Radwan","doi":"10.1109/ICM52667.2021.9664909","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664909","url":null,"abstract":"Parameter identification of Li-ion battery models is important for efficiently charge and discharge the most widely used energy storage devices. In this work, we propose a simplified battery model with a parameter identification method for time-domain charging and discharging. Staircase PotentioElectrochemical Impedance Spectroscopy technique (SPEIS) is chosen to characterize the batteries during charging and discharging cycles at different voltage steps values. Marine Predator Algorithm (MPA) is used to identify the proposed model parameters on two commercial Li-ion coin-shaped batteries. The proposed model shows very good matching with the experiments with absolute current error less than 10 4. Hence, the proposed model can be used for real-time applications to predict the battery’s behavior under different operating conditions.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116559403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664901
Malak Ahmad, N. Moubayed
Energy is the major resource in this whole world; however, it has been extensively used by buildings. In this paper, the concept of building's energy management is highlighted by modeling a hierarchized hybrid predictive control. HHMPC uniqueness goes to satisfying inhabitants, minimizing cost while covering minimal disturbances and considering constrains. A comparison was done after modeling and simulating classical model predictive control with a hierarchized hybrid predictive control. The contribution in this paper concerns the validation of the predictive control model. In addition, it treats the modeling and discusses the simulation results of the enhanced MPC called hierarchized hybrid model predictive control.
{"title":"From Model Predictive to Hierarchized Hybrid Controller for Energy Management in Buildings","authors":"Malak Ahmad, N. Moubayed","doi":"10.1109/ICM52667.2021.9664901","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664901","url":null,"abstract":"Energy is the major resource in this whole world; however, it has been extensively used by buildings. In this paper, the concept of building's energy management is highlighted by modeling a hierarchized hybrid predictive control. HHMPC uniqueness goes to satisfying inhabitants, minimizing cost while covering minimal disturbances and considering constrains. A comparison was done after modeling and simulating classical model predictive control with a hierarchized hybrid predictive control. The contribution in this paper concerns the validation of the predictive control model. In addition, it treats the modeling and discusses the simulation results of the enhanced MPC called hierarchized hybrid model predictive control.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124757597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664940
Omar M. Elsayed, Samar M. Ismail, M. A. E. Ghany
With the increasing demand on artificial intelligence in various daily life applications, a hardware design is proposed in this work for a convolutional neural network (CNN), for brain tumor classification. In terms of the type of data each machine learning technique uses or how the training process works, the CNN was chosen in this work because of its architecture, which was created exclusively to have picture input and its efficiency in image processing in general. The training phase is performed based on CNN using a brain tumor dataset in MATLAB. Then, a Register Transfer Level (RTL) inference model is built to use the parameters resultant from the training process (weights and biases), to be implemented on FPGA using Vivado HLS. The proposed model achieved higher accuracy than previous models in literature.
{"title":"Register Transfer Level Model For CNN Tumor Detection on FPGA","authors":"Omar M. Elsayed, Samar M. Ismail, M. A. E. Ghany","doi":"10.1109/ICM52667.2021.9664940","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664940","url":null,"abstract":"With the increasing demand on artificial intelligence in various daily life applications, a hardware design is proposed in this work for a convolutional neural network (CNN), for brain tumor classification. In terms of the type of data each machine learning technique uses or how the training process works, the CNN was chosen in this work because of its architecture, which was created exclusively to have picture input and its efficiency in image processing in general. The training phase is performed based on CNN using a brain tumor dataset in MATLAB. Then, a Register Transfer Level (RTL) inference model is built to use the parameters resultant from the training process (weights and biases), to be implemented on FPGA using Vivado HLS. The proposed model achieved higher accuracy than previous models in literature.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124994115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664914
Mahmoud N. Zidan, Retaj Yousri, A. Soltan, A. Madian
The full-wave rectifier is an essential step for extracting energy from a piezoelectric source. Yet, the inherent capacitance of the piezoelement significantly is considered a limitation of the efficiency of extraction. To address this issue, the bias-flip rectifier can be used. However, this rectifier needs large inductor and precise tuning. The large inductor increases the overall volume of the system which is inefficient. This paper address the problems with the traditional bias-flip rectifier by introducing an enhanced multi-step bias-flip rectifier to achieve a high voltage-flip efficiency using a much smaller inductor. Moreover, the implemented multi-step bias-flip rectifier the timing requirements on testing.
{"title":"Implementation of Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting","authors":"Mahmoud N. Zidan, Retaj Yousri, A. Soltan, A. Madian","doi":"10.1109/ICM52667.2021.9664914","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664914","url":null,"abstract":"The full-wave rectifier is an essential step for extracting energy from a piezoelectric source. Yet, the inherent capacitance of the piezoelement significantly is considered a limitation of the efficiency of extraction. To address this issue, the bias-flip rectifier can be used. However, this rectifier needs large inductor and precise tuning. The large inductor increases the overall volume of the system which is inefficient. This paper address the problems with the traditional bias-flip rectifier by introducing an enhanced multi-step bias-flip rectifier to achieve a high voltage-flip efficiency using a much smaller inductor. Moreover, the implemented multi-step bias-flip rectifier the timing requirements on testing.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125921184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664964
L. R. Gonçalves, R. M. Volpato, T. Pimenta
SmartGrid networks provides monitoring, management and control to the assets that are part of the electrical system. They can be implemented using various types of communication technologies, both wired and wireless. Data can be transmitted over a wired connection, cellular, short- range WPAN, and long-range LPWAN. These technologies use different frequency spectrum, data rates, power consumption, latency, modulation, bandwidth, and physical layers. This variety of differences enables the coexistence of those technologies on the same system, thus building a robust, complementary and flexible solution.
{"title":"A Comparison of Low Power Wireless Technologies for SmartGrid Networks","authors":"L. R. Gonçalves, R. M. Volpato, T. Pimenta","doi":"10.1109/ICM52667.2021.9664964","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664964","url":null,"abstract":"SmartGrid networks provides monitoring, management and control to the assets that are part of the electrical system. They can be implemented using various types of communication technologies, both wired and wireless. Data can be transmitted over a wired connection, cellular, short- range WPAN, and long-range LPWAN. These technologies use different frequency spectrum, data rates, power consumption, latency, modulation, bandwidth, and physical layers. This variety of differences enables the coexistence of those technologies on the same system, thus building a robust, complementary and flexible solution.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124070477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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