Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664914
Mahmoud N. Zidan, Retaj Yousri, A. Soltan, A. Madian
The full-wave rectifier is an essential step for extracting energy from a piezoelectric source. Yet, the inherent capacitance of the piezoelement significantly is considered a limitation of the efficiency of extraction. To address this issue, the bias-flip rectifier can be used. However, this rectifier needs large inductor and precise tuning. The large inductor increases the overall volume of the system which is inefficient. This paper address the problems with the traditional bias-flip rectifier by introducing an enhanced multi-step bias-flip rectifier to achieve a high voltage-flip efficiency using a much smaller inductor. Moreover, the implemented multi-step bias-flip rectifier the timing requirements on testing.
{"title":"Implementation of Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting","authors":"Mahmoud N. Zidan, Retaj Yousri, A. Soltan, A. Madian","doi":"10.1109/ICM52667.2021.9664914","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664914","url":null,"abstract":"The full-wave rectifier is an essential step for extracting energy from a piezoelectric source. Yet, the inherent capacitance of the piezoelement significantly is considered a limitation of the efficiency of extraction. To address this issue, the bias-flip rectifier can be used. However, this rectifier needs large inductor and precise tuning. The large inductor increases the overall volume of the system which is inefficient. This paper address the problems with the traditional bias-flip rectifier by introducing an enhanced multi-step bias-flip rectifier to achieve a high voltage-flip efficiency using a much smaller inductor. Moreover, the implemented multi-step bias-flip rectifier the timing requirements on testing.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125921184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664926
Abdelrahman Adel, Dina Saad, Mahmoud Abd El Mawgoed, Mohamed Sharshar, Zyad Ahmed, Hala Ibrahim, H. Mostafa
In the world of technology we live in, there is a huge increase in the number of internet of things (IoT) devices leading to a tremendous amount of data being sent. This wireless data is prone to eavesdropping and being hacked. The contribution of this work is the design of a System on Chip (SoC) with a processor based on the instruction set architecture (ISA) of reduced instruction-set computer (RISC-V). The system focuses on the security of data between IoT end-nodes. For SoC verification, a Universal Verification Methodology (UVM) environment is used for covering most of the functionality and security aspects to guarantee a sufficient level of trust in the implemented SoC.
{"title":"Implementation and Functional Verification of RISC-V Core for Secure IoT Applications","authors":"Abdelrahman Adel, Dina Saad, Mahmoud Abd El Mawgoed, Mohamed Sharshar, Zyad Ahmed, Hala Ibrahim, H. Mostafa","doi":"10.1109/ICM52667.2021.9664926","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664926","url":null,"abstract":"In the world of technology we live in, there is a huge increase in the number of internet of things (IoT) devices leading to a tremendous amount of data being sent. This wireless data is prone to eavesdropping and being hacked. The contribution of this work is the design of a System on Chip (SoC) with a processor based on the instruction set architecture (ISA) of reduced instruction-set computer (RISC-V). The system focuses on the security of data between IoT end-nodes. For SoC verification, a Universal Verification Methodology (UVM) environment is used for covering most of the functionality and security aspects to guarantee a sufficient level of trust in the implemented SoC.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126715055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664944
Tianfang Peng, Zheng You
Artillery launching is one of the extremely harsh environments faced by electronic systems. The commonly used potting protection will transmit the high-frequency vibration of the launching process to the electronic components, interfere with their internal structures (such as MEMS), and increase the probability of failure of the ammunition. This paper proposes a protective structure for electronic system facing artillery launching process. The structure can withstand the high-g acceleration, while filtering the high-frequency vibrations, so as to protect the electronic components in the ammunition. Firstly, we established a shock/vibration isolation model for the artillery launching process, and determined the ideal stiffness and damping ratio of the structure. Secondly, we designed the structure with a shock-resistant, low-rigidity spring and an adjustable liquid damper. The experimental result showed that the structure remained intact under the shock of about 35000g, and could filter the mechanical vibration above 500Hz. In addition, the damping ratio of the device could be adjusted between 0.04-0.26. Finally, we carried out shock experiments on several types of commercial chips with the protection of the structure. All of the chips had survived the shock of about 18000g without potting protection.
{"title":"A Protective Structure for Electronic Systems Facing Artillery Launching Process","authors":"Tianfang Peng, Zheng You","doi":"10.1109/ICM52667.2021.9664944","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664944","url":null,"abstract":"Artillery launching is one of the extremely harsh environments faced by electronic systems. The commonly used potting protection will transmit the high-frequency vibration of the launching process to the electronic components, interfere with their internal structures (such as MEMS), and increase the probability of failure of the ammunition. This paper proposes a protective structure for electronic system facing artillery launching process. The structure can withstand the high-g acceleration, while filtering the high-frequency vibrations, so as to protect the electronic components in the ammunition. Firstly, we established a shock/vibration isolation model for the artillery launching process, and determined the ideal stiffness and damping ratio of the structure. Secondly, we designed the structure with a shock-resistant, low-rigidity spring and an adjustable liquid damper. The experimental result showed that the structure remained intact under the shock of about 35000g, and could filter the mechanical vibration above 500Hz. In addition, the damping ratio of the device could be adjusted between 0.04-0.26. Finally, we carried out shock experiments on several types of commercial chips with the protection of the structure. All of the chips had survived the shock of about 18000g without potting protection.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134193660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664896
Yassine Attaoui, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, A. E. Mourabit
Nowadays, power optimization has become an important factor in VLSI design and various low power optimization techniques are being developed. Clock-Gating is considered one of the widely used techniques in VLSI power optimization. Gating the Clock path results in saving power by reducing wasted capacitances switching due to unnecessary activity in logic module paths, thus resulting in more wasted Switching power. Clock gating is not always beneficial, it presents some pitfalls and fallacies within its implementation in various VLSI designs, as well as it doesn't suit all kinds of VLSI logic circuits. In this paper, we measure the impact of the Clock-Gating technique on power as well as on design's performance. We have performed two separate trials, using 112 industrial designs from different technologies, the former trial enables Clock Gate insertion, and the latter does not insert Clock Gate cells in the design's circuitry. We intend to measure the impact of Clock Gating on power by measuring the Power variation and comparing metrics such Instance number Buffer & Inverter, Combinational blocks as well as QoR metrics such Runtime, wire-length, TNS, and Area. Results of this experiment showed that design circuits having Memories (SRAM, DFF, FIFO…) as dominant RTL modules, have the most impact on power when CG cells are inserted. Vice-versa power is less impacted by CG cells insertion for designs that contain microprocessors and Datapath blocks as dominant RTL instances.
{"title":"Clock Gating Efficiency and Impact on Power Optimization During Synthesis Flow","authors":"Yassine Attaoui, Mohamed Chentouf, Zine El Abidine Alaoui Ismaili, A. E. Mourabit","doi":"10.1109/ICM52667.2021.9664896","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664896","url":null,"abstract":"Nowadays, power optimization has become an important factor in VLSI design and various low power optimization techniques are being developed. Clock-Gating is considered one of the widely used techniques in VLSI power optimization. Gating the Clock path results in saving power by reducing wasted capacitances switching due to unnecessary activity in logic module paths, thus resulting in more wasted Switching power. Clock gating is not always beneficial, it presents some pitfalls and fallacies within its implementation in various VLSI designs, as well as it doesn't suit all kinds of VLSI logic circuits. In this paper, we measure the impact of the Clock-Gating technique on power as well as on design's performance. We have performed two separate trials, using 112 industrial designs from different technologies, the former trial enables Clock Gate insertion, and the latter does not insert Clock Gate cells in the design's circuitry. We intend to measure the impact of Clock Gating on power by measuring the Power variation and comparing metrics such Instance number Buffer & Inverter, Combinational blocks as well as QoR metrics such Runtime, wire-length, TNS, and Area. Results of this experiment showed that design circuits having Memories (SRAM, DFF, FIFO…) as dominant RTL modules, have the most impact on power when CG cells are inserted. Vice-versa power is less impacted by CG cells insertion for designs that contain microprocessors and Datapath blocks as dominant RTL instances.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121785234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664900
Luca Steinweg, P. V. Testa, C. Carta, F. Ellinger
This work studies a concept for a 90° vector-sum phase shifter operating at 54.6GHz, which delivers a high output power over a wide bandwidth of 20GHz, corresponding to a relative bandwidth of 37.2%. The circuit was designed to control the phase in a local-oscillator chain and was realized in a 130nm SiGe BiCMOS technology. A root mean square (RMS) magnitude error of only 0.23dB is paired with an RMS phase error of 0.89dB, achieving linear control with only one un-calibrated analog voltage. An output-referred 1dB-compression point oP1dB of 5.0dBm is achieved at 60GHz with 11.3dB gain and a power-added efficiency of 6.3%. The high output power qualifies this circuit to directly drive state-of-the-art frequency multipliers and leverage their multiplication factor to reach mm-wave bands with 360° of available phase control. To the best knowledge of the authors, this circuit demonstrates the highest output power and power-added efficiency reported for phase shifters operating at about 60GHz or above, while still providing high power gain.
{"title":"A 5 dBm BiCMOS 90° Phase Shifter with Single-Voltage Tuning for mm-Wave Beam Steering","authors":"Luca Steinweg, P. V. Testa, C. Carta, F. Ellinger","doi":"10.1109/ICM52667.2021.9664900","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664900","url":null,"abstract":"This work studies a concept for a 90° vector-sum phase shifter operating at 54.6GHz, which delivers a high output power over a wide bandwidth of 20GHz, corresponding to a relative bandwidth of 37.2%. The circuit was designed to control the phase in a local-oscillator chain and was realized in a 130nm SiGe BiCMOS technology. A root mean square (RMS) magnitude error of only 0.23dB is paired with an RMS phase error of 0.89dB, achieving linear control with only one un-calibrated analog voltage. An output-referred 1dB-compression point oP1dB of 5.0dBm is achieved at 60GHz with 11.3dB gain and a power-added efficiency of 6.3%. The high output power qualifies this circuit to directly drive state-of-the-art frequency multipliers and leverage their multiplication factor to reach mm-wave bands with 360° of available phase control. To the best knowledge of the authors, this circuit demonstrates the highest output power and power-added efficiency reported for phase shifters operating at about 60GHz or above, while still providing high power gain.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122250851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664921
Mohamed Chentouf, Chaimaa Naimy, Zine El Abidine Alaoui Ismaili
Power Analysis (PA) is an important task performed repeatedly throughout the flow to ensure the design closure within the power budget. One of the challenges of the state-of-art PA tools is the low accuracy at high abstraction levels such as gate and RTL. This accuracy gap can be reduced by feeding-back physical information such as Standard Parasitic Extraction File (SPEF) to higher abstraction level to have an estimate of the RC components of the nets. Unfortunately, with current design methodologies, the SPEF file is only available at a very late stage of the circuit development after passing the physical design stage. In this paper, we introduce a machine learning application that estimates accurately the switching power of the cells without needing the SPEF file (SPEF less PA flow). Three ML models (Multi-linear Regression, Random Forest, and Decision Tree) were trained and tested on different industrial designs at 7nm technology. They are trained using different cells' properties available, SPEF, and SPEF-less power numbers to accurately predict the Switching power and eliminate the need for the SPEF file. With this new ML approach, we were able to reduce the SPEF less flow average cell switching power error from 34% to 8%.
功率分析(PA)是在整个流程中反复执行的一项重要任务，以确保设计在功率预算范围内完成。最先进的PA工具面临的挑战之一是在高抽象级别(如gate和RTL)上的低准确性。这种准确性差距可以通过反馈物理信息(如标准寄生提取文件(SPEF))到更高的抽象级别来减少，从而对网络的RC组件进行估计。不幸的是，使用当前的设计方法，SPEF文件仅在通过物理设计阶段后的电路开发的非常后期阶段可用。在本文中，我们介绍了一种机器学习应用程序，它可以在不需要SPEF文件(SPEF less PA flow)的情况下准确估计单元的开关功率。三种机器学习模型(多元线性回归、随机森林和决策树)在不同的工业设计上进行了训练和测试。它们使用不同的可用单元属性、SPEF和SPEF-less功率数进行训练，以准确预测开关功率并消除对SPEF文件的需求。通过这种新的ML方法，我们能够将SPEF少流的平均电池开关功率误差从34%降低到8%。
{"title":"Machine Learning Application for Early Power Analysis Accuracy Improvement: A Case Study for Cells Switching Power","authors":"Mohamed Chentouf, Chaimaa Naimy, Zine El Abidine Alaoui Ismaili","doi":"10.1109/ICM52667.2021.9664921","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664921","url":null,"abstract":"Power Analysis (PA) is an important task performed repeatedly throughout the flow to ensure the design closure within the power budget. One of the challenges of the state-of-art PA tools is the low accuracy at high abstraction levels such as gate and RTL. This accuracy gap can be reduced by feeding-back physical information such as Standard Parasitic Extraction File (SPEF) to higher abstraction level to have an estimate of the RC components of the nets. Unfortunately, with current design methodologies, the SPEF file is only available at a very late stage of the circuit development after passing the physical design stage. In this paper, we introduce a machine learning application that estimates accurately the switching power of the cells without needing the SPEF file (SPEF less PA flow). Three ML models (Multi-linear Regression, Random Forest, and Decision Tree) were trained and tested on different industrial designs at 7nm technology. They are trained using different cells' properties available, SPEF, and SPEF-less power numbers to accurately predict the Switching power and eliminate the need for the SPEF file. With this new ML approach, we were able to reduce the SPEF less flow average cell switching power error from 34% to 8%.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123514082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664943
Omar Eid, M. M. A. E. Ghany
The high computational power of GPUs allowed for larger networks to be used in object detection applications. However, due to the huge power consumption and inefficiency when it comes to memory access and the number of bits used to represent the data, it is difficult to use them in embedded applications. Therefore, extensive research has been conducted to use FPGAs as a highly efficient substitute for GPUs to implement deep learning algorithms. As the scale and complexity of the algorithms keep increasing each year to improve their performance, it becomes even harder to implement such algorithms on an FPGA without reusing hardware resources. In this work, we implement Yolov4-tiny on a single FPGA by applying several resource sharing and optimization techniques. Our implementation shows a decrease in power consumption that ranges from 66% to 93.5% less power when compared to software. Moreover, less hardware resources and faster inference time is achieved. When comparing with the hardware implementation of networks with similar size, our design is 6.67 times faster and uses 62.5% less energy per image.
{"title":"Hardware Implementation of Yolov4-tiny for Object Detection","authors":"Omar Eid, M. M. A. E. Ghany","doi":"10.1109/ICM52667.2021.9664943","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664943","url":null,"abstract":"The high computational power of GPUs allowed for larger networks to be used in object detection applications. However, due to the huge power consumption and inefficiency when it comes to memory access and the number of bits used to represent the data, it is difficult to use them in embedded applications. Therefore, extensive research has been conducted to use FPGAs as a highly efficient substitute for GPUs to implement deep learning algorithms. As the scale and complexity of the algorithms keep increasing each year to improve their performance, it becomes even harder to implement such algorithms on an FPGA without reusing hardware resources. In this work, we implement Yolov4-tiny on a single FPGA by applying several resource sharing and optimization techniques. Our implementation shows a decrease in power consumption that ranges from 66% to 93.5% less power when compared to software. Moreover, less hardware resources and faster inference time is achieved. When comparing with the hardware implementation of networks with similar size, our design is 6.67 times faster and uses 62.5% less energy per image.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114227628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664924
Abdelrahman M. Mahran, S. Abdellatif
Solar cells have been in an evolution process day by day, which opens the door for brand new technologies and applications. One of the most promising technologies that is offered nowadays is the semi-transparent solar cells. Semi-transparent cells can offer light harvesting solutions in a wide band of applications, for instance electrical vehicle glass window and smart buildings. As this technology just walking its first steps, we introduce a new optimization attempt in terms of the trade-off between transparency and efficiency. Study has been conducted on six different third generation solar cells which include four perovskite solar cells (PSC) and two dye sanitized solar cells (DSSC). Results showed that organic lead-free PSC is the most appropriate candidate for semi-transparent technology with efficiency reaching 29.97% and transparency of 85.59%.
{"title":"Optoelectronic Modelling and Analysis of Transparency against Efficiency in Perovskites/Dye-based Solar Cells","authors":"Abdelrahman M. Mahran, S. Abdellatif","doi":"10.1109/ICM52667.2021.9664924","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664924","url":null,"abstract":"Solar cells have been in an evolution process day by day, which opens the door for brand new technologies and applications. One of the most promising technologies that is offered nowadays is the semi-transparent solar cells. Semi-transparent cells can offer light harvesting solutions in a wide band of applications, for instance electrical vehicle glass window and smart buildings. As this technology just walking its first steps, we introduce a new optimization attempt in terms of the trade-off between transparency and efficiency. Study has been conducted on six different third generation solar cells which include four perovskite solar cells (PSC) and two dye sanitized solar cells (DSSC). Results showed that organic lead-free PSC is the most appropriate candidate for semi-transparent technology with efficiency reaching 29.97% and transparency of 85.59%.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125447707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664906
M. Arnaout, Ahmad Ghizzawi, Ali Al-Hajj Hassan, Ali Koubayssi, M. Kafal, Ziad Noun
In order to follow the technological evolution in the 21st century, and to detect the fault with the minimal effort spent, this paper was developed to identify the open and short circuit faults that may occur in the lighting and socket grids used in residential area while using machine learning algorithms. In this research, two cable networks were formed (the first one has a short circuit fault, and the second with an open circuit fault), then a neural network was used in order to detect these faults. Finally, several results will be shown that lead to verify the adequacy of the proposed method.
{"title":"The Detection and Classification of Faults by the Use of Machine Learning Technique","authors":"M. Arnaout, Ahmad Ghizzawi, Ali Al-Hajj Hassan, Ali Koubayssi, M. Kafal, Ziad Noun","doi":"10.1109/ICM52667.2021.9664906","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664906","url":null,"abstract":"In order to follow the technological evolution in the 21st century, and to detect the fault with the minimal effort spent, this paper was developed to identify the open and short circuit faults that may occur in the lighting and socket grids used in residential area while using machine learning algorithms. In this research, two cable networks were formed (the first one has a short circuit fault, and the second with an open circuit fault), then a neural network was used in order to detect these faults. Finally, several results will be shown that lead to verify the adequacy of the proposed method.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125308333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-19DOI: 10.1109/ICM52667.2021.9664895
Wael Bou Diab, Reem Abou Hamdan, Ali Koubayssi, Mohammad Arnaout, Rabih Rammal
the paper offers a comprehensive study on integrating electric vehicles into the smart grid. Electric vehicles' environmental impacts are briefly discussed. The relationship between the smart grid and the electric vehicles denoted under the vehicle-to-grid, and grid-to-vehicle scenarios are expressed. The integration of electric vehicles into the smart grid poses difficulties in terms of planning, operating, and controlling the grid, so these challenges are supported by applications for a progressive integration, in addition to a literature review about an investigation on incorporating renewable energy resources in this integration. Also, a new patent called the SOC-OCV estimation method is expressed with the full steps of calculations. Further, an electric vehicle model is constructed to mimic the performance of a real electric vehicle is donated with its blocks assisted with the SOC-OCV estimation method.
{"title":"Integration of Electric Vehicles in Smart Grids","authors":"Wael Bou Diab, Reem Abou Hamdan, Ali Koubayssi, Mohammad Arnaout, Rabih Rammal","doi":"10.1109/ICM52667.2021.9664895","DOIUrl":"https://doi.org/10.1109/ICM52667.2021.9664895","url":null,"abstract":"the paper offers a comprehensive study on integrating electric vehicles into the smart grid. Electric vehicles' environmental impacts are briefly discussed. The relationship between the smart grid and the electric vehicles denoted under the vehicle-to-grid, and grid-to-vehicle scenarios are expressed. The integration of electric vehicles into the smart grid poses difficulties in terms of planning, operating, and controlling the grid, so these challenges are supported by applications for a progressive integration, in addition to a literature review about an investigation on incorporating renewable energy resources in this integration. Also, a new patent called the SOC-OCV estimation method is expressed with the full steps of calculations. Further, an electric vehicle model is constructed to mimic the performance of a real electric vehicle is donated with its blocks assisted with the SOC-OCV estimation method.","PeriodicalId":212613,"journal":{"name":"2021 International Conference on Microelectronics (ICM)","volume":"62 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129166910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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