Pub Date : 1994-10-11DOI: 10.1109/NORTHC.1994.643340
L. Carty
Since the publication of Reengineering the Corporation by Michael Hammer and James Champy in 1993 there has been an attitude in some circles that Total Quality Management is the old thing and Reengineering the direction of the future. This is caused by a failure to recognize that the principles of reengineering have been applied in Total Quality organizations for decades. As Peter Scholtes once said, "Reengineering has always been a part of Total Quality, it just didn't have a name.''
{"title":"Integrating Elements Of Reengineering Within A Total Quality Management Framework","authors":"L. Carty","doi":"10.1109/NORTHC.1994.643340","DOIUrl":"https://doi.org/10.1109/NORTHC.1994.643340","url":null,"abstract":"Since the publication of Reengineering the Corporation by Michael Hammer and James Champy in 1993 there has been an attitude in some circles that Total Quality Management is the old thing and Reengineering the direction of the future. This is caused by a failure to recognize that the principles of reengineering have been applied in Total Quality organizations for decades. As Peter Scholtes once said, \"Reengineering has always been a part of Total Quality, it just didn't have a name.''","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115664368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-11DOI: 10.1109/NORTHC.1994.639615
M. Morrow
{"title":"Where Is Iso 9000 Headed?","authors":"M. Morrow","doi":"10.1109/NORTHC.1994.639615","DOIUrl":"https://doi.org/10.1109/NORTHC.1994.639615","url":null,"abstract":"","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132424702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-11DOI: 10.1109/NORTHC.1994.638973
G. J. Taggart, J. D. Goff
We present the conditions in which a toroidal type, line frequency, power transformer can yield reduced stray magnetic field, reduced weight and size, and improved efficiency over an E-I laminate transformer in single phase linear power supplies. These benefits must be considered in relation to the disadvantages of slightly higher cost and greater inrush current.
{"title":"Optimizing linear power supply performance with line frequency toroidal transformers","authors":"G. J. Taggart, J. D. Goff","doi":"10.1109/NORTHC.1994.638973","DOIUrl":"https://doi.org/10.1109/NORTHC.1994.638973","url":null,"abstract":"We present the conditions in which a toroidal type, line frequency, power transformer can yield reduced stray magnetic field, reduced weight and size, and improved efficiency over an E-I laminate transformer in single phase linear power supplies. These benefits must be considered in relation to the disadvantages of slightly higher cost and greater inrush current.","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116869528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-11DOI: 10.1109/NORTHC.1994.643394
G. Eimers
As an alternative to the high cost and turnaround time associated with outsourcing to chemical houses, many design teams are opting instead to implement in-house systems for circuit board prototyping. Mechanical fabrication systems can now reduce the time it takes to turn a board to as little as an hour or two. And in many cases, these in-house board plotters are adding additional value in applications beyond their traditional use as a prototyping device. This paper explores the many ways in which in-house processing of printed circuit boards benefits the design engineer by saving dollars and time in overall product development. Additionally, we will illustrate that in-house fabrication of prototype circuit boards allows the design engineer to exercise greater control over his project and reduces the risks associated with making modifications to the product.
{"title":"The real value of prototyping systems","authors":"G. Eimers","doi":"10.1109/NORTHC.1994.643394","DOIUrl":"https://doi.org/10.1109/NORTHC.1994.643394","url":null,"abstract":"As an alternative to the high cost and turnaround time associated with outsourcing to chemical houses, many design teams are opting instead to implement in-house systems for circuit board prototyping. Mechanical fabrication systems can now reduce the time it takes to turn a board to as little as an hour or two. And in many cases, these in-house board plotters are adding additional value in applications beyond their traditional use as a prototyping device. This paper explores the many ways in which in-house processing of printed circuit boards benefits the design engineer by saving dollars and time in overall product development. Additionally, we will illustrate that in-house fabrication of prototype circuit boards allows the design engineer to exercise greater control over his project and reduces the risks associated with making modifications to the product.","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127635429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-11DOI: 10.1109/NORTHC.1994.638955
C. Hastings
The new Sharp LH5402X5-family 18-bit-wide First-in, First-Out memories (FIFOs) are high-speed, synchronous digital specialty-memory devices, useful for local temporary storage and for data-rate-matching applications in high-performance digital systems. These FIFOs are implemented in recent-vintage 0.8 /spl mu//0.7 /spl mu/ CMOS static-RAM technology, and feature many conveniences and useful options for digital-system designers. One of them can replace two industry-standard 9-bit-wide asynchronous FIFOs of the same depth, and at the same time provide higher-speed operation and more convenient timing characteristics. They also can replace other existing 18-bit-wide FIFOs, in many cases without design changes to the system. The LH5402X5 family indudes four pin-compatible FIFOs, differing in depth: LH540215 (512/spl times/18 meaning 512 18-bit words); LH540225 (1024/spl times/18); LH540235 (2048/spl times/18); and LH540245 (4096/spl times/18). As of this article, the first two of these FIFOs are in production; the other two are in the design stage. These FIFOs are available in speed grades up to 50 MHz (20 nsec-cycle-time).
{"title":"The Sharp LH5402X5 family: mainstream, designer-friendly, 18-bit-wide synchronous FIFOs","authors":"C. Hastings","doi":"10.1109/NORTHC.1994.638955","DOIUrl":"https://doi.org/10.1109/NORTHC.1994.638955","url":null,"abstract":"The new Sharp LH5402X5-family 18-bit-wide First-in, First-Out memories (FIFOs) are high-speed, synchronous digital specialty-memory devices, useful for local temporary storage and for data-rate-matching applications in high-performance digital systems. These FIFOs are implemented in recent-vintage 0.8 /spl mu//0.7 /spl mu/ CMOS static-RAM technology, and feature many conveniences and useful options for digital-system designers. One of them can replace two industry-standard 9-bit-wide asynchronous FIFOs of the same depth, and at the same time provide higher-speed operation and more convenient timing characteristics. They also can replace other existing 18-bit-wide FIFOs, in many cases without design changes to the system. The LH5402X5 family indudes four pin-compatible FIFOs, differing in depth: LH540215 (512/spl times/18 meaning 512 18-bit words); LH540225 (1024/spl times/18); LH540235 (2048/spl times/18); and LH540245 (4096/spl times/18). As of this article, the first two of these FIFOs are in production; the other two are in the design stage. These FIFOs are available in speed grades up to 50 MHz (20 nsec-cycle-time).","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125193928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-11DOI: 10.1109/NORTHC.1994.638963
R. Sohun
{"title":"Developing A Continuous Cultural Improvement Process","authors":"R. Sohun","doi":"10.1109/NORTHC.1994.638963","DOIUrl":"https://doi.org/10.1109/NORTHC.1994.638963","url":null,"abstract":"","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128201046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-11DOI: 10.1109/NORTHC.1994.643353
M. Seal
The design team for Viking 23 decided that a solar electric, parallel hybrid vehicle would be a realistic replacement for today's car. A range of up to 100 Km at an average urban speed of 50 kph in zero emission mode was set as a goal. An attempt will be made to do this with no power drawn from the existing electric power grid by utilizing solar cells to charge the battery. For inter-city use a target range of 500 km at an average speed of 100 kph was set. The parallel configuration was chosen because mechanical drive-line efficiency is greater than that possible for a series hybrid. One disadvantage of a parallel hybrid is that a larger more powerful internal combustion (IC) engine is required for hill climbing and maximum performance than would be needed for the series configuration. On the other hand, no large generator is needed to collect the IC engine power to charge the battery and run the electric motors.
{"title":"Viking 23-zero emissions in the city, range and performance on the freeway","authors":"M. Seal","doi":"10.1109/NORTHC.1994.643353","DOIUrl":"https://doi.org/10.1109/NORTHC.1994.643353","url":null,"abstract":"The design team for Viking 23 decided that a solar electric, parallel hybrid vehicle would be a realistic replacement for today's car. A range of up to 100 Km at an average urban speed of 50 kph in zero emission mode was set as a goal. An attempt will be made to do this with no power drawn from the existing electric power grid by utilizing solar cells to charge the battery. For inter-city use a target range of 500 km at an average speed of 100 kph was set. The parallel configuration was chosen because mechanical drive-line efficiency is greater than that possible for a series hybrid. One disadvantage of a parallel hybrid is that a larger more powerful internal combustion (IC) engine is required for hill climbing and maximum performance than would be needed for the series configuration. On the other hand, no large generator is needed to collect the IC engine power to charge the battery and run the electric motors.","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133335443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-11DOI: 10.1109/NORTHC.1994.643327
C. Huang, F. Wong, D. Kim
This paper will discuss several measuring techniques that are used in the industry today for extraction of electrical parasitics of packages and interconnects. Specifically, the techniques that will be covered are the SEMI-Standard (G23-84) method, the impedance method, and the network analysis method. The data measured from these methods will be presented. Theoretical analysis and simulation results from software will be compared to discuss the advantages and disadvantages of each method.
{"title":"Different electrical measuring techniques of package and interconnect parasitics for high speed VLSI devices","authors":"C. Huang, F. Wong, D. Kim","doi":"10.1109/NORTHC.1994.643327","DOIUrl":"https://doi.org/10.1109/NORTHC.1994.643327","url":null,"abstract":"This paper will discuss several measuring techniques that are used in the industry today for extraction of electrical parasitics of packages and interconnects. Specifically, the techniques that will be covered are the SEMI-Standard (G23-84) method, the impedance method, and the network analysis method. The data measured from these methods will be presented. Theoretical analysis and simulation results from software will be compared to discuss the advantages and disadvantages of each method.","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115694850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-10-11DOI: 10.1109/NORTHC.1994.643344
M. A. Pitts, M. S. Foster
Ever increasing system complexities, limited development resources, and the desire to implement flexible dual use applications are driving the need to reduce system design time, development costs, and risks. Development cost and design time can be reduced by minimizing design iterations and identifying roadblocks early in the design cycle. In addition, utilizing a hierarchical top down process that facilitates accurate timely requirements tracking, and top down system modeling/validation minimizes risks and supports flexibility. The Boeing Optical Interconnect System (BOIS) development is a representative example of a complex system design using a top down VHDL design, modeling, and validation process. Program development costs, design time, and risks were minimized while application flexibility was maintained.
{"title":"Optical interconnect system design using a top down design approach","authors":"M. A. Pitts, M. S. Foster","doi":"10.1109/NORTHC.1994.643344","DOIUrl":"https://doi.org/10.1109/NORTHC.1994.643344","url":null,"abstract":"Ever increasing system complexities, limited development resources, and the desire to implement flexible dual use applications are driving the need to reduce system design time, development costs, and risks. Development cost and design time can be reduced by minimizing design iterations and identifying roadblocks early in the design cycle. In addition, utilizing a hierarchical top down process that facilitates accurate timely requirements tracking, and top down system modeling/validation minimizes risks and supports flexibility. The Boeing Optical Interconnect System (BOIS) development is a representative example of a complex system design using a top down VHDL design, modeling, and validation process. Program development costs, design time, and risks were minimized while application flexibility was maintained.","PeriodicalId":218454,"journal":{"name":"Proceedings of NORTHCON '94","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1994-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116275059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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