Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665204
I. Thoidis, D. Soudris, I. Karafyllidis, A. Thanailakis, T. Stouraitis
A number of novel voltage-mode multiple-valued logic circuits are introduced. Adopting the main features of the true single-phase clocked logic, efficient quaternary logic dynamic and pseudo-static latches, dynamic and static master-slave storage units, and uni-signal controlled pass gates are proposed. These circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode, each of which has two threshold voltages. The proposed circuits exhibit regular, modular, and iterative structure, which means that the MVL circuits are VLSI implementable and can be easily re-designed for any radix of an arithmetic system. Since we use only clock signal, the derived circuits have low power dissipation. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.
{"title":"Multiple-valued logic voltage-mode storage circuits based on true-single-phase clocked logic","authors":"I. Thoidis, D. Soudris, I. Karafyllidis, A. Thanailakis, T. Stouraitis","doi":"10.1109/GLSV.1998.665204","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665204","url":null,"abstract":"A number of novel voltage-mode multiple-valued logic circuits are introduced. Adopting the main features of the true single-phase clocked logic, efficient quaternary logic dynamic and pseudo-static latches, dynamic and static master-slave storage units, and uni-signal controlled pass gates are proposed. These circuits use two kinds of MOS transistors, i.e., enhancement and depletion mode, each of which has two threshold voltages. The proposed circuits exhibit regular, modular, and iterative structure, which means that the MVL circuits are VLSI implementable and can be easily re-designed for any radix of an arithmetic system. Since we use only clock signal, the derived circuits have low power dissipation. Comparisons with existing circuits prove substantial improvements in terms of speed, power consumption, and transistor count.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129442155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665308
M. Aref, K. Elleithy
In this paper a new formal hardware verification approach based on object oriented techniques is presented. The HOOVER system (Hardware Object Oriented VERification) is described. A cell library of different hardware components has been implemented as classes. Components in the cell library are described at the transistor level, gate level, logical level, and functional level. The verification of a CMOS inverter and 1-bit CMOS adder using HOOVER is given in the paper.
{"title":"HOOVER: hardware object-oriented verification","authors":"M. Aref, K. Elleithy","doi":"10.1109/GLSV.1998.665308","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665308","url":null,"abstract":"In this paper a new formal hardware verification approach based on object oriented techniques is presented. The HOOVER system (Hardware Object Oriented VERification) is described. A cell library of different hardware components has been implemented as classes. Components in the cell library are described at the transistor level, gate level, logical level, and functional level. The verification of a CMOS inverter and 1-bit CMOS adder using HOOVER is given in the paper.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116211411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665203
T. Bakken, J. Choma
The stability of a continuous-time state variable filter is analyzed using the Routh-Hurwitz criterion. This criterion assesses stability by indicating the number of poles that lie in the right-half plane. The filter is examined separately with integrators implemented with an op-amp and an OTA-C. Both amplifier types are characterized by a dominant-pole frequency response, and the stability of each implementation is compared. HSPICE simulations confirm the theoretical analyses, which indicate that the gain-bandwidth product of the op-amps and the bandwidth of the OTAs must be much larger than the desired frequency of operation to ensure stability. Since the analyses assume a dominant-pole response, all higher-order poles of the actual amplifier must also be much greater than the unity-gain frequency to minimize excess phase.
{"title":"Stability of a continuous-time state variable filter with op-amp and OTA-C integrators","authors":"T. Bakken, J. Choma","doi":"10.1109/GLSV.1998.665203","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665203","url":null,"abstract":"The stability of a continuous-time state variable filter is analyzed using the Routh-Hurwitz criterion. This criterion assesses stability by indicating the number of poles that lie in the right-half plane. The filter is examined separately with integrators implemented with an op-amp and an OTA-C. Both amplifier types are characterized by a dominant-pole frequency response, and the stability of each implementation is compared. HSPICE simulations confirm the theoretical analyses, which indicate that the gain-bandwidth product of the op-amps and the bandwidth of the OTAs must be much larger than the desired frequency of operation to ensure stability. Since the analyses assume a dominant-pole response, all higher-order poles of the actual amplifier must also be much greater than the unity-gain frequency to minimize excess phase.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127695592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665226
S. Sadeghi-Emamchaie, G. Jullien, V. Dimitrov, W. Miller
This paper describes techniques for using locally connected analog cellular neural networks (CNNs) to implement digital arithmetic arrays; the arithmetic is implemented using a recently disclosed Double-Base Number System (DBNS). The CNN arrays are targeted for low power low-noise DSP applications where lower slew rate during transitions is a potential advantage. Specifically, we demonstrate that a CNN array, using a simple nonlinear feedback template, with hysteresis, can perform arbitrary length arithmetic with good performance in terms of stability and robustness. The principles presented in this paper can also be used to implement arithmetic in other number systems such as the binary number system.
{"title":"Digital arithmetic using analog arrays","authors":"S. Sadeghi-Emamchaie, G. Jullien, V. Dimitrov, W. Miller","doi":"10.1109/GLSV.1998.665226","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665226","url":null,"abstract":"This paper describes techniques for using locally connected analog cellular neural networks (CNNs) to implement digital arithmetic arrays; the arithmetic is implemented using a recently disclosed Double-Base Number System (DBNS). The CNN arrays are targeted for low power low-noise DSP applications where lower slew rate during transitions is a potential advantage. Specifically, we demonstrate that a CNN array, using a simple nonlinear feedback template, with hysteresis, can perform arbitrary length arithmetic with good performance in terms of stability and robustness. The principles presented in this paper can also be used to implement arithmetic in other number systems such as the binary number system.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131401267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665205
J. Navarro, W. Noije
A new optimization criterion, the propagation of the minimum width pulse through the buffer is studied for design of tapered buffers draining capacitive loads. Contrary to the classic minimum delay criterion, this one produces buffers which support maximum speed signal propagation. Simulation results for a 0.8 /spl mu/m and a 0.35 /spl mu/m CMOS processes are analyzed. Semi-empirical relations are proposed to relate the minimum width pulse with the inverter gain ratio, the number of inverters, and the capacitive load. Additionally, a brief study of the delay skew of tapered buffers due to mismatching as a function of the gain ratio is done, showing that no severe degradation appears with small gain ratios. Finally, this work points out that buffers with small gain ratios should reach higher speeds, nearly 30% over the speed of buffers with gain ratio larger than a factor of 3.
{"title":"CMOS tapered buffer design for small width clock/data signal propagation","authors":"J. Navarro, W. Noije","doi":"10.1109/GLSV.1998.665205","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665205","url":null,"abstract":"A new optimization criterion, the propagation of the minimum width pulse through the buffer is studied for design of tapered buffers draining capacitive loads. Contrary to the classic minimum delay criterion, this one produces buffers which support maximum speed signal propagation. Simulation results for a 0.8 /spl mu/m and a 0.35 /spl mu/m CMOS processes are analyzed. Semi-empirical relations are proposed to relate the minimum width pulse with the inverter gain ratio, the number of inverters, and the capacitive load. Additionally, a brief study of the delay skew of tapered buffers due to mismatching as a function of the gain ratio is done, showing that no severe degradation appears with small gain ratios. Finally, this work points out that buffers with small gain ratios should reach higher speeds, nearly 30% over the speed of buffers with gain ratio larger than a factor of 3.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115501792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665253
C. Samori, A. Lacaita, A. Zanchi, P. Vita
VCO for wireless receivers must fulfil tight requirements of phase noise and their complete integration in silicon VLSI technologies is still an open issue due to the low quality factor of the inductors. In this paper we address some of the constraints met in the design of low noise oscillator stages: the tank topology and its quality factor, the dynamics of the transconductor stage and its loading effects, the limitation resulting from the AM-to-PM conversion.
{"title":"Design issues of LC tuned oscillators for integrated transceivers","authors":"C. Samori, A. Lacaita, A. Zanchi, P. Vita","doi":"10.1109/GLSV.1998.665253","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665253","url":null,"abstract":"VCO for wireless receivers must fulfil tight requirements of phase noise and their complete integration in silicon VLSI technologies is still an open issue due to the low quality factor of the inductors. In this paper we address some of the constraints met in the design of low noise oscillator stages: the tank topology and its quality factor, the dynamics of the transconductor stage and its loading effects, the limitation resulting from the AM-to-PM conversion.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"130 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120864742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665346
T. Hochin, T. Tsuji
This paper proposes a storage structure for graph-oriented databases called the flattened separable directory method. In this method, a data representation graph, which is a unit of the represention graph, is primarily represented with an array of edge or node types. As every node or edge can be accessed without navigation, the values of nodes and/or edges can be quickly evaluated. Experimental evaluations support these characteristics, and clarify that the data insertion performance is high, and that less storage overhead is needed for graphs consisting of many node and edge types.
{"title":"A storage structure for graph-oriented databases using an array of element types","authors":"T. Hochin, T. Tsuji","doi":"10.1109/GLSV.1998.665346","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665346","url":null,"abstract":"This paper proposes a storage structure for graph-oriented databases called the flattened separable directory method. In this method, a data representation graph, which is a unit of the represention graph, is primarily represented with an array of edge or node types. As every node or edge can be accessed without navigation, the values of nodes and/or edges can be quickly evaluated. Experimental evaluations support these characteristics, and clarify that the data insertion performance is high, and that less storage overhead is needed for graphs consisting of many node and edge types.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125746052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665244
K. Raahemifar, M. Ahmadi
This paper provides a simulation-based study of the delay fault testing in logic circuits. It is shown that delay testing is necessary in order to achieve a high defect coverage. By detecting delayed time response in a transistor circuit, three types of faults are detected: (1) faults which cause delayed transitions at the output node due to some open defects, (2) faults which cause an intermediate voltage level at the output node, and (3) most stuck-at faults which halt the circuit at '1' or '0'. An on-line checker is presented which enables the concurrent detection of delay faults. Since one checker is used for each output signal, the area overhead is minimal. This technique does not degrade the speed of the circuit under test (CUT). We show that the test circuit is independent of the size of the CUT. Simulation results show that this technique can be adjusted to fit to any design style.
{"title":"A design-for-testability technique for detecting delay faults in logic circuits","authors":"K. Raahemifar, M. Ahmadi","doi":"10.1109/GLSV.1998.665244","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665244","url":null,"abstract":"This paper provides a simulation-based study of the delay fault testing in logic circuits. It is shown that delay testing is necessary in order to achieve a high defect coverage. By detecting delayed time response in a transistor circuit, three types of faults are detected: (1) faults which cause delayed transitions at the output node due to some open defects, (2) faults which cause an intermediate voltage level at the output node, and (3) most stuck-at faults which halt the circuit at '1' or '0'. An on-line checker is presented which enables the concurrent detection of delay faults. Since one checker is used for each output signal, the area overhead is minimal. This technique does not degrade the speed of the circuit under test (CUT). We show that the test circuit is independent of the size of the CUT. Simulation results show that this technique can be adjusted to fit to any design style.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129961878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665230
R. Raina, R. Molyneaux
This paper describes a novel method for generating test stimuli for digital systems. By taking advantage of certain properties of the Design Under Validation, the method can be used to generate test stimuli that are random as well as self-testing. We discuss the requirements and limitations of this method on practical designs. The use of this method for High-Level Design Validation of caches in PowerPC/sup TM/ microprocessors is also described. The paper concludes by identifying areas where further work is needed.
{"title":"Random self-test method applications on PowerPC/sup TM/ microprocessor caches","authors":"R. Raina, R. Molyneaux","doi":"10.1109/GLSV.1998.665230","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665230","url":null,"abstract":"This paper describes a novel method for generating test stimuli for digital systems. By taking advantage of certain properties of the Design Under Validation, the method can be used to generate test stimuli that are random as well as self-testing. We discuss the requirements and limitations of this method on practical designs. The use of this method for High-Level Design Validation of caches in PowerPC/sup TM/ microprocessors is also described. The paper concludes by identifying areas where further work is needed.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"os-13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127972935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665201
M. Bhattacharya, P. Mazumder
Threshold gates consisting of RTDs in conjunction, with HBTs or CHFETs or MOS transistors can form extremely compact, ultrafast, digital logic alternatives. The resonant tunneling phenomenon causes these circuits to exhibit super-high-speed switching capabilities. Additionally, by virtue of being threshold logic gates, they are guaranteed to be more compact than traditional digital logic circuits while achieving the same functionality. However, reliable logic design with these gates will need a thorough understanding of their noise performance and power dissipation among other things. In this paper, we present an analytical study of the noise performance of these threshold gates supplemented by computer simulation results, with the objective of obtaining reliable circuit design guidelines.
{"title":"Noise margins of threshold logic gates containing resonant tunneling diodes","authors":"M. Bhattacharya, P. Mazumder","doi":"10.1109/GLSV.1998.665201","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665201","url":null,"abstract":"Threshold gates consisting of RTDs in conjunction, with HBTs or CHFETs or MOS transistors can form extremely compact, ultrafast, digital logic alternatives. The resonant tunneling phenomenon causes these circuits to exhibit super-high-speed switching capabilities. Additionally, by virtue of being threshold logic gates, they are guaranteed to be more compact than traditional digital logic circuits while achieving the same functionality. However, reliable logic design with these gates will need a thorough understanding of their noise performance and power dissipation among other things. In this paper, we present an analytical study of the noise performance of these threshold gates supplemented by computer simulation results, with the objective of obtaining reliable circuit design guidelines.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125489334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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