Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665198
A. Shams, M. Bayoumi
A new low power CMOS 1-bit full adder cell is presented. It is based on recent design of XOR and XNOR gates, and pass-transistors, it has 17 transistors. This cell has been compared to two widely used efficient adder cells; the transmission function full adder cell (16 transistors) and the low power adder cell (14 transistors). The new cell has no short circuit power and lower dynamic power (than the other adder cells), because of less number and magnitude of circuit capacitances. It consumes 10% to 15% less power than the other two cells. A comparative analysis (using Magic and Hspice) for 8-bit ripple carry and carry select adders shows that the adders based on the new cell can save up to 25% of power consumption.
{"title":"A new full adder cell for low-power applications","authors":"A. Shams, M. Bayoumi","doi":"10.1109/GLSV.1998.665198","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665198","url":null,"abstract":"A new low power CMOS 1-bit full adder cell is presented. It is based on recent design of XOR and XNOR gates, and pass-transistors, it has 17 transistors. This cell has been compared to two widely used efficient adder cells; the transmission function full adder cell (16 transistors) and the low power adder cell (14 transistors). The new cell has no short circuit power and lower dynamic power (than the other adder cells), because of less number and magnitude of circuit capacitances. It consumes 10% to 15% less power than the other two cells. A comparative analysis (using Magic and Hspice) for 8-bit ripple carry and carry select adders shows that the adders based on the new cell can save up to 25% of power consumption.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132817412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665215
Ashutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John
Advances in VLSI technology and processor architectures have resulted in a tremendous increase in processor speeds and memory capacities. However, memory latencies have failed to improve as rapidly, making memory systems the performance bottlenecks in most high performance processor architectures. Caching is a time-tested mechanism to solve this speed disparity. Among the different cache mapping strategies, direct mapping is the only configuration where the critical path is merely the time required to access a RAM. Although direct mapped caches are preferable considering hit-access times, they have poor hit ratios compared to associative caches. The difference-bit cache proposed by Juan, Lang and Navarro (1996), is functionally equivalent to a two-way set-associative cache but tries to achieve an access time smaller than that of a conventional two-way set-associative cache and close to that of a direct-mapped cache. We modeled and analyzed the difference-bit cache to prove the hypothesis of its small access time. We have also tried to prove that the access time advantage of the difference-bit cache improves over the conventional two-way set-associative cache with an increase in the cache size. Finally we have tried to analyze the trade-off involved in applying these techniques to a higher associativity cache.
{"title":"Modeling and analysis of the difference-bit cache","authors":"Ashutosh Kulkarni, Navin Chander, Soumya Pillai, Lizy Kurian John","doi":"10.1109/GLSV.1998.665215","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665215","url":null,"abstract":"Advances in VLSI technology and processor architectures have resulted in a tremendous increase in processor speeds and memory capacities. However, memory latencies have failed to improve as rapidly, making memory systems the performance bottlenecks in most high performance processor architectures. Caching is a time-tested mechanism to solve this speed disparity. Among the different cache mapping strategies, direct mapping is the only configuration where the critical path is merely the time required to access a RAM. Although direct mapped caches are preferable considering hit-access times, they have poor hit ratios compared to associative caches. The difference-bit cache proposed by Juan, Lang and Navarro (1996), is functionally equivalent to a two-way set-associative cache but tries to achieve an access time smaller than that of a conventional two-way set-associative cache and close to that of a direct-mapped cache. We modeled and analyzed the difference-bit cache to prove the hypothesis of its small access time. We have also tried to prove that the access time advantage of the difference-bit cache improves over the conventional two-way set-associative cache with an increase in the cache size. Finally we have tried to analyze the trade-off involved in applying these techniques to a higher associativity cache.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121778954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665339
K. Davis, S. Venkatesan, L. Delcambre
Electronic Design Automation (EDA) tools, such as layout generators and simulators, have generally focused on algorithms and techniques for hardware design. Data management aspects have not been emphasized, but the volume of data, heterogeneity of data formats, and the evolution/proliferation of tools have made data modeling and data interchange increasingly important research issues. The data sharing problem stems from the fact that related EDA tools are often used in various sequences to manipulate and annotate a single design. In a typical design environment, tools use file-based data storage, with limited data modeling capabilities, and primitive or non-existent query facilities. In order to support current tools, we wish to preserve the semantics of existing hardware description languages in rigorous data models; we propose to capture each existing language in a semantic space model. We view data interchange as a query against one semantic space that produces objects, i.e., query answers, in another semantic space. We define an integrating meta-model, the meta-space, and also define general query operators for transforming objects between semantic spaces. These query operators define both the intension and extension of a query result; the transformed data is described in the type system of the meta-space, thus providing explicit semantics for the shared data. Our modeling approach supports advanced and evolving applications, such as hardware/software codesign, through the ability to retrieve data resident in individual semantic spaces, as well as to share data in semantic spaces from different EDA sources.
{"title":"Sharing electronic design data via semantic spaces","authors":"K. Davis, S. Venkatesan, L. Delcambre","doi":"10.1109/GLSV.1998.665339","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665339","url":null,"abstract":"Electronic Design Automation (EDA) tools, such as layout generators and simulators, have generally focused on algorithms and techniques for hardware design. Data management aspects have not been emphasized, but the volume of data, heterogeneity of data formats, and the evolution/proliferation of tools have made data modeling and data interchange increasingly important research issues. The data sharing problem stems from the fact that related EDA tools are often used in various sequences to manipulate and annotate a single design. In a typical design environment, tools use file-based data storage, with limited data modeling capabilities, and primitive or non-existent query facilities. In order to support current tools, we wish to preserve the semantics of existing hardware description languages in rigorous data models; we propose to capture each existing language in a semantic space model. We view data interchange as a query against one semantic space that produces objects, i.e., query answers, in another semantic space. We define an integrating meta-model, the meta-space, and also define general query operators for transforming objects between semantic spaces. These query operators define both the intension and extension of a query result; the transformed data is described in the type system of the meta-space, thus providing explicit semantics for the shared data. Our modeling approach supports advanced and evolving applications, such as hardware/software codesign, through the ability to retrieve data resident in individual semantic spaces, as well as to share data in semantic spaces from different EDA sources.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128232787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665212
J. Delgado-Frías, Richard Diaz
This paper describes a novel VLSI CMOS implementation of a self-compacting buffer (SCB) for the dynamically allocated multi-queue (DAMQ) switch architecture. The SCB is a scheme that dynamically allocates data regions within the input buffer for each output channel. The proposed implementation provides a high-performance solution to buffered communication switches that are required in interconnection networks. This performance comes from not only the DAMQ approach but also the pipelined implementation and novel circuitry. The major components of the SCB are described in detail in this paper. The system has the capability of performing a read, a write, or a simultaneous read/write operation per cycle due to its pipelined architecture.
{"title":"A VLSI self-compacting buffer for DAMQ communication switches","authors":"J. Delgado-Frías, Richard Diaz","doi":"10.1109/GLSV.1998.665212","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665212","url":null,"abstract":"This paper describes a novel VLSI CMOS implementation of a self-compacting buffer (SCB) for the dynamically allocated multi-queue (DAMQ) switch architecture. The SCB is a scheme that dynamically allocates data regions within the input buffer for each output channel. The proposed implementation provides a high-performance solution to buffered communication switches that are required in interconnection networks. This performance comes from not only the DAMQ approach but also the pipelined implementation and novel circuitry. The major components of the SCB are described in detail in this paper. The system has the capability of performing a read, a write, or a simultaneous read/write operation per cycle due to its pipelined architecture.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128470660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665210
Can K. Sandalci, S. Kiaei
Analysis of CMOS direct conversion architecture with adaptive DC offset compensation is presented. Due to process mismatches and local oscillator (LO) crosstalk, DC offsets up to 30 mV are observed at the mixer output. For a practical direct conversion or zero-IF down-conversion system, the incoming RF signal can be as low as -100 dBm or few microvolts at this stage and any LO coupling will cause a DC offset orders of magnitude larger than the received signal. The DC offset needs to be effectively reduced to prevent the consecutive gain stages from entering saturation and destroying the RF signal. To achieve this, an adaptive DC shifting circuit is presented. Adding a tunable DC offset on the LO signal can effectively counteract the output DC offset by exploiting the quadratic LO dependence of the process mismatch induced offsets. In addition to that, DSP approaches for adaptively generating the control signals for the DC shifting circuitry are investigated.
{"title":"Analysis of adaptive CMOS down conversion mixers","authors":"Can K. Sandalci, S. Kiaei","doi":"10.1109/GLSV.1998.665210","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665210","url":null,"abstract":"Analysis of CMOS direct conversion architecture with adaptive DC offset compensation is presented. Due to process mismatches and local oscillator (LO) crosstalk, DC offsets up to 30 mV are observed at the mixer output. For a practical direct conversion or zero-IF down-conversion system, the incoming RF signal can be as low as -100 dBm or few microvolts at this stage and any LO coupling will cause a DC offset orders of magnitude larger than the received signal. The DC offset needs to be effectively reduced to prevent the consecutive gain stages from entering saturation and destroying the RF signal. To achieve this, an adaptive DC shifting circuit is presented. Adding a tunable DC offset on the LO signal can effectively counteract the output DC offset by exploiting the quadratic LO dependence of the process mismatch induced offsets. In addition to that, DSP approaches for adaptively generating the control signals for the DC shifting circuitry are investigated.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121874382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665284
T. Doom, Jennifer L. White, A. S. Wojcik, G. Chisholm
The problem of finding meaningful subcircuits in a logic layout appears in many contexts in computer-aided design. Existing techniques rely upon finding exact matchings of subcircuit structure within the layout. These syntactic techniques fail to identify functionally equivalent subcircuits which are differently implemented optimized, or otherwise obfuscated. We present a mechanism for identifying functionally equivalent subcircuits which is capable of overcoming many of these limitations. Such semantic matching is particularly useful in the field of design recovery.
{"title":"Identifying high-level components in combinational circuits","authors":"T. Doom, Jennifer L. White, A. S. Wojcik, G. Chisholm","doi":"10.1109/GLSV.1998.665284","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665284","url":null,"abstract":"The problem of finding meaningful subcircuits in a logic layout appears in many contexts in computer-aided design. Existing techniques rely upon finding exact matchings of subcircuit structure within the layout. These syntactic techniques fail to identify functionally equivalent subcircuits which are differently implemented optimized, or otherwise obfuscated. We present a mechanism for identifying functionally equivalent subcircuits which is capable of overcoming many of these limitations. Such semantic matching is particularly useful in the field of design recovery.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131280844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665340
Rick Miller
As part of ARPA's RASSP technology program, we developed a hardware/software cosynthesis algorithm that was prototyped in C++. This initial prototype was developed in C++ using PCCTS, Tcl, Tcl/TK, and Tcl-DP. When this environment became unwieldy due to changing hardware development platforms and software packages, a second prototype was built in Java. This paper describes architectural features of the prototype and how they were addressed in Java.
{"title":"VHDL-based EDA tool implementation with Java","authors":"Rick Miller","doi":"10.1109/GLSV.1998.665340","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665340","url":null,"abstract":"As part of ARPA's RASSP technology program, we developed a hardware/software cosynthesis algorithm that was prototyped in C++. This initial prototype was developed in C++ using PCCTS, Tcl, Tcl/TK, and Tcl-DP. When this environment became unwieldy due to changing hardware development platforms and software packages, a second prototype was built in Java. This paper describes architectural features of the prototype and how they were addressed in Java.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125891429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665336
M. Khellah, M. Elmasry
This paper presents a simple, yet efficient method to characterize the effective capacitance in data-path macros for architectural-level power estimation. Given a library of hard-macros, a capacitance model based on linear regression is derived for each macro. A transistor-level tool is employed for capacitance extraction. The capacitance models can be used during architectural-level power estimation. Unlike previous approaches, our characterization methodology assumes no specific word-level statistics of the input data, requires little knowledge about the structure of the modules, allows the user to trade-off accuracy and characterization time, and propagates effective capacitance directly from transistor-level (real) implementations. Simulation experiments on a set of data-path components with various sizes are performed. Compared to a previously published approach, our scheme significantly improves the accuracy of RTL power estimation and produces results within 15% from a transistor-level tool on the average.
{"title":"Effective capacitance macro-modelling for architectural-level power estimation","authors":"M. Khellah, M. Elmasry","doi":"10.1109/GLSV.1998.665336","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665336","url":null,"abstract":"This paper presents a simple, yet efficient method to characterize the effective capacitance in data-path macros for architectural-level power estimation. Given a library of hard-macros, a capacitance model based on linear regression is derived for each macro. A transistor-level tool is employed for capacitance extraction. The capacitance models can be used during architectural-level power estimation. Unlike previous approaches, our characterization methodology assumes no specific word-level statistics of the input data, requires little knowledge about the structure of the modules, allows the user to trade-off accuracy and characterization time, and propagates effective capacitance directly from transistor-level (real) implementations. Simulation experiments on a set of data-path components with various sizes are performed. Compared to a previously published approach, our scheme significantly improves the accuracy of RTL power estimation and produces results within 15% from a transistor-level tool on the average.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126407333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665197
Y. Ismail, E. Friedman, J. Neves
The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented These solutions agree with AS/X circuit simulations within 11% error for a wide range of transistor widths and line impedances. The ratio of the short-circuit to dynamic power is shown to be less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. The total power consumption is expected to decrease as inductance effects become more significant as compared to an RC dominated interconnect.
{"title":"Dynamic and short-circuit power of CMOS gates driving lossless transmission lines","authors":"Y. Ismail, E. Friedman, J. Neves","doi":"10.1109/GLSV.1998.665197","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665197","url":null,"abstract":"The dynamic and short-circuit power consumption of a CMOS gate driving an LC transmission line as a limiting case of an RLC transmission line is investigated in this paper. Closed form solutions for the output voltage and short-circuit power of a CMOS gate driving an LC transmission line are presented These solutions agree with AS/X circuit simulations within 11% error for a wide range of transistor widths and line impedances. The ratio of the short-circuit to dynamic power is shown to be less than 7% for CMOS gates driving LC transmission lines where the line is matched or underdriven. The total power consumption is expected to decrease as inductance effects become more significant as compared to an RC dominated interconnect.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124707183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665207
J. Navarro, W. Noije
The design of an 8:1 multiplexer circuit, for SDH/SONET data transmission systems, is presented. In order to achieve maximum transmission rates, new circuits, high speed input/output converters for ECL-CMOS levels and modified true single phase clocked (TSPC) cells, as well as new techniques for clock buffer optimization, were applied. The multiplexer was implemented in a 0.8 /spl mu/m CMOS process (0.7 /spl mu/m effective length) achieved 1.7 Gbit/s rate and 42.6 /spl mu/W/MHz power consumption at 5 V. These results were compared to a previous implementation (in the same process), and to other recently published works, showing superior performances.
{"title":"Design of an 8:1 MUX at 1.7 Gbit/s in 0.8 /spl mu/m CMOS technology","authors":"J. Navarro, W. Noije","doi":"10.1109/GLSV.1998.665207","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665207","url":null,"abstract":"The design of an 8:1 multiplexer circuit, for SDH/SONET data transmission systems, is presented. In order to achieve maximum transmission rates, new circuits, high speed input/output converters for ECL-CMOS levels and modified true single phase clocked (TSPC) cells, as well as new techniques for clock buffer optimization, were applied. The multiplexer was implemented in a 0.8 /spl mu/m CMOS process (0.7 /spl mu/m effective length) achieved 1.7 Gbit/s rate and 42.6 /spl mu/W/MHz power consumption at 5 V. These results were compared to a previous implementation (in the same process), and to other recently published works, showing superior performances.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132968445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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