Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665199
V. Varshavsky
Circuits on threshold elements have aroused considerable interest in recent years. One of the possible approaches of their implementation is using output wired CMOS inverters. The model of such an element is a CMOS pair with variable /spl beta/ of fully open p- and n-transistors. This model is specified by the ratio form of threshold function. It has been proved that any threshold function can be rewritten in ratio form. This gives us an evident way of /spl beta/-driven implementation of threshold functions. It has the following differences from implementation on output wired CMOS invertors: -/spl beta/DTE requires one transistor per weight unit rather than two; -the implementability of /spl beta/DTE depends only on threshold value, not on the input weights sum. The analysis of /spl beta/DTE implementability, examples of circuits and results of their SPICE simulation are given.
{"title":"/spl beta/-driven threshold elements","authors":"V. Varshavsky","doi":"10.1109/GLSV.1998.665199","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665199","url":null,"abstract":"Circuits on threshold elements have aroused considerable interest in recent years. One of the possible approaches of their implementation is using output wired CMOS inverters. The model of such an element is a CMOS pair with variable /spl beta/ of fully open p- and n-transistors. This model is specified by the ratio form of threshold function. It has been proved that any threshold function can be rewritten in ratio form. This gives us an evident way of /spl beta/-driven implementation of threshold functions. It has the following differences from implementation on output wired CMOS invertors: -/spl beta/DTE requires one transistor per weight unit rather than two; -the implementability of /spl beta/DTE depends only on threshold value, not on the input weights sum. The analysis of /spl beta/DTE implementability, examples of circuits and results of their SPICE simulation are given.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123190492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665303
D. Stroobandt, F. Kurdahi
Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those properties is essential for improving placement and routing techniques for digital circuits. Previous work on estimating design properties failed to take multi-point nets into account. All nets were assumed to be 2-point nets (especially for estimating the number of nets). In this paper we aim at characterizing multi-point nets in electronic designs. We develop a model for the behaviour of multi-point nets during the partitioning process. The resulting distribution of nets over their net degree is validated through comparison with benchmark data.
{"title":"On the characterization of multi-point nets in electronic designs","authors":"D. Stroobandt, F. Kurdahi","doi":"10.1109/GLSV.1998.665303","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665303","url":null,"abstract":"Important layout properties of electronic designs include interconnection length values, clock speed, area requirements, and power dissipation. A reliable estimation of those properties is essential for improving placement and routing techniques for digital circuits. Previous work on estimating design properties failed to take multi-point nets into account. All nets were assumed to be 2-point nets (especially for estimating the number of nets). In this paper we aim at characterizing multi-point nets in electronic designs. We develop a model for the behaviour of multi-point nets during the partitioning process. The resulting distribution of nets over their net degree is validated through comparison with benchmark data.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129036318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665249
R. Caverly
There is increasing interest in the use of CMOS circuits for highly integrated high frequency wireless telecommunications systems. This paper presents the results of on-going work into the development of a cell library that includes many of the circuit elements required for the high frequency sub-system of a communications integrated circuit. The cells were fabricated using standard MOSIS processes and measurement results are presented. The full design files, testing results and circuit tutorials describing the cells and how they interface with baseband circuits are available from the author.
{"title":"Development of a CMOS cell library for RF wireless and telecommunications applications","authors":"R. Caverly","doi":"10.1109/GLSV.1998.665249","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665249","url":null,"abstract":"There is increasing interest in the use of CMOS circuits for highly integrated high frequency wireless telecommunications systems. This paper presents the results of on-going work into the development of a cell library that includes many of the circuit elements required for the high frequency sub-system of a communications integrated circuit. The cells were fabricated using standard MOSIS processes and measurement results are presented. The full design files, testing results and circuit tutorials describing the cells and how they interface with baseband circuits are available from the author.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121100830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665202
A. Yusof, Lim Chu Aun, S. Hasan
A 16-bit digitally controlled BiCMOS ring oscillator (DCO) is described. This BiCMOS DCO design provides improved frequency stability under thermal fluctuations. Simulations of a 5-stage DCO using 1 /spl mu/m BiCMOS process parameters achieved controllable frequency range of 90-640 MHz with a linear/quasi-linear range of around 300 MHz. Monotone frequency gain (frequency vs control-word transfer function) with fine stepping (tuning) in several KHz was verified This augurs the prospect of accurate frequency lock in a BiCMOS all digital PLL (ADPLL) application in digital VLSI communication systems. Worstcase jitter due to digital control transitions at pathological control-word boundaries for the BiCMOS DCO was observed to be less than 50 ps, which is lower than that for the CMOS DCO.
{"title":"600 MHz digitally controlled BiCMOS oscillator (DCO) for VLSI signal processing and communication applications","authors":"A. Yusof, Lim Chu Aun, S. Hasan","doi":"10.1109/GLSV.1998.665202","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665202","url":null,"abstract":"A 16-bit digitally controlled BiCMOS ring oscillator (DCO) is described. This BiCMOS DCO design provides improved frequency stability under thermal fluctuations. Simulations of a 5-stage DCO using 1 /spl mu/m BiCMOS process parameters achieved controllable frequency range of 90-640 MHz with a linear/quasi-linear range of around 300 MHz. Monotone frequency gain (frequency vs control-word transfer function) with fine stepping (tuning) in several KHz was verified This augurs the prospect of accurate frequency lock in a BiCMOS all digital PLL (ADPLL) application in digital VLSI communication systems. Worstcase jitter due to digital control transitions at pathological control-word boundaries for the BiCMOS DCO was observed to be less than 50 ps, which is lower than that for the CMOS DCO.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116435730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665328
Kaishen Wang, T. Yu, E. Sha
Many real time applications such as multimedia and DSP systems require high throughput, so it is necessary to have special purpose designs for them. Loop pipelining is an effective approach to reduce the total execution time of loops. While most previous research concentrates on the scheduling of computation, the experiments show that data access may give significant overhead if the register resource is limited. This paper studies the register constraint problem and presents Register Constrained Rotation Scheduling (RCRS), including the algorithm analyzing the number of required registers for loops and two classes of algorithms based on different assumptions. The first class is for loop scheduling with a given number of registers. If the number of registers is too stringent, the second class of algorithms are applied by inserting necessary LOAD/STORE operations into the loop schedule. Through the series of experiments, the RCRS algorithms are shown to achieve near optimal schedule length while satisfying register constraints.
{"title":"RCRS: a framework for loop scheduling with limited number of registers","authors":"Kaishen Wang, T. Yu, E. Sha","doi":"10.1109/GLSV.1998.665328","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665328","url":null,"abstract":"Many real time applications such as multimedia and DSP systems require high throughput, so it is necessary to have special purpose designs for them. Loop pipelining is an effective approach to reduce the total execution time of loops. While most previous research concentrates on the scheduling of computation, the experiments show that data access may give significant overhead if the register resource is limited. This paper studies the register constraint problem and presents Register Constrained Rotation Scheduling (RCRS), including the algorithm analyzing the number of required registers for loops and two classes of algorithms based on different assumptions. The first class is for loop scheduling with a given number of registers. If the number of registers is too stringent, the second class of algorithms are applied by inserting necessary LOAD/STORE operations into the loop schedule. Through the series of experiments, the RCRS algorithms are shown to achieve near optimal schedule length while satisfying register constraints.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124305794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665213
A. Harvin, J. Delgado-Frías
In this paper, we propose a dictionary machine emulation using a novel VLSI tree structure that operates on the dictionary using a blocking technique. We show that dictionary machine operations can be performed through the implementation of a number of processing and communication tasks overlapped on a simple structure. By manipulating the key-records bit serially, and storing them in an external memory rather than within the layers of the structure, we show that the size of the dictionary is limited only by the capacity of the external memory. This structure, which consists of multiple units, can be implemented in VLSI onto a single-chip. The key advantage of our structure is that it provides a means of implementing a high speed and low cost dictionary machine with virtually unlimited capacity; thus, eliminating the need for multiple chips should the dictionary expand. We have that an exhaustive search on a 2048 key-record dictionary can be performed in 29.78 /spl mu/s.
{"title":"A dictionary machine emulation on a VLSI computing tree system","authors":"A. Harvin, J. Delgado-Frías","doi":"10.1109/GLSV.1998.665213","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665213","url":null,"abstract":"In this paper, we propose a dictionary machine emulation using a novel VLSI tree structure that operates on the dictionary using a blocking technique. We show that dictionary machine operations can be performed through the implementation of a number of processing and communication tasks overlapped on a simple structure. By manipulating the key-records bit serially, and storing them in an external memory rather than within the layers of the structure, we show that the size of the dictionary is limited only by the capacity of the external memory. This structure, which consists of multiple units, can be implemented in VLSI onto a single-chip. The key advantage of our structure is that it provides a means of implementing a high speed and low cost dictionary machine with virtually unlimited capacity; thus, eliminating the need for multiple chips should the dictionary expand. We have that an exhaustive search on a 2048 key-record dictionary can be performed in 29.78 /spl mu/s.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132847878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665270
L. Luh, J. Choma, J. Draper
A novel architecture for a second-order continuous-time switched-current /spl Sigma//spl Delta/ modulator is presented. The loop delay is reduced by predicting the states of the second integrator and feeding the predicted states to the comparator. The predicted states are generated by summing three scaled current mode signals. A gain-manager is used to accurately control the integrator gain to generate the predicted states and stabilize the system. A newly designed high-speed current-mode comparator is capable of summing the three scaled current inputs and comparing them. With a 50 MHz sampling rate, it has achieved 60 dB dynamic range (10-bit) at 1 MHz. The modulator has been fabricated in a 2 /spl mu/m CMOS process with an active area of 0.37 mm/sup 2/. The power dissipation is 16.6 mW from a 5 V single power supply.
{"title":"A continuous-time switched-current /spl Sigma//spl Delta/ modulator with reduced loop delay","authors":"L. Luh, J. Choma, J. Draper","doi":"10.1109/GLSV.1998.665270","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665270","url":null,"abstract":"A novel architecture for a second-order continuous-time switched-current /spl Sigma//spl Delta/ modulator is presented. The loop delay is reduced by predicting the states of the second integrator and feeding the predicted states to the comparator. The predicted states are generated by summing three scaled current mode signals. A gain-manager is used to accurately control the integrator gain to generate the predicted states and stabilize the system. A newly designed high-speed current-mode comparator is capable of summing the three scaled current inputs and comparing them. With a 50 MHz sampling rate, it has achieved 60 dB dynamic range (10-bit) at 1 MHz. The modulator has been fabricated in a 2 /spl mu/m CMOS process with an active area of 0.37 mm/sup 2/. The power dissipation is 16.6 mW from a 5 V single power supply.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126941161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665196
R. Hobson
Power saving techniques for CMOS programmable logic arrays (PLAs) are discussed. Two new techniques are introduced, an AND-plane pulse generator, and wired-OR CMOS. Power reduction in excess of 75% over pseudo-NMOS techniques and 50% over some clocked PLA techniques is possible.
{"title":"Power reducing techniques for clocked CMOS PLAs","authors":"R. Hobson","doi":"10.1109/GLSV.1998.665196","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665196","url":null,"abstract":"Power saving techniques for CMOS programmable logic arrays (PLAs) are discussed. Two new techniques are introduced, an AND-plane pulse generator, and wired-OR CMOS. Power reduction in excess of 75% over pseudo-NMOS techniques and 50% over some clocked PLA techniques is possible.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132282476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665331
H. Marck, J. Depreitere, D. Stroobandt, J. V. Campenhout
Designs targeted for FPGAs are becoming increasingly larger and more complex. The need for I/O often surpasses the number of I/O pads that can be provided at the perimeter of the FPGA chip. As a result, these designs have to be implemented in larger FPGAs, the size of which is fired by the number of I/O pads and not by the logic needed, reducing the performance of the implementation. Providing FPGA chips with I/O pads that are spread out across the whole chip area drastically reduces this problem. In this paper, we present a quantitative analysis of the impact of area-I/O in FPGAs.
{"title":"A quantitative study of the benefits of area-I/O in FPGAs","authors":"H. Marck, J. Depreitere, D. Stroobandt, J. V. Campenhout","doi":"10.1109/GLSV.1998.665331","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665331","url":null,"abstract":"Designs targeted for FPGAs are becoming increasingly larger and more complex. The need for I/O often surpasses the number of I/O pads that can be provided at the perimeter of the FPGA chip. As a result, these designs have to be implemented in larger FPGAs, the size of which is fired by the number of I/O pads and not by the logic needed, reducing the performance of the implementation. Providing FPGA chips with I/O pads that are spread out across the whole chip area drastically reduces this problem. In this paper, we present a quantitative analysis of the impact of area-I/O in FPGAs.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114269365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665220
B. Alhalabi, Q. Malluhi, R. Ayoubi
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally update the weights from the analog back-propagation signals for fast on-chip learning. In this circuit, the weight is stored as a 5-bit digital number, which controls the gates of five pass transistors allowing five binary-weighted (1,2,4,8,16) voltage references to integrate at a voltage adder. The output of the voltage adder is the analog weight. The 5-bit register is designed as an up/down counter so that every pulse on the up/down input will increase/decrease the weight by one level out of 32 possible levels. The learning circuit takes the analog graded error signal and generates two pulse streams for up/down counting depending on the sign of the error signal. The duration of the pulse stream is proportional to the magnitude of the error signal. This complete modular synaptic body (storage and learning technique) is appropriate for large scaleable analog VLSI neural networks because it handles recall and learning operations at the same speed with full parallelism.
{"title":"Non-refreshing analog neural storage tailored for on-chip learning","authors":"B. Alhalabi, Q. Malluhi, R. Ayoubi","doi":"10.1109/GLSV.1998.665220","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665220","url":null,"abstract":"In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally update the weights from the analog back-propagation signals for fast on-chip learning. In this circuit, the weight is stored as a 5-bit digital number, which controls the gates of five pass transistors allowing five binary-weighted (1,2,4,8,16) voltage references to integrate at a voltage adder. The output of the voltage adder is the analog weight. The 5-bit register is designed as an up/down counter so that every pulse on the up/down input will increase/decrease the weight by one level out of 32 possible levels. The learning circuit takes the analog graded error signal and generates two pulse streams for up/down counting depending on the sign of the error signal. The duration of the pulse stream is proportional to the magnitude of the error signal. This complete modular synaptic body (storage and learning technique) is appropriate for large scaleable analog VLSI neural networks because it handles recall and learning operations at the same speed with full parallelism.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123653291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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