Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665264
J. Long
It is anticipated that the next generation of wireless systems will deliver voice and data services at carrier frequencies extending up to 6 GHz. The front-end circuits for these radios must be aggressively designed in order to deal with issues such as analog and digital compatibility, higher linearity imposed by broadband signal processing at IF, low supply voltage to minimize size, weight and power consumption, as well as operation in multiple frequency bands. The challenges and opportunities facing the designer of these radio frequency (RF) front-end IC's in silicon will be addressed in this paper from both the technological and circuit perspectives.
{"title":"Next generation narrowband RF front-ends in silicon IC technology","authors":"J. Long","doi":"10.1109/GLSV.1998.665264","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665264","url":null,"abstract":"It is anticipated that the next generation of wireless systems will deliver voice and data services at carrier frequencies extending up to 6 GHz. The front-end circuits for these radios must be aggressively designed in order to deal with issues such as analog and digital compatibility, higher linearity imposed by broadband signal processing at IF, low supply voltage to minimize size, weight and power consumption, as well as operation in multiple frequency bands. The challenges and opportunities facing the designer of these radio frequency (RF) front-end IC's in silicon will be addressed in this paper from both the technological and circuit perspectives.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132126191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665275
W. Gosti, A. Sangiovanni-Vincentelli, T. Villa, A. Saldanha
We address the problem of encoding the state variables of a finite state machine such that the BDD representing its characteristic function has the minimum number of nodes. We present an exact formulation of the problem. Our formulation characterizes the two BDD reduction rules by deriving conditions under which these reduction rules can be applied. We then provide an algorithm that finds these conditions and solves the problem by formulating it as a 2-CNF formula and extracting all its prime implicants. In addition to this, we implemented a simulated annealing algorithm for this problem and provide a thorough experiment of the impact of encoding on a BDD representing an FSM with different orderings.
{"title":"An exact input encoding algorithm for BDDs representing FSMs","authors":"W. Gosti, A. Sangiovanni-Vincentelli, T. Villa, A. Saldanha","doi":"10.1109/GLSV.1998.665275","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665275","url":null,"abstract":"We address the problem of encoding the state variables of a finite state machine such that the BDD representing its characteristic function has the minimum number of nodes. We present an exact formulation of the problem. Our formulation characterizes the two BDD reduction rules by deriving conditions under which these reduction rules can be applied. We then provide an algorithm that finds these conditions and solves the problem by formulating it as a 2-CNF formula and extracting all its prime implicants. In addition to this, we implemented a simulated annealing algorithm for this problem and provide a thorough experiment of the impact of encoding on a BDD representing an FSM with different orderings.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133572805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665234
B. Provost, E. Sánchez-Sinencio, A. M. Brosa
Being able to fully test a circuit is an important issue for quality manufacturing. Unlike fault analysis for digital circuits, analog fault analysis has been comparatively slow to evolve. The purpose of this paper is to study the feasibility of the time domain response analysis as a test method for analog circuits. The approach was to first study the fault coverage obtained by testing the main parameters of the new NGCC amplifier, which shows the feasibility of built-in self test in time-domain. A circuit macromodel to implement a time-domain built-in self-test circuit was then proposed.
{"title":"A unified approach for a time-domain built-in self-test technique and fault detection","authors":"B. Provost, E. Sánchez-Sinencio, A. M. Brosa","doi":"10.1109/GLSV.1998.665234","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665234","url":null,"abstract":"Being able to fully test a circuit is an important issue for quality manufacturing. Unlike fault analysis for digital circuits, analog fault analysis has been comparatively slow to evolve. The purpose of this paper is to study the feasibility of the time domain response analysis as a test method for analog circuits. The approach was to first study the fault coverage obtained by testing the main parameters of the new NGCC amplifier, which shows the feasibility of built-in self test in time-domain. A circuit macromodel to implement a time-domain built-in self-test circuit was then proposed.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116531291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665211
H. Abdel-Aty-Zohdy
Advanced microsystems that include, sensors, interface-circuits, and pattern-recognition integrated monolithically or in a hybrid module are needed for civilian, military, and space applications. These include: automotive, medical applications, environmental engineering, and manufacturing automation. ASICs with Artificial Neural Networks (ANN) are considered in this paper, with the objective of recognizing air-borne volatile organic compounds, especially alcohols, ethers, esters, halocarbons, NH/sub 3/, NO/sub 2/, and other warfare agent simulants. The ASIC inputs are connected to the outputs from array-distributed sensors which measure three-features for identifying each of four chemicals. A Specialized Reinforcement Neural Network (RNN) learning approach is chosen for the chemicals classification problem. Hardware implementation of the RNN is presented for 2 /spl mu/m CMOS process, MOSIS chip. Design implementation and evaluation are also presented.
先进的微系统包括传感器、接口电路和模式识别集成在单片或混合模块中，用于民用、军事和空间应用。其中包括:汽车、医疗应用、环境工程和制造自动化。本文研究了基于人工神经网络(ANN)的asic，其目的是识别空气中的挥发性有机化合物，特别是醇类、醚类、酯类、卤代烃、nh3 / sub3 /、NO/ sub2 /和其他战争剂模拟物。ASIC输入连接到阵列分布式传感器的输出，该传感器测量用于识别四种化学物质中的每种化学物质的三个特征。采用一种特殊的强化神经网络(RNN)学习方法来解决化学品分类问题。在2 /spl μ m CMOS工艺、MOSIS芯片上，给出了RNN的硬件实现。并给出了设计实现和评价。
{"title":"Artificial neural network electronic nose for volatile organic compounds","authors":"H. Abdel-Aty-Zohdy","doi":"10.1109/GLSV.1998.665211","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665211","url":null,"abstract":"Advanced microsystems that include, sensors, interface-circuits, and pattern-recognition integrated monolithically or in a hybrid module are needed for civilian, military, and space applications. These include: automotive, medical applications, environmental engineering, and manufacturing automation. ASICs with Artificial Neural Networks (ANN) are considered in this paper, with the objective of recognizing air-borne volatile organic compounds, especially alcohols, ethers, esters, halocarbons, NH/sub 3/, NO/sub 2/, and other warfare agent simulants. The ASIC inputs are connected to the outputs from array-distributed sensors which measure three-features for identifying each of four chemicals. A Specialized Reinforcement Neural Network (RNN) learning approach is chosen for the chemicals classification problem. Hardware implementation of the RNN is presented for 2 /spl mu/m CMOS process, MOSIS chip. Design implementation and evaluation are also presented.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124967232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665224
F. Maloberti, Chen Gang
This paper discusses how to apply the approach used in the Chinese Abacus to implement digital arithmetic. Firstly, we examine the representations and the basic techniques used in the Chinese Abacus; then, we propose an MOS realization of the basic functions required; finally, we discuss a novel 12 bit full adder based on the Chinese Abacus method. Simulations of 0.5 /spl mu/m CMOS realizations showed that a parallel solution can run at 200 MHz while a pipeline realization can achieve 1 GHz of clock frequency. The complexity of the circuit is quite limited; thus, the use of the Chinese Abacus approach results in a competitive technique with respect to conventional methodologies.
{"title":"The Chinese Abacus method: can we use it for digital arithmetic?","authors":"F. Maloberti, Chen Gang","doi":"10.1109/GLSV.1998.665224","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665224","url":null,"abstract":"This paper discusses how to apply the approach used in the Chinese Abacus to implement digital arithmetic. Firstly, we examine the representations and the basic techniques used in the Chinese Abacus; then, we propose an MOS realization of the basic functions required; finally, we discuss a novel 12 bit full adder based on the Chinese Abacus method. Simulations of 0.5 /spl mu/m CMOS realizations showed that a parallel solution can run at 200 MHz while a pipeline realization can achieve 1 GHz of clock frequency. The complexity of the circuit is quite limited; thus, the use of the Chinese Abacus approach results in a competitive technique with respect to conventional methodologies.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125223309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665337
V. Krishna, N. Ranganathan
Effective power reduction can be achieved at higher levels of design abstraction. A number of such techniques have been proposed for power optimization in the literature. These techniques use RT level templates which characterize the area, delay and power of the design. The templates are based on some knowledge of the logic block such as the number of nodes, levels and their interconnections. Methods which model the power consumption of a logic block whose internal details are not known are desirable to explore trade-offs early on in the design cycle. Recently, lower bounds for switching activity at the gate level based on decision theory have been proposed by the authors. This has been extended to derive the average switching activity of a module based solely on its functionality. The experimental results on ISCAS '85 benchmark circuits indicate that the approach gives reasonably accurate estimates at low computational cost. In this paper, we use the RT level estimates for pourer exploration at the behavioral level for various high level synthesis benchmarks. The experimental results show that appropriate design decisions can be taken at the high level to reduce the cost of redesigning which would be incurred if committed to a particular circuit structure.
{"title":"A methodology for high level power estimation and exploration","authors":"V. Krishna, N. Ranganathan","doi":"10.1109/GLSV.1998.665337","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665337","url":null,"abstract":"Effective power reduction can be achieved at higher levels of design abstraction. A number of such techniques have been proposed for power optimization in the literature. These techniques use RT level templates which characterize the area, delay and power of the design. The templates are based on some knowledge of the logic block such as the number of nodes, levels and their interconnections. Methods which model the power consumption of a logic block whose internal details are not known are desirable to explore trade-offs early on in the design cycle. Recently, lower bounds for switching activity at the gate level based on decision theory have been proposed by the authors. This has been extended to derive the average switching activity of a module based solely on its functionality. The experimental results on ISCAS '85 benchmark circuits indicate that the approach gives reasonably accurate estimates at low computational cost. In this paper, we use the RT level estimates for pourer exploration at the behavioral level for various high level synthesis benchmarks. The experimental results show that appropriate design decisions can be taken at the high level to reduce the cost of redesigning which would be incurred if committed to a particular circuit structure.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127153473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665227
J. Stine, M. Schulte
Interval arithmetic provides an efficient method for monitoring and controlling errors in numerical calculations. However, existing software packages for interval arithmetic are often too slow for numerically intensive computations. This paper presents the design of a multiplier that performs either interval or floating point multiplication. This multiplier requires only slightly more area and delay than a conventional floating point multiplier, and is one to two orders of magnitude faster than software implementations of interval multiplication.
{"title":"A combined interval and floating point multiplier","authors":"J. Stine, M. Schulte","doi":"10.1109/GLSV.1998.665227","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665227","url":null,"abstract":"Interval arithmetic provides an efficient method for monitoring and controlling errors in numerical calculations. However, existing software packages for interval arithmetic are often too slow for numerically intensive computations. This paper presents the design of a multiplier that performs either interval or floating point multiplication. This multiplier requires only slightly more area and delay than a conventional floating point multiplier, and is one to two orders of magnitude faster than software implementations of interval multiplication.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129210155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665191
L. Benini, G. Micheli, A. Macii, E. Macii, M. Poncino
With the increased clock frequency of modern, high-performance processors (over 500 MHz, in some cases), limiting the power dissipation has become the most stringent design target. It is thus mandatory for processor engineers to resort to a large variety of optimization techniques to reduce the power requirements in the hot zones of the chip. In this paper, we focus on the power dissipated By the instruction fetch and decode logic, a portion of the processor architecture where a lot of capacitance switching normally takes place. We propose a methodology for determining an encoding of the instruction set that guarantees the minimization of the number of bit transitions occurring inside the registers of the pipeline stages involved in instruction fetching and decoding. The assignment of the binary patterns to the op-codes is driven by the statistics concerning instruction adjacency collected through instruction-level simulation of typical software applications; therefore, the technique is best exploited when applied to encode the instruction set of core processors and microcontrollers, since components of these types ore commonly used to execute fixed portions of machine code within embedded systems. We illustrate the effectiveness of the methodology through the experimental data we have obtained on an existing microprocessor.
{"title":"Reducing power consumption of dedicated processors through instruction set encoding","authors":"L. Benini, G. Micheli, A. Macii, E. Macii, M. Poncino","doi":"10.1109/GLSV.1998.665191","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665191","url":null,"abstract":"With the increased clock frequency of modern, high-performance processors (over 500 MHz, in some cases), limiting the power dissipation has become the most stringent design target. It is thus mandatory for processor engineers to resort to a large variety of optimization techniques to reduce the power requirements in the hot zones of the chip. In this paper, we focus on the power dissipated By the instruction fetch and decode logic, a portion of the processor architecture where a lot of capacitance switching normally takes place. We propose a methodology for determining an encoding of the instruction set that guarantees the minimization of the number of bit transitions occurring inside the registers of the pipeline stages involved in instruction fetching and decoding. The assignment of the binary patterns to the op-codes is driven by the statistics concerning instruction adjacency collected through instruction-level simulation of typical software applications; therefore, the technique is best exploited when applied to encode the instruction set of core processors and microcontrollers, since components of these types ore commonly used to execute fixed portions of machine code within embedded systems. We illustrate the effectiveness of the methodology through the experimental data we have obtained on an existing microprocessor.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122602622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665266
H. Elwan, M. Ismail
This paper describes a new technique for realizing CMOS digitally controlled, dB-linear variable gain amplifier (VGA) circuit. The circuit is developed taking into account system level issues for a direct conversion receiver. Besides being effective and simple to use from a system point of view, the developed VGA offers precise gain control, high linearity and low power consumption. The circuit can operate in a current domain or a voltage domain mode with single ended or fully differential signal handling capability. The proposed VGA circuit is implemented using a novel class AB operational transconductance amplifier and current division networks. Simulation results are included.
{"title":"Low voltage low power CMOS AGC circuit for wireless communication","authors":"H. Elwan, M. Ismail","doi":"10.1109/GLSV.1998.665266","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665266","url":null,"abstract":"This paper describes a new technique for realizing CMOS digitally controlled, dB-linear variable gain amplifier (VGA) circuit. The circuit is developed taking into account system level issues for a direct conversion receiver. Besides being effective and simple to use from a system point of view, the developed VGA offers precise gain control, high linearity and low power consumption. The circuit can operate in a current domain or a voltage domain mode with single ended or fully differential signal handling capability. The proposed VGA circuit is implemented using a novel class AB operational transconductance amplifier and current division networks. Simulation results are included.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"203 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123043071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665285
A. D. Johnson
Local Optimality paradigm is applicable to all combinatorial optimization problems. Its direct field of application are the constructive solution algorithm; its main advantage is the low computational cost for multiple high quality initial solutions for iterative improvement algorithms. The application of the paradigm to the VLSI channel routing has necessitated the creation of new knowledge represented by the theory of locally optimal breaking (LOB) of directed circuits (DC) in the vertical constraint graph. Existing theory has supported deterministic polynomial time algorithms for LOB of two classes of directed circuits, the classes of vertex disjoint DCs, and of couples of connected DCs. The new LOB theory supports algorithms for more complex classes of any number of DCs sharing a single vertex and of a uniform lattices of DCs. It is significant that the new theory relies on the theory for couples of connected DCs for breaking more complex structures of connected DCs.
{"title":"Local optimality theory in VLSI channel routing: composite cyclic vertical constraints","authors":"A. D. Johnson","doi":"10.1109/GLSV.1998.665285","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665285","url":null,"abstract":"Local Optimality paradigm is applicable to all combinatorial optimization problems. Its direct field of application are the constructive solution algorithm; its main advantage is the low computational cost for multiple high quality initial solutions for iterative improvement algorithms. The application of the paradigm to the VLSI channel routing has necessitated the creation of new knowledge represented by the theory of locally optimal breaking (LOB) of directed circuits (DC) in the vertical constraint graph. Existing theory has supported deterministic polynomial time algorithms for LOB of two classes of directed circuits, the classes of vertex disjoint DCs, and of couples of connected DCs. The new LOB theory supports algorithms for more complex classes of any number of DCs sharing a single vertex and of a uniform lattices of DCs. It is significant that the new theory relies on the theory for couples of connected DCs for breaking more complex structures of connected DCs.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115655233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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