Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665319
Jianping Lu, S. Tahar
In this paper we present several practical methods for formally verifying an Asynchronous Transfer Mode (ATM) network switching fabric using the Verification Interacting with Synthesis (VIS) tool. We produced Verilog RTL behavioral and netlist structural descriptions of the switch fabric at different levels of hierarchy and established several abstracted models of the fabric. Using various techniques presented in the paper, we provided a number of relevant liveness and safety properties expressible in CTL, and accomplished their verification in reasonable CPU time. Moreover, we performed equivalence checking between the structural and behavioral descriptions of each submodule of the implementation hierarchy.
{"title":"Practical approaches to the automatic verification of an ATM switch fabric using VIS","authors":"Jianping Lu, S. Tahar","doi":"10.1109/GLSV.1998.665319","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665319","url":null,"abstract":"In this paper we present several practical methods for formally verifying an Asynchronous Transfer Mode (ATM) network switching fabric using the Verification Interacting with Synthesis (VIS) tool. We produced Verilog RTL behavioral and netlist structural descriptions of the switch fabric at different levels of hierarchy and established several abstracted models of the fabric. Using various techniques presented in the paper, we provided a number of relevant liveness and safety properties expressible in CTL, and accomplished their verification in reasonable CPU time. Moreover, we performed equivalence checking between the structural and behavioral descriptions of each submodule of the implementation hierarchy.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126239498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665311
O. Mohamed, E. Cerny, Xiaoyu Song
Multiway Decision Graphs (MDGs) have been recently proposed as an efficient verification tool for RTL designs based on an efficient representation mechanism. In MDG, a data value is represented by a single variable of abstract sort, and a data operation is represented by an uninterpreted function symbol. In this work we investigate the non-termination problem of MDG-based verification. We present a novel approach to dealing with the problem based on retiming and circuit transformations that preserve the behaviour of the circuit. We demonstrate the effectiveness of our method on the example of the Island Tunnel Controller (ITC).
{"title":"MDG-based verification by retiming and combinational transformations","authors":"O. Mohamed, E. Cerny, Xiaoyu Song","doi":"10.1109/GLSV.1998.665311","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665311","url":null,"abstract":"Multiway Decision Graphs (MDGs) have been recently proposed as an efficient verification tool for RTL designs based on an efficient representation mechanism. In MDG, a data value is represented by a single variable of abstract sort, and a data operation is represented by an uninterpreted function symbol. In this work we investigate the non-termination problem of MDG-based verification. We present a novel approach to dealing with the problem based on retiming and circuit transformations that preserve the behaviour of the circuit. We demonstrate the effectiveness of our method on the example of the Island Tunnel Controller (ITC).","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127447785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665223
A. Skavantzos
The Residue Number System (RNS) is an integer system appropriate far implementing fast digital signal processors since it can support parallel, carry-free, highspeed arithmetic. In this paper a new RNS system and an efficient implementation of its residue-to-weighted converter are presented. The new RNS is a balanced 5-moduli system appropriate for large dynamic ranges. The new residue-to-binary converter is very fast and hardware-efficient and is based on a 1's complement multioperand adder adding operands of size only 80% of the size of the system's dynamic range.
{"title":"An efficient residue to weighted converter for a new residue number system","authors":"A. Skavantzos","doi":"10.1109/GLSV.1998.665223","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665223","url":null,"abstract":"The Residue Number System (RNS) is an integer system appropriate far implementing fast digital signal processors since it can support parallel, carry-free, highspeed arithmetic. In this paper a new RNS system and an efficient implementation of its residue-to-weighted converter are presented. The new RNS is a balanced 5-moduli system appropriate for large dynamic ranges. The new residue-to-binary converter is very fast and hardware-efficient and is based on a 1's complement multioperand adder adding operands of size only 80% of the size of the system's dynamic range.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114034904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665326
Ahmad S. Al-Mulhem, Alaaeldin A. M. Amin, H. Youssef
A new technology mapper (SELF-Map) for Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) is described. SELF-Map is based on the Stochastic Evolution (SE) algorithm. The state space model of the problem is defined and suitable cost function which allows optimization for area, delay, or area-delay combinations is proposed. Experimental results show that SELF-Map has an overall better performance compared to other algorithms reported in the literature.
{"title":"Stochastic evolution algorithm for technology mapping","authors":"Ahmad S. Al-Mulhem, Alaaeldin A. M. Amin, H. Youssef","doi":"10.1109/GLSV.1998.665326","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665326","url":null,"abstract":"A new technology mapper (SELF-Map) for Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs) is described. SELF-Map is based on the Stochastic Evolution (SE) algorithm. The state space model of the problem is defined and suitable cost function which allows optimization for area, delay, or area-delay combinations is proposed. Experimental results show that SELF-Map has an overall better performance compared to other algorithms reported in the literature.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"48 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129915768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665314
A. Chandra, Li-C. Wang, M. Abadir
Recently, formal verification has become more a part of the VLSI design methodology. Formally verifying a design guarantees 100% coverage and negates the need to do simulation. Theoretically, 100% coverage is very appealing and formal verification looks to be the panacea to solve the coverage problem. However, there are many practical considerations in deploying formal verification in real design environments. These considerations if not evaluated can lead to ineffective and even erroneous formal verification methodologies. In this paper we show how to make formal verification a successful part of a design methodology by paying attention to practical considerations and knowing the limitations of formal verification. We show the errors that can result by making over generalized assumptions and how they can be avoided. We do this in the context of the design of PowerPC microprocessors. We limit ourselves to a formal verification technique commonly used in our design methodology-boolean equivalence checking.
{"title":"Practical considerations in formal equivalence checking of PowerPC microprocessors","authors":"A. Chandra, Li-C. Wang, M. Abadir","doi":"10.1109/GLSV.1998.665314","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665314","url":null,"abstract":"Recently, formal verification has become more a part of the VLSI design methodology. Formally verifying a design guarantees 100% coverage and negates the need to do simulation. Theoretically, 100% coverage is very appealing and formal verification looks to be the panacea to solve the coverage problem. However, there are many practical considerations in deploying formal verification in real design environments. These considerations if not evaluated can lead to ineffective and even erroneous formal verification methodologies. In this paper we show how to make formal verification a successful part of a design methodology by paying attention to practical considerations and knowing the limitations of formal verification. We show the errors that can result by making over generalized assumptions and how they can be avoided. We do this in the context of the design of PowerPC microprocessors. We limit ourselves to a formal verification technique commonly used in our design methodology-boolean equivalence checking.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134542378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665257
M. Alioto, G. Palumbo
Accurate and simple models of CML propagation delay are given. The approach used is new. The propagation delay is represented with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The most accurate model has a typical and worst case errors as low as 2% and 5%, respectively.
{"title":"Novel simple models of CML propagation delay","authors":"M. Alioto, G. Palumbo","doi":"10.1109/GLSV.1998.665257","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665257","url":null,"abstract":"Accurate and simple models of CML propagation delay are given. The approach used is new. The propagation delay is represented with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The most accurate model has a typical and worst case errors as low as 2% and 5%, respectively.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"582 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132948434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665229
I. Pomeranz, S. Reddy
We introduce a new concept for test sequence compaction referred to as recycling. Recycling is based on the observation that easy-to-detect faults tend to be detected several times by a deterministic test sequence, whereas hard-to-detect faults are detected once towards the end of the test sequence. Thus, the suffix of a test sequence detects a large number of faults, including hard-to-detect faults. The recycling operation keeps a suffix S/sub 1/ of a test sequence T/sub 1/ and discards the rest of the sequence. The suffix S/sub 1/ is then used as a prefix of a new test sequence T/sub 2/. In this process, S/sub 1/ is expected to detect the more difficult to detect faults as well as many of the easy-to-detect faults, resulting in a new sequence T/sub 2/ which is shorter than T/sub 1/. Recycling is enhanced by a scheme where several faults are targeted simultaneously to generate the shortest possible test sequence that detects all of them.
{"title":"Test compaction for synchronous sequential circuits by test sequence recycling","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/GLSV.1998.665229","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665229","url":null,"abstract":"We introduce a new concept for test sequence compaction referred to as recycling. Recycling is based on the observation that easy-to-detect faults tend to be detected several times by a deterministic test sequence, whereas hard-to-detect faults are detected once towards the end of the test sequence. Thus, the suffix of a test sequence detects a large number of faults, including hard-to-detect faults. The recycling operation keeps a suffix S/sub 1/ of a test sequence T/sub 1/ and discards the rest of the sequence. The suffix S/sub 1/ is then used as a prefix of a new test sequence T/sub 2/. In this process, S/sub 1/ is expected to detect the more difficult to detect faults as well as many of the easy-to-detect faults, resulting in a new sequence T/sub 2/ which is shorter than T/sub 1/. Recycling is enhanced by a scheme where several faults are targeted simultaneously to generate the shortest possible test sequence that detects all of them.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131456919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665209
G. Giustolisi, G. Palmisano, G. Palumbo, C. Strano
New and simple CMOS mixer powered with 1.5 V is presented. It works with a 200 MHz clock, and has a -7-dB IP/sub 3/. Moreover, it elaborates signals up to 150 mV with 1-dB compression point. The particular topology makes it useful for an integration in fully digital ICs.
提出了一种新的简单的1.5 V CMOS混频器。它使用200 MHz时钟，并具有-7 db IP/sub /。此外，它以1db压缩点阐述高达150mv的信号。这种特殊的拓扑结构对于全数字集成电路的集成非常有用。
{"title":"A novel 1.5-V CMOS mixer","authors":"G. Giustolisi, G. Palmisano, G. Palumbo, C. Strano","doi":"10.1109/GLSV.1998.665209","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665209","url":null,"abstract":"New and simple CMOS mixer powered with 1.5 V is presented. It works with a 200 MHz clock, and has a -7-dB IP/sub 3/. Moreover, it elaborates signals up to 150 mV with 1-dB compression point. The particular topology makes it useful for an integration in fully digital ICs.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121435466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665218
N. Wang, C. Shih, Duan Juat Wong-Ho, N. Ling
A video decoder with an efficient controller scheme and a sub-picture decoder for DVD application is presented in this paper. Most of the reported architecture for MPEG2 video decoding uses a 64 bit bus and a complex bus arbitration scheme. Our design uses synchronous DRAMs instead of standard EDO DRAMs and involves a novel controller scheme that allocates bus space for DRAM access efficiently. This efficient allocation allows us to reduce bus width from 64 bits to 32 bits, without significantly increasing embedded buffer sizes, and still meeting the requirements for MPEG2 MP/ML decoding. The bus arbitration algorithm is also simple allowing for a less complex controller design. Our main strategy is to impose a certain order in the DRAM access by the various processes instead of allowing any process to request for bus access arbitrarily. We also take advantage of the restricted GOP (group of picture) sequence in the DVD format to allow a longer decoding time for B frames. The sub-picture pixel data are run-length compressed bitmaps that are overlayed on top of the MPEG reconstruction video. The architecture for sub-picture decoding is simple and easy to implement.
{"title":"MPEG-2 video decoder for DVD","authors":"N. Wang, C. Shih, Duan Juat Wong-Ho, N. Ling","doi":"10.1109/GLSV.1998.665218","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665218","url":null,"abstract":"A video decoder with an efficient controller scheme and a sub-picture decoder for DVD application is presented in this paper. Most of the reported architecture for MPEG2 video decoding uses a 64 bit bus and a complex bus arbitration scheme. Our design uses synchronous DRAMs instead of standard EDO DRAMs and involves a novel controller scheme that allocates bus space for DRAM access efficiently. This efficient allocation allows us to reduce bus width from 64 bits to 32 bits, without significantly increasing embedded buffer sizes, and still meeting the requirements for MPEG2 MP/ML decoding. The bus arbitration algorithm is also simple allowing for a less complex controller design. Our main strategy is to impose a certain order in the DRAM access by the various processes instead of allowing any process to request for bus access arbitrarily. We also take advantage of the restricted GOP (group of picture) sequence in the DVD format to allow a longer decoding time for B frames. The sub-picture pixel data are run-length compressed bitmaps that are overlayed on top of the MPEG reconstruction video. The architecture for sub-picture decoding is simple and easy to implement.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122521387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-02-19DOI: 10.1109/GLSV.1998.665338
S. Gailhard, N. Julien, J. Diguet, E. Martin
High level synthesis (HLS) for low power VLSI design is a complex optimization problem due to the area/time/power interdependence. As few low power design tools are available, a new approach providing a modular low power synthesis method is proposed. Although based for the moment on a generic architectural synthesis tool Gaut, the use of different "commercial" tools is possible. The Gaut-w HLS tool is constituted of low power modules: high level power dissipation estimation, assignment, module selection (operators and supply voltage), optimization criteria and operators library. As illustration, power saving factors on DWT algorithms are presented.
{"title":"How to transform an architectural synthesis tool for low power VLSI designs","authors":"S. Gailhard, N. Julien, J. Diguet, E. Martin","doi":"10.1109/GLSV.1998.665338","DOIUrl":"https://doi.org/10.1109/GLSV.1998.665338","url":null,"abstract":"High level synthesis (HLS) for low power VLSI design is a complex optimization problem due to the area/time/power interdependence. As few low power design tools are available, a new approach providing a modular low power synthesis method is proposed. Although based for the moment on a generic architectural synthesis tool Gaut, the use of different \"commercial\" tools is possible. The Gaut-w HLS tool is constituted of low power modules: high level power dissipation estimation, assignment, module selection (operators and supply voltage), optimization criteria and operators library. As illustration, power saving factors on DWT algorithms are presented.","PeriodicalId":225107,"journal":{"name":"Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-02-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131587990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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