Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202380
R.E. Eggen, C. Kurak
The problem of finding the occurrences of a pattern in a body of text is discussed. Several algorithms exist to solve this problem. The authors provide an overview of the Boyer-Moore algorithm, including its performance characteristics. They explain the implementation of the Kurak algorithm and its performance characteristics and compare the two algorithms. The analysis shows the Kurak algorithm to be superior when counting comparisons and when timing the search. The Kurak algorithm requires preprocessing of the text and thus, for the initial search, more time is required than for the Boyer-Moore algorithm. However, after the text has been processed the Kurak algorithm always provides superior performance.<>
{"title":"Pattern matching in fewer comparisons","authors":"R.E. Eggen, C. Kurak","doi":"10.1109/SECON.1992.202380","DOIUrl":"https://doi.org/10.1109/SECON.1992.202380","url":null,"abstract":"The problem of finding the occurrences of a pattern in a body of text is discussed. Several algorithms exist to solve this problem. The authors provide an overview of the Boyer-Moore algorithm, including its performance characteristics. They explain the implementation of the Kurak algorithm and its performance characteristics and compare the two algorithms. The analysis shows the Kurak algorithm to be superior when counting comparisons and when timing the search. The Kurak algorithm requires preprocessing of the text and thus, for the initial search, more time is required than for the Boyer-Moore algorithm. However, after the text has been processed the Kurak algorithm always provides superior performance.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125191390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202359
W. Huang, A. Glisson, A. Kishk
The effect of dielectric loading on the electromagnetic radiation characteristics of thick monopole antennas is investigated. A surface integral equation formulation for a dielectric-loaded thick monopole antenna modeled as a body of revolution is presented. The surface integral equations were solved via the method of moments for the unknown surface current distributions. The numerical data were verified by comparison of the results for input impedance with data available in the literature and with measured data for different configurations. The effects of loading on the input impedance, bandwidth, and beamwidth are considered for antennas mounted on both infinite and finite ground planes. Loads of various shapes and dielectric constants are investigated. Numerical results are presented for various conical and wire monopoles loaded with dielectrics which may partially or completely cover the conducting surface of the antenna.<>
{"title":"Electromagnetic characteristics of a thick monopole antenna with dielectric loading","authors":"W. Huang, A. Glisson, A. Kishk","doi":"10.1109/SECON.1992.202359","DOIUrl":"https://doi.org/10.1109/SECON.1992.202359","url":null,"abstract":"The effect of dielectric loading on the electromagnetic radiation characteristics of thick monopole antennas is investigated. A surface integral equation formulation for a dielectric-loaded thick monopole antenna modeled as a body of revolution is presented. The surface integral equations were solved via the method of moments for the unknown surface current distributions. The numerical data were verified by comparison of the results for input impedance with data available in the literature and with measured data for different configurations. The effects of loading on the input impedance, bandwidth, and beamwidth are considered for antennas mounted on both infinite and finite ground planes. Loads of various shapes and dielectric constants are investigated. Numerical results are presented for various conical and wire monopoles loaded with dielectrics which may partially or completely cover the conducting surface of the antenna.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121772142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202436
G. F. Smith
Some of the problems associated with the design of computer-based systems are discussed. Engineering of computer-based systems requires the designer to address two types of issues. First, there are the technical issues concerning the definition of the requirements, their partitioning, and the physical design of the system. In technical issues of system design, perhaps the most important issue to be addressed is the control of complexity. The second type of issue relates to the social environment within which the system has to operate, and within which it must be designed. Some practical guidelines are given to aid in overcoming the problems.<>
{"title":"Engineering computer-based systems","authors":"G. F. Smith","doi":"10.1109/SECON.1992.202436","DOIUrl":"https://doi.org/10.1109/SECON.1992.202436","url":null,"abstract":"Some of the problems associated with the design of computer-based systems are discussed. Engineering of computer-based systems requires the designer to address two types of issues. First, there are the technical issues concerning the definition of the requirements, their partitioning, and the physical design of the system. In technical issues of system design, perhaps the most important issue to be addressed is the control of complexity. The second type of issue relates to the social environment within which the system has to operate, and within which it must be designed. Some practical guidelines are given to aid in overcoming the problems.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131563486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202326
I. Paramanick
Presents an inherently parallel heuristic solution methodology called parallel dynamic interaction (PDI) and report its application to the flow-shop scheduling problem. Results indicate that, across the 40 examples studied, PDI solutions were on an average of within 2.5% of optimal. Additionally, the time taken for PDI to arrive at such high-quality solutions was negligible compared to that taken by conventional search techniques.<>
{"title":"Application of an inherently parallel heuristic methodology to flow-shop scheduling","authors":"I. Paramanick","doi":"10.1109/SECON.1992.202326","DOIUrl":"https://doi.org/10.1109/SECON.1992.202326","url":null,"abstract":"Presents an inherently parallel heuristic solution methodology called parallel dynamic interaction (PDI) and report its application to the flow-shop scheduling problem. Results indicate that, across the 40 examples studied, PDI solutions were on an average of within 2.5% of optimal. Additionally, the time taken for PDI to arrive at such high-quality solutions was negligible compared to that taken by conventional search techniques.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125490097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202250
K.-K. Lee, R. G. Deshmukh
The authors present an architecture for an 8-b*8-b real-time parallel array processor that can be used for high-speed digital signal processing applications. The processor generates 18-b outputs from a stream of 8-b input data and a set of 8-b predetermined coefficients. The processor has been designed in 1.5- mu m CMOS technology, analyzed for its timing, and functionally simulated by a hardware description language and a schematic simulator. The processor includes a pipelined array of multiplier-accumulators which provides parallel operation to the processor. The processor does not use parallel operation for an input rate lower than 28.5 Msamples/s, but the degree of parallelism was increased up to three for an input rate higher than 57.0 Msamples/s. This increase of the degree of parallelism resulted in a maximum throughput of 60.2 Msamples/s.<>
提出了一种可用于高速数字信号处理的8b * 8b实时并行阵列处理器体系结构。处理器从8b输入数据流和一组8b预定系数中产生18b输出。采用1.5 μ m CMOS工艺设计了该处理器，对其时序进行了分析，并用硬件描述语言和原理图模拟器进行了功能仿真。处理器包括向处理器提供并行操作的乘数-累加器的流水线阵列。当输入速率低于28.5 Msamples/s时，处理器不使用并行操作，但当输入速率高于57.0 Msamples/s时，并行度增加到3。这种并行度的增加导致最大吞吐量为60.2 Msamples/s。
{"title":"A high-speed 8*8-bit CMOS parallel array processor","authors":"K.-K. Lee, R. G. Deshmukh","doi":"10.1109/SECON.1992.202250","DOIUrl":"https://doi.org/10.1109/SECON.1992.202250","url":null,"abstract":"The authors present an architecture for an 8-b*8-b real-time parallel array processor that can be used for high-speed digital signal processing applications. The processor generates 18-b outputs from a stream of 8-b input data and a set of 8-b predetermined coefficients. The processor has been designed in 1.5- mu m CMOS technology, analyzed for its timing, and functionally simulated by a hardware description language and a schematic simulator. The processor includes a pipelined array of multiplier-accumulators which provides parallel operation to the processor. The processor does not use parallel operation for an input rate lower than 28.5 Msamples/s, but the degree of parallelism was increased up to three for an input rate higher than 57.0 Msamples/s. This increase of the degree of parallelism resulted in a maximum throughput of 60.2 Msamples/s.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130610032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202253
A. Barbir, J. Aravena
A parallel structure that can implement a matrix-matrix and a triple-matrix filtering algorithm efficiently is introduced. The architecture is a specialized form of a class of multiple single-instruction multiple-data machines (MSIMDs). It consists of systolic nodes of fixed dimension connected via a system network similar to the mesh interconnection network. The nodes have their own local memory and can access a common global memory. Communication among the nodes is performed by message passing. The structure is called the m/sup 2/-array (MSA). A technique is developed that analyzes the evolution of partial results in the MSA. The approach enables the designer to use the compute time as an added degree of freedom. This results in generating a family of low-complexity high-concurrence algorithms in the structure. This class of algorithms offer an attractive alternative for increasing the response time of the dedicated architecture.<>
{"title":"An efficient parallel structure for evaluating the triple matrix product algorithm","authors":"A. Barbir, J. Aravena","doi":"10.1109/SECON.1992.202253","DOIUrl":"https://doi.org/10.1109/SECON.1992.202253","url":null,"abstract":"A parallel structure that can implement a matrix-matrix and a triple-matrix filtering algorithm efficiently is introduced. The architecture is a specialized form of a class of multiple single-instruction multiple-data machines (MSIMDs). It consists of systolic nodes of fixed dimension connected via a system network similar to the mesh interconnection network. The nodes have their own local memory and can access a common global memory. Communication among the nodes is performed by message passing. The structure is called the m/sup 2/-array (MSA). A technique is developed that analyzes the evolution of partial results in the MSA. The approach enables the designer to use the compute time as an added degree of freedom. This results in generating a family of low-complexity high-concurrence algorithms in the structure. This class of algorithms offer an attractive alternative for increasing the response time of the dedicated architecture.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"28 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120932053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202288
A. Newman, D. G. Meyer
The observability of the nonlinear system equations describing the hot isostatic pressing (HIP'ing) dynamic system is investigated. HIP'ing is a process for consolidating porous materials to high density. The feasibility of estimating a particular state (grain size) of the HIP nonlinear system dynamics from measurements of the system's output (density) and input (applied temperature and applied pressure) is examined. The problem is treated as an observability issue in which it is desired to determine whether knowledge of the input/output data for the HIP'ing process can uniquely determine the states of the system. If the system is observable, then grain size can be estimated during the HIP'ing process without directly measuring it as an output of the system. The results indicate that the system is observable.<>
{"title":"Observability of HIP nonlinear dynamics","authors":"A. Newman, D. G. Meyer","doi":"10.1109/SECON.1992.202288","DOIUrl":"https://doi.org/10.1109/SECON.1992.202288","url":null,"abstract":"The observability of the nonlinear system equations describing the hot isostatic pressing (HIP'ing) dynamic system is investigated. HIP'ing is a process for consolidating porous materials to high density. The feasibility of estimating a particular state (grain size) of the HIP nonlinear system dynamics from measurements of the system's output (density) and input (applied temperature and applied pressure) is examined. The problem is treated as an observability issue in which it is desired to determine whether knowledge of the input/output data for the HIP'ing process can uniquely determine the states of the system. If the system is observable, then grain size can be estimated during the HIP'ing process without directly measuring it as an output of the system. The results indicate that the system is observable.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120959072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202307
A. Meghani, H. Latchman
A few reasons for the continued popularity enjoyed by H/sub infinity / theory in the control community are discussed. The mixed sensitivity H/sub infinity / robust control design problem based upon the Glover-Doyle 2-Riccati state-space approach (Doyle, Glover, Khargonekar and Francis, 1989) is considered. Particular emphasis is placed on the choice of suitable weighting functions, design parameters selected to reflect the relative importance of different design goals, upon which often hinges the successful computation of a satisfactory H/sub infinity / optimal controller. The Glover-Doyle algorithm was used to design a H/sub infinity / robust controller for a single-input-single-output system.<>
讨论了H/次无穷/理论在控制界持续流行的几个原因。考虑了基于Glover-Doyle 2-Riccati状态空间方法(Doyle, Glover, Khargonekar and Francis, 1989)的混合灵敏度H/次∞/鲁棒控制设计问题。特别强调的是选择合适的加权函数，设计参数的选择以反映不同设计目标的相对重要性，这往往取决于一个令人满意的H/次∞/最优控制器的成功计算。采用Glover-Doyle算法设计了单输入-单输出系统的H/sub∞/鲁棒控制器。
{"title":"H/sub infinity / vs. classical methods in the design of feedback control systems","authors":"A. Meghani, H. Latchman","doi":"10.1109/SECON.1992.202307","DOIUrl":"https://doi.org/10.1109/SECON.1992.202307","url":null,"abstract":"A few reasons for the continued popularity enjoyed by H/sub infinity / theory in the control community are discussed. The mixed sensitivity H/sub infinity / robust control design problem based upon the Glover-Doyle 2-Riccati state-space approach (Doyle, Glover, Khargonekar and Francis, 1989) is considered. Particular emphasis is placed on the choice of suitable weighting functions, design parameters selected to reflect the relative importance of different design goals, upon which often hinges the successful computation of a satisfactory H/sub infinity / optimal controller. The Glover-Doyle algorithm was used to design a H/sub infinity / robust controller for a single-input-single-output system.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131182934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202368
H. Fan, D.B. Miller
Steep-front, high current tests have been performed on 10 kV and 15 kV MOV (metal oxide varistor) and gapped SiC (silicon carbide) distribution arresters. Arrester voltage responses to steep-front, nearly rectangular current pulses exhibited a large voltage overshoot or initial spike. A considerable part of this overshoot voltage was the induced voltage in the voltage divider due to time-changing magnetic field generated by the rapidly rising arrester current. The overshoot voltage was estimated by replacing the test arrester with a similarly sized aluminum tube. Noises have been filtered out of the voltage and current waveforms by software filtering to determine the maximum rate of rise of the arrester current. The arrester peak voltages and the peak responses of the arrester materials are related linearly to the maximum rate of rise of the arrester currents.<>
{"title":"Measurement techniques to reveal arrester MOV response during steep-front impulsing","authors":"H. Fan, D.B. Miller","doi":"10.1109/SECON.1992.202368","DOIUrl":"https://doi.org/10.1109/SECON.1992.202368","url":null,"abstract":"Steep-front, high current tests have been performed on 10 kV and 15 kV MOV (metal oxide varistor) and gapped SiC (silicon carbide) distribution arresters. Arrester voltage responses to steep-front, nearly rectangular current pulses exhibited a large voltage overshoot or initial spike. A considerable part of this overshoot voltage was the induced voltage in the voltage divider due to time-changing magnetic field generated by the rapidly rising arrester current. The overshoot voltage was estimated by replacing the test arrester with a similarly sized aluminum tube. Noises have been filtered out of the voltage and current waveforms by software filtering to determine the maximum rate of rise of the arrester current. The arrester peak voltages and the peak responses of the arrester materials are related linearly to the maximum rate of rise of the arrester currents.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130936859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-04-12DOI: 10.1109/SECON.1992.202276
K. Krishnakumar
The author presents a generalized neural network structure and the associated backpropagation learning algorithm. This structure is an extension of a neural net structure presented by P.J. Werbos (1988, 1990). Generalization is aimed at ease of implementation and flexibility in structure selection. It is shown how certain network structures can be accommodated using this general structural form. Networks that are investigated include feedforward, recurrent, and memory networks.<>
{"title":"Backpropagation algorithm for a generalized neural network structure","authors":"K. Krishnakumar","doi":"10.1109/SECON.1992.202276","DOIUrl":"https://doi.org/10.1109/SECON.1992.202276","url":null,"abstract":"The author presents a generalized neural network structure and the associated backpropagation learning algorithm. This structure is an extension of a neural net structure presented by P.J. Werbos (1988, 1990). Generalization is aimed at ease of implementation and flexibility in structure selection. It is shown how certain network structures can be accommodated using this general structural form. Networks that are investigated include feedforward, recurrent, and memory networks.<<ETX>>","PeriodicalId":230446,"journal":{"name":"Proceedings IEEE Southeastcon '92","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134278929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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