Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111088
Y. Nakase, T. Ikeda, K. Mashiko, S. Kayano
A reduced word line voltage swing circuit is proposed in order to achieve high-speed ECL (emitter coupled logic) RAMs. This makes the word line voltage swing small without any sacrifice of the write operation, and allows 25% faster read operation to be obtained. In the circuit, large ISR and small reverse mode current gain are required for the fast write operation
{"title":"A 2 ns 16 K ECL RAM with reduced word line voltage swing","authors":"Y. Nakase, T. Ikeda, K. Mashiko, S. Kayano","doi":"10.1109/VLSIC.1990.111088","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111088","url":null,"abstract":"A reduced word line voltage swing circuit is proposed in order to achieve high-speed ECL (emitter coupled logic) RAMs. This makes the word line voltage swing small without any sacrifice of the write operation, and allows 25% faster read operation to be obtained. In the circuit, large ISR and small reverse mode current gain are required for the fast write operation","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132673735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111092
N. Kumazawa, N. Fukushima, N. Ono, N. Sakamoto
An 8-bit digital-to-analog converter with 30-pVs low glitch energy, 2-Vp-p wide-range output from GND, and a 150-MHz sampling rate is described. This device has been achieved on the basis of a new current cell and a biased switch using a 1.4-μm CMOS process. Experimental results for the device are reported
描述了一种8位数模转换器，具有30pv低故障能量，2 vp -p从地的宽范围输出，以及150 mhz的采样率。该器件是在使用1.4 μ m CMOS工艺的新电流单元和偏置开关的基础上实现的。报道了该装置的实验结果
{"title":"An 8 bit 150 MHz CMOS D/A converter with 2 Vp-p wide range output","authors":"N. Kumazawa, N. Fukushima, N. Ono, N. Sakamoto","doi":"10.1109/VLSIC.1990.111092","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111092","url":null,"abstract":"An 8-bit digital-to-analog converter with 30-pVs low glitch energy, 2-Vp-p wide-range output from GND, and a 150-MHz sampling rate is described. This device has been achieved on the basis of a new current cell and a biased switch using a 1.4-μm CMOS process. Experimental results for the device are reported","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128242480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111112
H. Nakai, K. Kanazawa, M. Asano, I. Sato, H. Iwahashi, K. Sakai, M. Yahata, S. Tanaka, N. Tozawa, M. Yatabe, S. Saito
A 36-ns, 1-Mb EPROM using a unique pseudodifferential sensing technique for high speed and a new noise immunity technique has been developed. In order to achieve both high speed and small die size, a newly developed pseudodifferential sensing technique with single-ended bit lines (one transistor/cell) and only two reference bit lines has been implemented, instead of a conventional fully differential sensing technique which has the disadvantage of large die size. A new data transfer circuit whose data transfer speed is controlled by an address transition detection pulse is utilized to obtain high noise immunity against power line noise caused by charging or discharging an output capacitance. Using 0.9-μm lithography, a cell size of 3.1 μm×2.9 μm has been achieved, resulting in a small die size of 6.67 mm×6.56 mm. The chip is fabricated by an n-well CMOS double poly-Si process with polycide technology and a single metal
采用独特的高速伪差分传感技术和新的抗噪技术，研制了一种36ns, 1mb的EPROM。为了实现高速度和小芯片尺寸，采用单端位线(一个晶体管/单元)和两个参考位线的伪差分传感技术取代了传统的全差分传感技术，该技术具有芯片尺寸大的缺点。利用地址转换检测脉冲控制数据传输速度的新型数据传输电路，对输出电容充放电产生的电力线噪声具有较高的抗扰性。采用0.9 μ m光刻技术，实现了3.1 μ m × 2.9 μ m的晶片尺寸，从而实现了6.67 mm × 6.56 mm的小晶片尺寸。该芯片采用n阱CMOS双多晶硅工艺，采用多晶技术和单一金属制造
{"title":"A 36 ns 1 Mbit CMOS EPROM with new data sensing technique","authors":"H. Nakai, K. Kanazawa, M. Asano, I. Sato, H. Iwahashi, K. Sakai, M. Yahata, S. Tanaka, N. Tozawa, M. Yatabe, S. Saito","doi":"10.1109/VLSIC.1990.111112","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111112","url":null,"abstract":"A 36-ns, 1-Mb EPROM using a unique pseudodifferential sensing technique for high speed and a new noise immunity technique has been developed. In order to achieve both high speed and small die size, a newly developed pseudodifferential sensing technique with single-ended bit lines (one transistor/cell) and only two reference bit lines has been implemented, instead of a conventional fully differential sensing technique which has the disadvantage of large die size. A new data transfer circuit whose data transfer speed is controlled by an address transition detection pulse is utilized to obtain high noise immunity against power line noise caused by charging or discharging an output capacitance. Using 0.9-μm lithography, a cell size of 3.1 μm×2.9 μm has been achieved, resulting in a small die size of 6.67 mm×6.56 mm. The chip is fabricated by an n-well CMOS double poly-Si process with polycide technology and a single metal","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124568425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111089
D. Wendell, J. Demaris, J. Chritz
A self-timed SRAM of 18-Kb density has been developed. It has several value-added features for specialty computer CPU applications. This part has an access time of 3.5 ns and a cycle time of less than access. All inputs are registered with respect to the clock positive edge, and read and write operations are internally self-timed. The output latch self-loads internally, thus insuring that data are valid for the entire cycle. The external timing facilities system usage. The part is formed using a self-timed synchronous architecture. An innovative circuit method called postcharge logic that allows a CMOS technology to achieve gate delays roughly equivalent to ECL (emitter coupled logic) gate delays was employed. Gate delays of 105 ps have been observed, compared to 145 ps for a regular CMOS inverter
{"title":"A 3.5 ns, 2 K×9 self timed SRAM","authors":"D. Wendell, J. Demaris, J. Chritz","doi":"10.1109/VLSIC.1990.111089","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111089","url":null,"abstract":"A self-timed SRAM of 18-Kb density has been developed. It has several value-added features for specialty computer CPU applications. This part has an access time of 3.5 ns and a cycle time of less than access. All inputs are registered with respect to the clock positive edge, and read and write operations are internally self-timed. The output latch self-loads internally, thus insuring that data are valid for the entire cycle. The external timing facilities system usage. The part is formed using a self-timed synchronous architecture. An innovative circuit method called postcharge logic that allows a CMOS technology to achieve gate delays roughly equivalent to ECL (emitter coupled logic) gate delays was employed. Gate delays of 105 ps have been observed, compared to 145 ps for a regular CMOS inverter","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122871359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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