Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111087
T. Douseki, Y. Ohmori, H. Yoshino, J. Yamada
A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept's effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time variance to within 4% for a 15% supply voltage variation
{"title":"Fast-access BiCMOS SRAM architecture with a VSS generator","authors":"T. Douseki, Y. Ohmori, H. Yoshino, J. Yamada","doi":"10.1109/VLSIC.1990.111087","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111087","url":null,"abstract":"A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept's effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time variance to within 4% for a 15% supply voltage variation","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124208206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111114
K. Shohji, T. Wada, K. Seki, T. Mutoh, T. Noda, Y. Kubota, T. Hagiwara, K. Shimohigashi
An on-chip automatic erase technique using an internal voltage generator has been developed and has proved to operate well in 1-Mb-flash EEPROM. This technology permits accurate control of erasure and guarantees the performance after erasure of the true single-transistor-per-cell type of flash EEPROM. Device implementation is described
{"title":"A novel automatic erase technique using an internal voltage generator for 1 Mbit flash EEPROM","authors":"K. Shohji, T. Wada, K. Seki, T. Mutoh, T. Noda, Y. Kubota, T. Hagiwara, K. Shimohigashi","doi":"10.1109/VLSIC.1990.111114","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111114","url":null,"abstract":"An on-chip automatic erase technique using an internal voltage generator has been developed and has proved to operate well in 1-Mb-flash EEPROM. This technology permits accurate control of erasure and guarantees the performance after erasure of the true single-transistor-per-cell type of flash EEPROM. Device implementation is described","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126231185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111104
K. Arimoto, M. Asakura, H. Hidaka, Y. Matsuda, K. Fujishima
The authors describe a unique intelligent memory based on a distributed CDRAM (cache DRAM) architecture, which consists of three hierarchical memory sections, DRAM, SRAM, and CAM, that constitute on-chip TAG. This architecture provides a high-performance intelligent main memory and a pin compatibility with high-speed address nonmultiplexed memories (DRAM, SRAM, and pseudo-SRAM). This RAM can be fabricated by the standard CMOS DRAM process with little area penalty. The intelligent CDRAM with an automatic write-back function can realize a short average read/write cycle time. The write-back operation without a complex controller minimizes the write cycle time drastically compared with write through
{"title":"A circuit design of intelligent CDRAM with automatic write back capability","authors":"K. Arimoto, M. Asakura, H. Hidaka, Y. Matsuda, K. Fujishima","doi":"10.1109/VLSIC.1990.111104","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111104","url":null,"abstract":"The authors describe a unique intelligent memory based on a distributed CDRAM (cache DRAM) architecture, which consists of three hierarchical memory sections, DRAM, SRAM, and CAM, that constitute on-chip TAG. This architecture provides a high-performance intelligent main memory and a pin compatibility with high-speed address nonmultiplexed memories (DRAM, SRAM, and pseudo-SRAM). This RAM can be fabricated by the standard CMOS DRAM process with little area penalty. The intelligent CDRAM with an automatic write-back function can realize a short average read/write cycle time. The write-back operation without a complex controller minimizes the write cycle time drastically compared with write through","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125661440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111127
J. Mori, M. Nagamatsu, M. Hirano, S. Tanaka, M. Noda, Y. Toyoshima, K. Hashimoto, H. Hayashida, K. Maeguchi
A 54-b×54-b multiplier fabricated in double metal 0.5-μm CMOS technology is described. A 10-ns multiplication time has been achieved by employing a 4-2 compressor, a carry select adder, and a carry lookahead adder. The 54-b×54-b full array is adopted to complete the multiplication within one latency. This multiplier is intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz. The multiplier has integrated 81600 transistors in an active area of 3.62 mm×3.45 mm
描述了一种采用双金属0.5 μ m CMOS技术制造的54倍54倍倍增器。通过采用4-2压缩器、进位选择加法器和进位前瞻加法器，实现了10-ns的乘法时间。采用54-b×54-b全阵列，在一个时延内完成乘法运算。该乘法器用于基于IEEE标准的双精度浮点数据处理，时钟范围为100mhz。该倍增器在3.62 mm * 3.45 mm的有源面积上集成了81600个晶体管
{"title":"A 10 ns 54×54-bit parallel structured full array multiplier with 0.5 μm CMOS technology","authors":"J. Mori, M. Nagamatsu, M. Hirano, S. Tanaka, M. Noda, Y. Toyoshima, K. Hashimoto, H. Hayashida, K. Maeguchi","doi":"10.1109/VLSIC.1990.111127","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111127","url":null,"abstract":"A 54-b×54-b multiplier fabricated in double metal 0.5-μm CMOS technology is described. A 10-ns multiplication time has been achieved by employing a 4-2 compressor, a carry select adder, and a carry lookahead adder. The 54-b×54-b full array is adopted to complete the multiplication within one latency. This multiplier is intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz. The multiplier has integrated 81600 transistors in an active area of 3.62 mm×3.45 mm","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130858526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111097
K. Sakaue, Y. Shobatake, M. Motoyama, Y. Kumaki, S. Takatsuka, S. Tanaka, H. Hara, K. Matsuda, S. Kitaoka, M. Noda, Y. Niitsu, M. Norishima, H. Momose, K. Maeguchi, S. Shimizu, T. Kodama
A two-input, two-output element switch for use in future ATM (asynchronous transfer mode) switching systems for buffered banyan networks with CASO (contents associated output) buffers has been realized in 0.8-μm BiCMOS technology. Three key features of the element switch architecture are CASO buffers to increase the throughput, SCDB (synchronization in clocked dual-port buffer) to make asynchronous cell transmission possible on the element switches with a simple structure, and CELL-BYPASS, which lowers the latency (the time of cell passage through the element switch). The element switch adopted an ECL (emitter coupled logic) interface to achieve high through rate. Using these techniques, a high-speed, low-latency, very-large-scale buffered self-routing switching network is easily constructed
一种用于未来ATM(异步传输模式)交换系统的双输入双输出元件开关已在0.8 μ m BiCMOS技术中实现，该开关用于具有CASO(内容相关输出)缓冲区的缓冲榕树网络。元件交换机架构的三个关键特征是CASO缓冲器(用于增加吞吐量)、SCDB(时钟双端口缓冲器中的同步)(用于在结构简单的元件交换机上实现异步单元传输)和cell - bypass(用于降低延迟(单元通过元件交换机的时间))。元件开关采用ECL(发射极耦合逻辑)接口，实现高通达率。利用这些技术，可以很容易地构建高速、低延迟、超大规模的缓冲自路由交换网络
{"title":"A 0.8 μm BiCMOS ATM switch on the 800 Mbps asynchronous buffered banyan network","authors":"K. Sakaue, Y. Shobatake, M. Motoyama, Y. Kumaki, S. Takatsuka, S. Tanaka, H. Hara, K. Matsuda, S. Kitaoka, M. Noda, Y. Niitsu, M. Norishima, H. Momose, K. Maeguchi, S. Shimizu, T. Kodama","doi":"10.1109/VLSIC.1990.111097","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111097","url":null,"abstract":"A two-input, two-output element switch for use in future ATM (asynchronous transfer mode) switching systems for buffered banyan networks with CASO (contents associated output) buffers has been realized in 0.8-μm BiCMOS technology. Three key features of the element switch architecture are CASO buffers to increase the throughput, SCDB (synchronization in clocked dual-port buffer) to make asynchronous cell transmission possible on the element switches with a simple structure, and CELL-BYPASS, which lowers the latency (the time of cell passage through the element switch). The element switch adopted an ECL (emitter coupled logic) interface to achieve high through rate. Using these techniques, a high-speed, low-latency, very-large-scale buffered self-routing switching network is easily constructed","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130633454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111095
S. Takagi, H. Nitta, M. Furihata, M. Fujii, M. Nagata, T. Yanagisawa
Proposes an implementation of a monolithic filter with a 100 MHz cutoff frequency and a 200 MHz transmission zero. The method is based on the modified leapfrog simulation and requires no floating capacitors. Integrators are realized by balanced-type NICs because the NICs have excellent high frequency characteristics. Results of computer simulation are also presented
{"title":"A synthesis of 100 MHz monolithic third-order lowpass filters with a transmission zero","authors":"S. Takagi, H. Nitta, M. Furihata, M. Fujii, M. Nagata, T. Yanagisawa","doi":"10.1109/VLSIC.1990.111095","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111095","url":null,"abstract":"Proposes an implementation of a monolithic filter with a 100 MHz cutoff frequency and a 200 MHz transmission zero. The method is based on the modified leapfrog simulation and requires no floating capacitors. Integrators are realized by balanced-type NICs because the NICs have excellent high frequency characteristics. Results of computer simulation are also presented","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130678547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111099
S. Kotani, A. Inoue, S. Hasuo
The design and technology for a high-speed Josephson macrocell array are described. A macrocell array including 7.6 k gates was fabricated using a 1.5-μm Nb Josephson process. The chip dimensions are 5×5 mm, and its power consumption is 23 mW. An average gate delay in full adder of 5.3 ps has been achieved using the macrocell
介绍了一种高速约瑟夫逊宏单元阵列的设计和技术。采用1.5 μ m Nb Josephson工艺制备了包含7.6 k栅极的macrocell阵列。芯片尺寸为5 × 5mm，功耗为23 mW。在全加法器中实现了5.3 ps的平均门延迟
{"title":"A 7.6 K-gate Josephson macrocell array","authors":"S. Kotani, A. Inoue, S. Hasuo","doi":"10.1109/VLSIC.1990.111099","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111099","url":null,"abstract":"The design and technology for a high-speed Josephson macrocell array are described. A macrocell array including 7.6 k gates was fabricated using a 1.5-μm Nb Josephson process. The chip dimensions are 5×5 mm, and its power consumption is 23 mW. An average gate delay in full adder of 5.3 ps has been achieved using the macrocell","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130965042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111078
B. Brandt, D. Wingard, B. Wooley
The authors describe a CMOS second-order Σ-Δ modulator that does not require error correction or component trimming to achieve virtually ideal 16-b performance at a conversion rate of 50 kHz. This modulator is a fully differential circuit that operates from a single 5-V power supply and does not require the use of precision sample-and-hold circuitry. With an oversampling ratio of 256 and a clock rate of 12.8 MHz, an experimental implementation of the modulator achieves a 98-dB dynamic range and 94-dB linearity. The nearly ideal 16-b performance of the modulator and its small area of 0.39 mm2 and power dissipation of only 13.8 mW make it suitable for use as a digital-audio quality analog interface within digital signal processing chips and systems
{"title":"A 12.8-MHz sigma-delta modulator with 16-bit performance","authors":"B. Brandt, D. Wingard, B. Wooley","doi":"10.1109/VLSIC.1990.111078","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111078","url":null,"abstract":"The authors describe a CMOS second-order Σ-Δ modulator that does not require error correction or component trimming to achieve virtually ideal 16-b performance at a conversion rate of 50 kHz. This modulator is a fully differential circuit that operates from a single 5-V power supply and does not require the use of precision sample-and-hold circuitry. With an oversampling ratio of 256 and a clock rate of 12.8 MHz, an experimental implementation of the modulator achieves a 98-dB dynamic range and 94-dB linearity. The nearly ideal 16-b performance of the modulator and its small area of 0.39 mm2 and power dissipation of only 13.8 mW make it suitable for use as a digital-audio quality analog interface within digital signal processing chips and systems","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134374136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111120
D.D. Lee, R. Katz
It is shown that, by using simple circuit techniques and a few modifications to cache organization, one can effectively eliminate the refreshing requirement of a DRAM. A selective invalidation scheme is employed. Selective invalidation can be implemented with a small (six transistors per subblock) circuit. The performances of the DRAM cache with selective invalidation and an equivalent SRAM cache are compared. The difference in performance is quite small even for large caches using selective invalidation. By replacing the SRAM cache with higher-density DRAM, the area efficiency and overall processor performance can be greatly improved. The miss ratio difference in large caches indicates that there are some cache entries active at intervals greater than the refresh period. This may depend on the referencing behavior of program or data
{"title":"Non-refreshing dynamic RAM for on-chip cache memories","authors":"D.D. Lee, R. Katz","doi":"10.1109/VLSIC.1990.111120","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111120","url":null,"abstract":"It is shown that, by using simple circuit techniques and a few modifications to cache organization, one can effectively eliminate the refreshing requirement of a DRAM. A selective invalidation scheme is employed. Selective invalidation can be implemented with a small (six transistors per subblock) circuit. The performances of the DRAM cache with selective invalidation and an equivalent SRAM cache are compared. The difference in performance is quite small even for large caches using selective invalidation. By replacing the SRAM cache with higher-density DRAM, the area efficiency and overall processor performance can be greatly improved. The miss ratio difference in large caches indicates that there are some cache entries active at intervals greater than the refresh period. This may depend on the referencing behavior of program or data","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128987718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111075
H. Hidaka, Y. Matsuda, K. Fujishima
New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyond
{"title":"A divided/shared bitline sensing scheme for 64 Mb DRAM core","authors":"H. Hidaka, Y. Matsuda, K. Fujishima","doi":"10.1109/VLSIC.1990.111075","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111075","url":null,"abstract":"New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyond","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114537838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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