Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111113
Y. Terada, T. Nakayama, K. Kobayashi, M. Hayashikoshi, S. Kobayashi, Y. Miyawaki, N. Ajika, T. Yoshihara
A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved
{"title":"High speed page mode sensing scheme for EPROMs and flash EEEPROMs using divided bit line architecture","authors":"Y. Terada, T. Nakayama, K. Kobayashi, M. Hayashikoshi, S. Kobayashi, Y. Miyawaki, N. Ajika, T. Yoshihara","doi":"10.1109/VLSIC.1990.111113","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111113","url":null,"abstract":"A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114708711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111119
I. Okabayashi, H. Kotani, H. Kadota
A new structure for a high-density 4-Mb CAM (content addressable memory) with sorting function (sort-CAM) is proposed. Retrieval or sorting operations are done in word-parallel/bit-serial manner at the device. This is different from previous CAMs where operations are done in word-parallel/bit-parallel or flash manner. The device organization, circuits for retrieval or sorting, and chip operations are explained. Estimated performance of the device and chip size are also discussed. The device has 64 K-word×64-b organization and a 3.1-MB/s sorting speed. In practical applications, such as RDB (relational database) systems, this speed is enough, but a number of chips should be connected if larger data volume is needed
{"title":"A proposed structure of a 4 Mbit content-addressable and sorting memory","authors":"I. Okabayashi, H. Kotani, H. Kadota","doi":"10.1109/VLSIC.1990.111119","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111119","url":null,"abstract":"A new structure for a high-density 4-Mb CAM (content addressable memory) with sorting function (sort-CAM) is proposed. Retrieval or sorting operations are done in word-parallel/bit-serial manner at the device. This is different from previous CAMs where operations are done in word-parallel/bit-parallel or flash manner. The device organization, circuits for retrieval or sorting, and chip operations are explained. Estimated performance of the device and chip size are also discussed. The device has 64 K-word×64-b organization and a 3.1-MB/s sorting speed. In practical applications, such as RDB (relational database) systems, this speed is enough, but a number of chips should be connected if larger data volume is needed","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127594247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111094
Y. Matsunaga, H. Yamashita, S. Ohsawa, N. Harada
A novel high-sensitivity on-chip amplifier for CCD (charge coupled device) image sensors is evaluated within a very small signal range of under 20 electrons, which is the photon counting region for highly sensitive imaging devices. Because the output noise of 0.084 mV RMS is smaller than the output voltage/electron of 0.22 mV/electron measured in the larger-signal region, the discrete voltage levels corresponding to numbers of signal electrons were directly observed in an oscilloscope in the small signal region. By this observation, it was confirmed that high responsivity is maintained in the very-small-signal region. Therefore, it is possible to realize a photon-counting solid-state image sensor and a highly sensitive megapixel-level HDTV (high-definition television) imager
{"title":"Ultra high sensitivity on-chip amplifier for VLSI CCD image sensor","authors":"Y. Matsunaga, H. Yamashita, S. Ohsawa, N. Harada","doi":"10.1109/VLSIC.1990.111094","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111094","url":null,"abstract":"A novel high-sensitivity on-chip amplifier for CCD (charge coupled device) image sensors is evaluated within a very small signal range of under 20 electrons, which is the photon counting region for highly sensitive imaging devices. Because the output noise of 0.084 mV RMS is smaller than the output voltage/electron of 0.22 mV/electron measured in the larger-signal region, the discrete voltage levels corresponding to numbers of signal electrons were directly observed in an oscilloscope in the small signal region. By this observation, it was confirmed that high responsivity is maintained in the very-small-signal region. Therefore, it is possible to realize a photon-counting solid-state image sensor and a highly sensitive megapixel-level HDTV (high-definition television) imager","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122741407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111118
T. Matsumura, K. Endo, J. Yamada
A pipelined, time-sharing access (PTA) technique that enables a two-port memory cell to operate as a four-port memory cell is proposed. The effectiveness of this technique has been demonstrated by fabricating a 64-kb four-port (read/write) memory with 60-MHz operation under a 3-V supply voltage
{"title":"Pipelined, time-sharing access technique for a highly integrated multi-port memory","authors":"T. Matsumura, K. Endo, J. Yamada","doi":"10.1109/VLSIC.1990.111118","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111118","url":null,"abstract":"A pipelined, time-sharing access (PTA) technique that enables a two-port memory cell to operate as a four-port memory cell is proposed. The effectiveness of this technique has been demonstrated by fabricating a 64-kb four-port (read/write) memory with 60-MHz operation under a 3-V supply voltage","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123793060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111084
B. Kertis, G. Costakis, J. Jensen, J. Zeiter, J. Rickard, M. Pusztai, T. Bowman
A 1-Mb ECL (emitter coupled logic) I/O SRAM which has been fabricated using 0.8-μm BiCMOS technology is described. The die is configurable to four different organizations (1 Mb×1, 1 Mb×1 with differential output, 512 K×2 with differential output, and 256 K×4) by way of bonding options. The device, with a die size of 240 mil×475 mil, has a typical access time of 6.8 ns and is 10 K or 100 K I/O compatible with a metal option
描述了一种采用0.8 μ m BiCMOS技术制造的1mb ECL(发射极耦合逻辑)I/O SRAM。通过键合选项，该模具可配置为四种不同的组织(1mb×1, 1mb×1带差分输出，512k×2带差分输出，256k×4)。该器件的芯片尺寸为240密耳(475密耳)，典型存取时间为6.8 ns，可与金属选项兼容10 K或100 K I/O
{"title":"A 6.8 ns 1 Mb ECL I/O BiCMOS configurable SRAM","authors":"B. Kertis, G. Costakis, J. Jensen, J. Zeiter, J. Rickard, M. Pusztai, T. Bowman","doi":"10.1109/VLSIC.1990.111084","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111084","url":null,"abstract":"A 1-Mb ECL (emitter coupled logic) I/O SRAM which has been fabricated using 0.8-μm BiCMOS technology is described. The die is configurable to four different organizations (1 Mb×1, 1 Mb×1 with differential output, 512 K×2 with differential output, and 256 K×4) by way of bonding options. The device, with a die size of 240 mil×475 mil, has a typical access time of 6.8 ns and is 10 K or 100 K I/O compatible with a metal option","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131872755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111130
K. Wise
The challenges facing the development of monolithic instrumentation systems are reviewed. Sensor technology is discussed, and examples of merging transducer and circuit processes are given. It is noted that, for many future systems, transducers, analog circuits, logic, and memory should probably be merged on a single chip, and system-level standards are needed to focus such efforts. It is concluded that microcomputer-based sensing nodes capable of functioning as smart peripherals and employing features such as self-testing, autocalibration, and PROM-based digital compensation should be realizable on a single chip within a decade
{"title":"VLSI circuit challenges for integrated sensing systems","authors":"K. Wise","doi":"10.1109/VLSIC.1990.111130","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111130","url":null,"abstract":"The challenges facing the development of monolithic instrumentation systems are reviewed. Sensor technology is discussed, and examples of merging transducer and circuit processes are given. It is noted that, for many future systems, transducers, analog circuits, logic, and memory should probably be merged on a single chip, and system-level standards are needed to focus such efforts. It is concluded that microcomputer-based sensing nodes capable of functioning as smart peripherals and employing features such as self-testing, autocalibration, and PROM-based digital compensation should be realizable on a single chip within a decade","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134025942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111074
T. Blalock, R. Jaeger
A novel two-transistor DRAM cell technology is introduced which uses a unique clamped bit line, unbalanced-gain sense amplifier. The 2T cell topology offers nondestructive readout of the cell state and high-speed operation. The speed of the sense amplifier is independent of bit-line capacitance, and the bit lines of the new topology are insensitive to noise voltage coupling. The memory exhibits access times of 12.4 ns at 298 K and 7 ns at 89 K. The design is well suited to quasi-static low-temperature memory operation and high-speed cache memory applications
{"title":"An experimental 2T cell RAM with 7 ns access time at low temperature","authors":"T. Blalock, R. Jaeger","doi":"10.1109/VLSIC.1990.111074","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111074","url":null,"abstract":"A novel two-transistor DRAM cell technology is introduced which uses a unique clamped bit line, unbalanced-gain sense amplifier. The 2T cell topology offers nondestructive readout of the cell state and high-speed operation. The speed of the sense amplifier is independent of bit-line capacitance, and the bit lines of the new topology are insensitive to noise voltage coupling. The memory exhibits access times of 12.4 ns at 298 K and 7 ns at 89 K. The design is well suited to quasi-static low-temperature memory operation and high-speed cache memory applications","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116352419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111110
M. Fujishima, K. Asada, T. Sugano
The authors present a general appraisal of voltage-dependent speed degradation for three kinds of BiCMOS logic circuits from the viewpoints of (1) essential delays without parasitic capacitances, (2) practical delays with parasitics, (3) full-swing (power to ground) mode operation, and (4) partial-swing operation. The essential delay times of the three circuits are analytically derived and effects of parasitic capacitances are discussed. The degradation of delay time is shown to depend significantly on whether the input signal swings fully or partially. For partial-swing operation, it has been found that an emitter follower circuit with bias diodes is effective. In general, full-swing operation can be achieved by inserting resistors
{"title":"Appraisal of BiCMOS from circuit voltage and delay time","authors":"M. Fujishima, K. Asada, T. Sugano","doi":"10.1109/VLSIC.1990.111110","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111110","url":null,"abstract":"The authors present a general appraisal of voltage-dependent speed degradation for three kinds of BiCMOS logic circuits from the viewpoints of (1) essential delays without parasitic capacitances, (2) practical delays with parasitics, (3) full-swing (power to ground) mode operation, and (4) partial-swing operation. The essential delay times of the three circuits are analytically derived and effects of parasitic capacitances are discussed. The degradation of delay time is shown to depend significantly on whether the input signal swings fully or partially. For partial-swing operation, it has been found that an emitter follower circuit with bias diodes is effective. In general, full-swing operation can be achieved by inserting resistors","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133301038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111077
I. Hayashi
Progress in OEIC (optoelectronic integrated-circuit) technologies is briefly reviewed, and the feasibility of optically integrated ULSI is examined. It is concluded that an overall delay time of 0.1-0.2 ns will be achievable for a bus line in ULSI using optical interconnections, which is more than one order of magnitude faster than the conventional metal wire bus line. Future prospects in optoelectronics are addressed
{"title":"Impacts of optoelectronics technology on ULSI","authors":"I. Hayashi","doi":"10.1109/VLSIC.1990.111077","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111077","url":null,"abstract":"Progress in OEIC (optoelectronic integrated-circuit) technologies is briefly reviewed, and the feasibility of optically integrated ULSI is examined. It is concluded that an overall delay time of 0.1-0.2 ns will be achievable for a bus line in ULSI using optical interconnections, which is more than one order of magnitude faster than the conventional metal wire bus line. Future prospects in optoelectronics are addressed","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116901957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111106
M. Marlett, B. Prickett, R. Lall, N. Chidambaram
An integrated simulation environment which accurately models the noise behavior of VLSI circuits in a package with reasonable simulation time has been developed. These models are generated by automatic tools developed for this purpose. When used in a methodical approach to noise analysis, the tools speed up the simulation process and make it possible to reliably predict the behavior of a VLSI circuit in a package before it is fabricated. Theoretical package-pin models have been correlated with scattering parameter measurements, SPICE simulations, electrical-parameter simulation, and bench measurements. Die parasitics are automatically extracted to produce a compact die model. Models for the package-pins, the die capacitance, the active circuits, and the output loads are combined to simulate the noise behavior of a circuit
{"title":"Environment and methodology for accurate noise simulation of VLSI circuits","authors":"M. Marlett, B. Prickett, R. Lall, N. Chidambaram","doi":"10.1109/VLSIC.1990.111106","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111106","url":null,"abstract":"An integrated simulation environment which accurately models the noise behavior of VLSI circuits in a package with reasonable simulation time has been developed. These models are generated by automatic tools developed for this purpose. When used in a methodical approach to noise analysis, the tools speed up the simulation process and make it possible to reliably predict the behavior of a VLSI circuit in a package before it is fabricated. Theoretical package-pin models have been correlated with scattering parameter measurements, SPICE simulations, electrical-parameter simulation, and bench measurements. Die parasitics are automatically extracted to produce a compact die model. Models for the package-pins, the die capacitance, the active circuits, and the output loads are combined to simulate the noise behavior of a circuit","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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