Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111072
T. Furuyama, N. Kushiyama, Y. Watanabe, T. Ohsawa, K. Muraoka, Y. Nagahama
A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e. a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAD access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family
{"title":"A high random-access-data-rate 4 Mb DRAM with pipeline operation","authors":"T. Furuyama, N. Kushiyama, Y. Watanabe, T. Ohsawa, K. Muraoka, Y. Nagahama","doi":"10.1109/VLSIC.1990.111072","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111072","url":null,"abstract":"A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e. a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAD access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116187605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111071
G. Wilson
The advancement of bipolar VLSI technology coupled with the lower complexity of RISC (reduced instruction set computer) architectures has made possible bipolar ECL (emitter coupled logic) implementations of single-chip instruction units with much higher clock rates. It is projected that future RISC generations will be implemented in BICMOS as well as ECL and CMOS. It is concluded that ECL-based technology should continue to produce the fastest chips, but the technology must evolve to provide even higher densities and far more on-chip memory to maintain its position
{"title":"Future high performance ECL microprocessors","authors":"G. Wilson","doi":"10.1109/VLSIC.1990.111071","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111071","url":null,"abstract":"The advancement of bipolar VLSI technology coupled with the lower complexity of RISC (reduced instruction set computer) architectures has made possible bipolar ECL (emitter coupled logic) implementations of single-chip instruction units with much higher clock rates. It is projected that future RISC generations will be implemented in BICMOS as well as ECL and CMOS. It is concluded that ECL-based technology should continue to produce the fastest chips, but the technology must evolve to provide even higher densities and far more on-chip memory to maintain its position","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124864088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111103
S. Murakami, T. Wada, M. Eino, M. Ukita, Y. Nishimura, K. Anami
The inverted dependence of the soft-error rate (SER) on the cycle time in static RAMs with high resistive load cells is described. The inverted dependence is observed in the SRAM with a PMOS bit-line load. At a cycle time of 100 ns, the SER is reduced by 1.5 orders of magnitude, compared with that of the SRAM with NMOS bit-line load. The mechanism is explained with reference to the time constant of the potential drop of the high storage node in the selected cell. It is concluded that the PMOS bit-line load is an effective method for improving the SER when the subthreshold current through the driver transistor is reduced. This technique shows potential for ULSI SRAMs beyond 4 Mb
{"title":"A new soft-error phenomenon in ULSI SRAMs-inverted dependence of soft-error rate on cycle time","authors":"S. Murakami, T. Wada, M. Eino, M. Ukita, Y. Nishimura, K. Anami","doi":"10.1109/VLSIC.1990.111103","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111103","url":null,"abstract":"The inverted dependence of the soft-error rate (SER) on the cycle time in static RAMs with high resistive load cells is described. The inverted dependence is observed in the SRAM with a PMOS bit-line load. At a cycle time of 100 ns, the SER is reduced by 1.5 orders of magnitude, compared with that of the SRAM with NMOS bit-line load. The mechanism is explained with reference to the time constant of the potential drop of the high storage node in the selected cell. It is concluded that the PMOS bit-line load is an effective method for improving the SER when the subthreshold current through the driver transistor is reduced. This technique shows potential for ULSI SRAMs beyond 4 Mb","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126462691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111126
F. Lu, H. Samueli
A bit-level pipelined 12-b×12-b two's complement multiplier with a 27-b accumulator has been designed and fabricated in a 1-μm CMOS technology. A novel quasi N-P domino logic structure has been adopted to increase the throughput, and special pipeline structures were used to reduce the latency significantly. The measured maximum clock rate is 140 MHz (i.e. 140 million multiply-accumulate operations per second), and the typical power-speed ratio is 11 mW/MHz. The chip complexity is 10000 transistors and the 68-pad chip area is 2.5 mm×3.7 mm
采用1 μ m CMOS技术，设计并制作了一种位级流水线式12b倍12b双补乘法器和27b累加器。采用了一种新颖的准N-P多米诺逻辑结构来提高吞吐量，并采用了特殊的管道结构来显著降低延迟。测量到的最大时钟速率为140 MHz(即每秒1.4亿次乘法累积操作)，典型的功率-速度比为11 mW/MHz。芯片的复杂性是10000个晶体管，68个衬垫的芯片面积是2.5 mm乘以3.7 mm
{"title":"A 140-MHz CMOS bit-level pipelined multiplier-accumulator using a new dynamic full-adder cell design","authors":"F. Lu, H. Samueli","doi":"10.1109/VLSIC.1990.111126","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111126","url":null,"abstract":"A bit-level pipelined 12-b×12-b two's complement multiplier with a 27-b accumulator has been designed and fabricated in a 1-μm CMOS technology. A novel quasi N-P domino logic structure has been adopted to increase the throughput, and special pipeline structures were used to reduce the latency significantly. The measured maximum clock rate is 140 MHz (i.e. 140 million multiply-accumulate operations per second), and the typical power-speed ratio is 11 mW/MHz. The chip complexity is 10000 transistors and the 68-pad chip area is 2.5 mm×3.7 mm","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133744801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111125
F. Lai
A hybrid number system data execution unit which supports the 32-b IEEE 754 floating-point and a 32-b logarithmic number system is described. By using the proposed conversion algorithms, a very-high-performance data execution unit is realized for all basic arithmetic operations, such as multiplication, division, squaring, and square root. These operations, in a pipelined structure, can be executed in 10 ns in a 0.8-μm CMOS technology. Critical paths, such as the required 12-b by 12-b Booth multiplier, are implemented with the redundant binary bit representation to enhance the performance, and the multiple-port ROMs are carefully laid out and use half-VDD precharge to reduce the access time. The architecture, circuit design, and design methodology are described in detail. Simulated circuit performance of this data execution unit is also discussed
介绍了一种支持32b IEEE 754浮点数和32b对数数的混合数制数据执行单元。通过使用所提出的转换算法，实现了所有基本算术运算(如乘法、除法、平方和平方根)的高性能数据执行单元。这些操作采用流水线结构，在0.8 μ m CMOS技术中可在10ns内完成。关键路径，如所需的12b × 12b Booth乘子，通过冗余二进制位表示来实现以提高性能，并且精心布局多端口rom并使用半vdd预充电来减少访问时间。详细介绍了系统的结构、电路设计和设计方法。文中还讨论了该数据执行单元的仿真电路性能
{"title":"Design of a 100 MHz hybrid number system data execution unit","authors":"F. Lai","doi":"10.1109/VLSIC.1990.111125","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111125","url":null,"abstract":"A hybrid number system data execution unit which supports the 32-b IEEE 754 floating-point and a 32-b logarithmic number system is described. By using the proposed conversion algorithms, a very-high-performance data execution unit is realized for all basic arithmetic operations, such as multiplication, division, squaring, and square root. These operations, in a pipelined structure, can be executed in 10 ns in a 0.8-μm CMOS technology. Critical paths, such as the required 12-b by 12-b Booth multiplier, are implemented with the redundant binary bit representation to enhance the performance, and the multiple-port ROMs are carefully laid out and use half-VDD precharge to reduce the access time. The architecture, circuit design, and design methodology are described in detail. Simulated circuit performance of this data execution unit is also discussed","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130498579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111086
K. Fung, T. Suzuki, J. Terazawa, A. Khayami, S. Martindell, C. Blanton, H. Tran, R. Eklund, S. Madan, T. Holloway, M. Rodder, J. Graham, R. Chapman, R. Haken, D. Scott
A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory cell of 28 μm2
{"title":"An experimental 5 ns BiCMOS SRAM with a high-speed architecture","authors":"K. Fung, T. Suzuki, J. Terazawa, A. Khayami, S. Martindell, C. Blanton, H. Tran, R. Eklund, S. Madan, T. Holloway, M. Rodder, J. Graham, R. Chapman, R. Haken, D. Scott","doi":"10.1109/VLSIC.1990.111086","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111086","url":null,"abstract":"A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory cell of 28 μm2","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116458809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111116
H. Stiegler, B. Ashmore, R. Bussey, M. Gill, S. Lin, M. McConnell, D. McElroy, J. Schreck, P. Shah, P. Truong, A. Esquivel, J. Paterson, B. Riemenschneider
A full 4-Mb flash EEPROM was fabricated in 0.8-μm CMOS and its functionality was verified. Conservative 1.0-μm features were used in the periphery, resulting in a die area of 95 mm2. The device features 5-V-only operation and either full-chip or sector erase. A segmented architecture, remote row decode, and innovative design techniques provide the sector erase feature and high-voltage handling with improved breakdown protection and isolation
在0.8 μ m CMOS上制作了一个完整的4mb闪存EEPROM，并对其功能进行了验证。外围采用保守的1.0-μm特征，导致模具面积为95 mm2。该器件具有仅5v操作和全芯片或扇区擦除功能。分段架构、远程行解码和创新的设计技术提供了扇区擦除功能和高压处理，并改进了击穿保护和隔离
{"title":"A 4 Mb 5 V-only flash EEPROM with sector erase","authors":"H. Stiegler, B. Ashmore, R. Bussey, M. Gill, S. Lin, M. McConnell, D. McElroy, J. Schreck, P. Shah, P. Truong, A. Esquivel, J. Paterson, B. Riemenschneider","doi":"10.1109/VLSIC.1990.111116","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111116","url":null,"abstract":"A full 4-Mb flash EEPROM was fabricated in 0.8-μm CMOS and its functionality was verified. Conservative 1.0-μm features were used in the periphery, resulting in a die area of 95 mm2. The device features 5-V-only operation and either full-chip or sector erase. A segmented architecture, remote row decode, and innovative design techniques provide the sector erase feature and high-voltage handling with improved breakdown protection and isolation","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121515971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111117
T. Tanaka, M. Momodomi, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R. Shirota, K. Ohuchi, F. Masuoka
The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin p-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design
{"title":"A 4-Mbit NAND-EEPROM with tight programmed Vt distribution","authors":"T. Tanaka, M. Momodomi, Y. Iwata, Y. Tanaka, H. Oodaira, Y. Itoh, R. Shirota, K. Ohuchi, F. Masuoka","doi":"10.1109/VLSIC.1990.111117","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111117","url":null,"abstract":"The authors describe a 4-Mb NAND-EEPROM with tight Vt (threshold voltage) distribution which is controlled by a novel program verify technique. A tight Vt distribution width of 0.6 V for the entire 4-Mb cell array is achieved, and read margin is improved. A unique twin p-well structure has made it possible to realize low-power 5-V-only erase/program operation easily compared with the previous design","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125170277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111105
Dong-Sun Min Dong-Sun Min, Dong-Il Seo Dong-Il Seo, Jehwan You Jehwan You, Sooin Cho Sooin Cho, Daeje Chin Daeje Chin, Y.E. Park
The wordline architecture of the twisted word line (TWL) scheme and a wordline latch circuit for suppressing wordline coupling noise have been proposed and demonstrated. Using this approach, wordline coupling noise is reduced by 70% compared to the conventional wordline structure. This technique was found to be effective for suppressing wordline coupling noise with minimum layout penalty in scaled high-density DRAMs
{"title":"Wordline coupling noise reduction techniques for scaled DRAMs","authors":"Dong-Sun Min Dong-Sun Min, Dong-Il Seo Dong-Il Seo, Jehwan You Jehwan You, Sooin Cho Sooin Cho, Daeje Chin Daeje Chin, Y.E. Park","doi":"10.1109/VLSIC.1990.111105","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111105","url":null,"abstract":"The wordline architecture of the twisted word line (TWL) scheme and a wordline latch circuit for suppressing wordline coupling noise have been proposed and demonstrated. Using this approach, wordline coupling noise is reduced by 70% compared to the conventional wordline structure. This technique was found to be effective for suppressing wordline coupling noise with minimum layout penalty in scaled high-density DRAMs","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127480197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-06-07DOI: 10.1109/VLSIC.1990.111088
Y. Nakase, T. Ikeda, K. Mashiko, S. Kayano
A reduced word line voltage swing circuit is proposed in order to achieve high-speed ECL (emitter coupled logic) RAMs. This makes the word line voltage swing small without any sacrifice of the write operation, and allows 25% faster read operation to be obtained. In the circuit, large ISR and small reverse mode current gain are required for the fast write operation
{"title":"A 2 ns 16 K ECL RAM with reduced word line voltage swing","authors":"Y. Nakase, T. Ikeda, K. Mashiko, S. Kayano","doi":"10.1109/VLSIC.1990.111088","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111088","url":null,"abstract":"A reduced word line voltage swing circuit is proposed in order to achieve high-speed ECL (emitter coupled logic) RAMs. This makes the word line voltage swing small without any sacrifice of the write operation, and allows 25% faster read operation to be obtained. In the circuit, large ISR and small reverse mode current gain are required for the fast write operation","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132673735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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