An algorithm for random testing of functional faults in RAMs based on the modification of a random testing experiment algorithm is developed. To examine the effectiveness of the algorithm for the testing of stuck-at faults, inversion 2-coupling faults, and type 1 active neighborhood pattern sensitive faults on a reduced memory model, the authors present a simulation package.<>
{"title":"Functional testing of RAMs by random testing simulation","authors":"M. Ashtijou, Fusheng Chen","doi":"10.1109/MT.1993.263151","DOIUrl":"https://doi.org/10.1109/MT.1993.263151","url":null,"abstract":"An algorithm for random testing of functional faults in RAMs based on the modification of a random testing experiment algorithm is developed. To examine the effectiveness of the algorithm for the testing of stuck-at faults, inversion 2-coupling faults, and type 1 active neighborhood pattern sensitive faults on a reduced memory model, the authors present a simulation package.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115653723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the growing complexity of semiconductor memories a good understanding of memory fault models becomes very important. In this paper, the author discusses the coupling and pattern sensitive fault (PSF) models in detail. Test algorithms to cover these faults are given. Pros and cons of different test algorithms are discussed and validity of fault models is examined.<>
{"title":"Algorithms to test PSF and coupling faults in random access memories","authors":"R. Rajsuman","doi":"10.1109/MT.1993.263150","DOIUrl":"https://doi.org/10.1109/MT.1993.263150","url":null,"abstract":"With the growing complexity of semiconductor memories a good understanding of memory fault models becomes very important. In this paper, the author discusses the coupling and pattern sensitive fault (PSF) models in detail. Test algorithms to cover these faults are given. Pros and cons of different test algorithms are discussed and validity of fault models is examined.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132013756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The author describes a 20 MHz RAM test vector generator that generates both deterministic and probabilistic tests for detecting single 4-coupling or 5-coupling faults (as defined by Nair, Thatte, and Abraham). Such faults model pattern sensitivities involving 4 or 5 cells, respectively, when nothing is known about the mapping from logical cell addresses to physical cell locations. The generated tests are thus unaffected by cell re-arrangements resulting from multiple vendors, decoder address scrambling, and repair using redundant cells. Using a parallel test mode, all sub-arrays in a RAM can be tested together even if each sub-array has a different cell arrangement. The generator consists of one 60 K transistor semicustom IC and one 4 Mbit look-up PROM.<>
{"title":"A 20 MHz test vector generator for producing tests that detect single 4- and 5-coupling faults in RAMs","authors":"B. Cockburn","doi":"10.1109/MT.1993.263157","DOIUrl":"https://doi.org/10.1109/MT.1993.263157","url":null,"abstract":"The author describes a 20 MHz RAM test vector generator that generates both deterministic and probabilistic tests for detecting single 4-coupling or 5-coupling faults (as defined by Nair, Thatte, and Abraham). Such faults model pattern sensitivities involving 4 or 5 cells, respectively, when nothing is known about the mapping from logical cell addresses to physical cell locations. The generated tests are thus unaffected by cell re-arrangements resulting from multiple vendors, decoder address scrambling, and repair using redundant cells. Using a parallel test mode, all sub-arrays in a RAM can be tested together even if each sub-array has a different cell arrangement. The generator consists of one 60 K transistor semicustom IC and one 4 Mbit look-up PROM.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"99 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132324927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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