The authors solve the fault location problem for a realistic fault model that is based on the physical defects and resulting faulty behaviours observed in 4 Mbit DRAMs manufactured by Siemens. Assuming an n*1 DRAM organization, they derive a lower bound of 8n on the length of any march test that locates all of the faults in the fault model. They then propose a march test whose length matches the lower bound, and then show that this test has 100% fault coverage.<>
{"title":"An optimal march test for locating faults in DRAMs","authors":"Lin. Shen, B. Cockburn","doi":"10.1109/MT.1993.263148","DOIUrl":"https://doi.org/10.1109/MT.1993.263148","url":null,"abstract":"The authors solve the fault location problem for a realistic fault model that is based on the physical defects and resulting faulty behaviours observed in 4 Mbit DRAMs manufactured by Siemens. Assuming an n*1 DRAM organization, they derive a lower bound of 8n on the length of any march test that locates all of the faults in the fault model. They then propose a march test whose length matches the lower bound, and then show that this test has 100% fault coverage.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129291532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Hamada, M. Kumanoya, M. Ishii, T. Kawagoe, M. Niiro
The authors describe a new high-speed Shmoo plot algorithm for ULSI memory devices. The proposed boundary search method is 8 times faster than the conventional (linear searching) method. Using this method the evaluation time of a 64 Mbit memory is reduced to 2.5 hours from the 20 hours of the conventional method.<>
{"title":"A high-speed boundary search Shmoo plot for ULSI memories","authors":"M. Hamada, M. Kumanoya, M. Ishii, T. Kawagoe, M. Niiro","doi":"10.1109/MT.1993.263158","DOIUrl":"https://doi.org/10.1109/MT.1993.263158","url":null,"abstract":"The authors describe a new high-speed Shmoo plot algorithm for ULSI memory devices. The proposed boundary search method is 8 times faster than the conventional (linear searching) method. Using this method the evaluation time of a 64 Mbit memory is reduced to 2.5 hours from the 20 hours of the conventional method.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"49 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121260272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Some results from qualification test procedures on 64 k (4 designs) and 256 k (4 designs) EEPROM as well as 1 M (4 designs) flash memories are presented. Electrical characterization, various environmental tests, and reliability tests on up to about 220 devices per design were performed. Different defect and failed devices were detected and failure analysis (whenever possible) was accomplished. The results indicate enhancements of the quality and reliability of newer NV-memory generations but the levels of other standard memories (DRAM, SRAM) are not reached yet.<>
{"title":"Are NV-memories non-volatile?","authors":"D. Ratchev","doi":"10.1109/MT.1993.263141","DOIUrl":"https://doi.org/10.1109/MT.1993.263141","url":null,"abstract":"Some results from qualification test procedures on 64 k (4 designs) and 256 k (4 designs) EEPROM as well as 1 M (4 designs) flash memories are presented. Electrical characterization, various environmental tests, and reliability tests on up to about 220 devices per design were performed. Different defect and failed devices were detected and failure analysis (whenever possible) was accomplished. The results indicate enhancements of the quality and reliability of newer NV-memory generations but the levels of other standard memories (DRAM, SRAM) are not reached yet.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123171596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Completeness and irredundancy proofs for SRAM march tests can be quite complicated. The authors present a method to automatically verify march tests. This method can be adapted for any other memory test. They present a way of modelling faults mathematically and describe how the verification process has been automated.<>
{"title":"Automatic verification of march tests (SRAMs)","authors":"A. van de Goor, B. Smit","doi":"10.1109/MT.1993.263136","DOIUrl":"https://doi.org/10.1109/MT.1993.263136","url":null,"abstract":"Completeness and irredundancy proofs for SRAM march tests can be quite complicated. The authors present a method to automatically verify march tests. This method can be adapted for any other memory test. They present a way of modelling faults mathematically and describe how the verification process has been automated.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128986825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
First-in-first-out (FIFO) memories are becoming increasingly popular as buffer storage between subsystems operating at different data rates. One way to implement a FIFO is to use a single-port SRAM memory with arbitration logic to resolve conflicts due to simultaneous read and write requests. The well-know functional tests for SRAMs cannot be applied to FIFOs because of their built in access restrictions. Functional fault models and functional tests for FIFOs have been presented by van de Goor (1992). This paper presents functional fault models together with a set of tests and their correctness proofs for the logic implementing the FIFO functionality; e.g. embedded address registers, multiplexers, empty and full flags, etc.<>
先进先出(FIFO)存储器作为以不同数据速率运行的子系统之间的缓冲存储器正变得越来越流行。实现FIFO的一种方法是使用带有仲裁逻辑的单端口SRAM内存来解决由于同时读取和写入请求而产生的冲突。众所周知的sram功能测试不能应用于fifo，因为它们具有内置的访问限制。van de Goor(1992)提出了fifo的功能故障模型和功能测试。本文提出了实现FIFO功能的逻辑的功能故障模型，并给出了一组测试和它们的正确性证明;例如，嵌入式地址寄存器，多路复用器，空和满标志等。
{"title":"Fault models and tests specific for FIFO functionality","authors":"A. van de Goor, Y. Zorian","doi":"10.1109/MT.1993.263146","DOIUrl":"https://doi.org/10.1109/MT.1993.263146","url":null,"abstract":"First-in-first-out (FIFO) memories are becoming increasingly popular as buffer storage between subsystems operating at different data rates. One way to implement a FIFO is to use a single-port SRAM memory with arbitration logic to resolve conflicts due to simultaneous read and write requests. The well-know functional tests for SRAMs cannot be applied to FIFOs because of their built in access restrictions. Functional fault models and functional tests for FIFOs have been presented by van de Goor (1992). This paper presents functional fault models together with a set of tests and their correctness proofs for the logic implementing the FIFO functionality; e.g. embedded address registers, multiplexers, empty and full flags, etc.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129342534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To accelerate deterministic functional memory chip testing, the authors propose modifying a memory chip using circuit structures known from flag-oriented associative memories. Based on these modifications new test algorithms have been developed. Compared with existing test algorithms the complexity of algorithms developed for fault detection is one or two orders lower. For fault localization it is approximately one order lower and depends additionally on the number of faulty cells in a memory chip. It is shown that this complexity can be reduced further using contents-oriented processing of the information stored in a memory with corresponding circuit structures. In this contribution the basics of the new test approach, the structure of the newly developed test algorithms, the hardware requirements and the achievable test acceleration are discussed.<>
{"title":"Associative search based test algorithms for test acceleration in FAST-RAMs","authors":"C. Elm, D. Tavangarian","doi":"10.1109/MT.1993.263152","DOIUrl":"https://doi.org/10.1109/MT.1993.263152","url":null,"abstract":"To accelerate deterministic functional memory chip testing, the authors propose modifying a memory chip using circuit structures known from flag-oriented associative memories. Based on these modifications new test algorithms have been developed. Compared with existing test algorithms the complexity of algorithms developed for fault detection is one or two orders lower. For fault localization it is approximately one order lower and depends additionally on the number of faulty cells in a memory chip. It is shown that this complexity can be reduced further using contents-oriented processing of the information stored in a memory with corresponding circuit structures. In this contribution the basics of the new test approach, the structure of the newly developed test algorithms, the hardware requirements and the achievable test acceleration are discussed.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"713 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133050810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In order to make decoder lines shorter, and thus decrease average access-times to the cells, SRAM designers employ a cascaded, multiple-array structure-instead of building SRAMs as a single 'monolithic' array of cells. By rearranging traditional memory test patterns to take account of the true distribution of decoder branches within the die layout, the test can be focussed on cells which form a single array 'segment', (i.e. cells that share the same row/column decoders). This 'segmented' test pattern requires fewer cycles to execute, and in nearly all cases has at least the same fault coverage as the traditional 'monolithic' version of the test pattern. Additionally, these 'segmented' patterns can be ideally handled by logic test ATE using the modern 'per-pin' resource architecture, to take advantage of the superior accuracy and vector rate of these testers.<>
{"title":"Segmentation: a technique for adapting high-performance logic ATE to test high-density, high-speed SRAMs","authors":"Ruben Mookerjee","doi":"10.1109/MT.1993.263138","DOIUrl":"https://doi.org/10.1109/MT.1993.263138","url":null,"abstract":"In order to make decoder lines shorter, and thus decrease average access-times to the cells, SRAM designers employ a cascaded, multiple-array structure-instead of building SRAMs as a single 'monolithic' array of cells. By rearranging traditional memory test patterns to take account of the true distribution of decoder branches within the die layout, the test can be focussed on cells which form a single array 'segment', (i.e. cells that share the same row/column decoders). This 'segmented' test pattern requires fewer cycles to execute, and in nearly all cases has at least the same fault coverage as the traditional 'monolithic' version of the test pattern. Additionally, these 'segmented' patterns can be ideally handled by logic test ATE using the modern 'per-pin' resource architecture, to take advantage of the superior accuracy and vector rate of these testers.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130455520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is known that test pattern generation even for fixed structured realizations of digital circuits, i.e. PLAs is a NP-complete problem. With respect to the growing complexity of integrated circuits, this process has to be optimized to avoid large development and production cycles. The target of the authors' work is a method (as a part of fault simulation), which speeds up the process of test pattern generation for regular structures as PLAs, ROMs, RAMs and which also reduces time and storage complexity.<>
{"title":"PLA test pattern generation with orthogonal transform","authors":"M.W. Riege, S. Wolter, W. Anheier","doi":"10.1109/MT.1993.263156","DOIUrl":"https://doi.org/10.1109/MT.1993.263156","url":null,"abstract":"It is known that test pattern generation even for fixed structured realizations of digital circuits, i.e. PLAs is a NP-complete problem. With respect to the growing complexity of integrated circuits, this process has to be optimized to avoid large development and production cycles. The target of the authors' work is a method (as a part of fault simulation), which speeds up the process of test pattern generation for regular structures as PLAs, ROMs, RAMs and which also reduces time and storage complexity.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125158007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A radiation hardened circuit should be both processed and designed for hardness. It is demonstrated that the MOSIS two micron CMOS technology exhibits radiation hardened properties, making it particularly suitable for a design methodology in which circuitry is added to compensate for the radiation induced degradation of the zero input noise margin. The non-ideal behavior of the compensation circuitry is explained and application of the circuitry in a static RAM cell is explored.<>
{"title":"Total dose radiation hardening and testing issues of CMOS static memories","authors":"R. Hensley, A. Srivastava","doi":"10.1109/MT.1993.263140","DOIUrl":"https://doi.org/10.1109/MT.1993.263140","url":null,"abstract":"A radiation hardened circuit should be both processed and designed for hardness. It is demonstrated that the MOSIS two micron CMOS technology exhibits radiation hardened properties, making it particularly suitable for a design methodology in which circuitry is added to compensate for the radiation induced degradation of the zero input noise margin. The non-ideal behavior of the compensation circuitry is explained and application of the circuitry in a static RAM cell is explored.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126483631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, the authors take advantage from the regularity of the RAM test algorithms and show that exact aliasing computation and/or aliasing free signature analysis can be achieved in RAM BIST.<>
{"title":"Exact aliasing computation and/or aliasing free design for RAM BIST","authors":"V. Yarmolik, M. Nicolaidis","doi":"10.1109/MT.1993.263155","DOIUrl":"https://doi.org/10.1109/MT.1993.263155","url":null,"abstract":"Signature analyzers are very efficient output response compactors in BIST techniques. The only limitation of signature analysis is the fault coverage reduction (aliasing) due to the information loss inherent to any data compaction. In this paper, in order to increase the effectiveness of RAM BIST, the authors take advantage from the regularity of the RAM test algorithms and show that exact aliasing computation and/or aliasing free signature analysis can be achieved in RAM BIST.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"74 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133239210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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