Pub Date : 2008-07-10DOI: 10.1109/ECCSC.2008.4611658
A. Pugliese, F. Amoroso, G. Cappuccino, G. Cocorullo
A novel design procedure for two-stage operational amplifiers (op-amps) with current-buffer Miller compensation (CBMC) is proposed. The method is based on equations which relate both bias current and aspect ratio of transistors to the main amplifier parameters. The important innovation of the procedure is the definition of a systematic strategy to achieve the desired settling time by performing the op-amp dynamic behaviour optimization, which is badly needed in high-performance discrete-time applications. To prove the effectiveness of the proposed approach, a design example of a CBMC op-amp in 0.35 mum CMOS technology is presented.
提出了一种带电流缓冲米勒补偿的两级运算放大器的设计方法。该方法基于将晶体管的偏置电流和宽高比与主放大器参数联系起来的方程。该过程的重要创新是定义了一种系统策略，通过执行运放动态行为优化来实现所需的稳定时间，这在高性能离散时间应用中是非常需要的。为了证明该方法的有效性，给出了一个0.35 μ m CMOS技术的CBMC运放设计实例。
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Pub Date : 2008-07-10DOI: 10.1109/ECCSC.2008.4611669
L. Dumitriu, M. Iordache, G. Stamatescu
Widely-separated time scales appear in many electronic circuits, making traditional analysis difficult even impossible if the circuits are highly nonlinear. The paper presents a new version of the modified nodal method in two time variables for the analysis of the circuit with widely separated time scales. By applying this approach the differential algebraic equations (DAE) describing the nonlinear analog circuits driven by multi-tone signals are transformed into multi-time partial differential equations (MPDEs). In order to solve MPDEs, associated resistive discrete equivalent circuits (companion circuits) for the dynamic circuit elements are used. The boundary conditions are detailed and simulation results are presented.
{"title":"Boundary conditions for multi-tone steady-state analysis of nonlinear integrated analog circuits","authors":"L. Dumitriu, M. Iordache, G. Stamatescu","doi":"10.1109/ECCSC.2008.4611669","DOIUrl":"https://doi.org/10.1109/ECCSC.2008.4611669","url":null,"abstract":"Widely-separated time scales appear in many electronic circuits, making traditional analysis difficult even impossible if the circuits are highly nonlinear. The paper presents a new version of the modified nodal method in two time variables for the analysis of the circuit with widely separated time scales. By applying this approach the differential algebraic equations (DAE) describing the nonlinear analog circuits driven by multi-tone signals are transformed into multi-time partial differential equations (MPDEs). In order to solve MPDEs, associated resistive discrete equivalent circuits (companion circuits) for the dynamic circuit elements are used. The boundary conditions are detailed and simulation results are presented.","PeriodicalId":249205,"journal":{"name":"2008 4th European Conference on Circuits and Systems for Communications","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129461013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-10DOI: 10.1109/ECCSC.2008.4611685
Muhammad Ali, Michael Welzl, Martin. Zwicknagl, Muhammad Ali
According to the International Technology Roadmap for Semiconductors (ITRS), before the end of this decade we will be entering the era of a billion transistors on a single chip. It is being stated that soon we will have a chip of 50-100 nm comprising around 4 billion transistors operating at a frequency of 10 Ghz. Such a development means that in the near future we probably have devices with such complex functions ranging from mere mobile phones to mobile devices controlling satellite functions. But developing such kind of chips is not an easy task as the number of transistors increases on-chip, and so does the complexity of integrating them. Todaypsilas SoCs use shared or dedicated buses to interconnect the communicating on-chip resources. However, these buses are not scalable beyond a certain limit. In this case, the current interconnect infrastructure will become a bottleneck for the development of billion transistor chips. Hence, in this tutorial, we will try to highlight a new design paradigm that has been proposed to counter the inefficiency of buses in future SoCs. This new design paradigm has been termed with a variety of titles, but the most common and agreed upon one is networks on chips (NoCs). We will show that how this paradigm shift from ordinary buses to networks on chips can make the kind of SoCs mentioned above very much possible.
{"title":"Networks on Chips: Scalable interconnects for future systems on chips","authors":"Muhammad Ali, Michael Welzl, Martin. Zwicknagl, Muhammad Ali","doi":"10.1109/ECCSC.2008.4611685","DOIUrl":"https://doi.org/10.1109/ECCSC.2008.4611685","url":null,"abstract":"According to the International Technology Roadmap for Semiconductors (ITRS), before the end of this decade we will be entering the era of a billion transistors on a single chip. It is being stated that soon we will have a chip of 50-100 nm comprising around 4 billion transistors operating at a frequency of 10 Ghz. Such a development means that in the near future we probably have devices with such complex functions ranging from mere mobile phones to mobile devices controlling satellite functions. But developing such kind of chips is not an easy task as the number of transistors increases on-chip, and so does the complexity of integrating them. Todaypsilas SoCs use shared or dedicated buses to interconnect the communicating on-chip resources. However, these buses are not scalable beyond a certain limit. In this case, the current interconnect infrastructure will become a bottleneck for the development of billion transistor chips. Hence, in this tutorial, we will try to highlight a new design paradigm that has been proposed to counter the inefficiency of buses in future SoCs. This new design paradigm has been termed with a variety of titles, but the most common and agreed upon one is networks on chips (NoCs). We will show that how this paradigm shift from ordinary buses to networks on chips can make the kind of SoCs mentioned above very much possible.","PeriodicalId":249205,"journal":{"name":"2008 4th European Conference on Circuits and Systems for Communications","volume":"487 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133251306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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