Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806569
M. Zmuda, A. Elesev, Y. Morton
A mobile robot must know its position in order to operate autonomously. The process of determining the robot's absolute position from sensor data is called robot localization. Sonar, inertial, RF, and laser sensors can all be used for navigation and localization purposes. These sensors can achieve good accuracy when operating in certain conditions. For example, sonar is useful when operating in a mapped environment containing known obstacles. Inertial sensors have trouble with drift, which is accentuated when moving continuously for long periods of time. By merging the results from multiple sensors, the accuracy over a wider range of conditions can be obtained. This work proposes a technique of merging heterogeneous signals from inertial and RF sensors. Since sensors have errors associated with their readings, the robot's state will be represented probabilistically. Based on the sensors used in this work, the robot's position, velocity, and acceleration will be estimated using a joint probability distribution function (PDF). At each time step, this PDF will be updated based on the RF readings and then updated again based on the readings from the inertial sensor. The proposed algorithm will be applied to simulation of an uncluttered, level environment. The accuracy of the localization algorithm is compared to the accuracies obtained by other localization algorithms. The results show better localization accuracy when using the RF and inertial sensors together.
{"title":"Robot Localization Using RE and Inertial Sensors","authors":"M. Zmuda, A. Elesev, Y. Morton","doi":"10.1109/NAECON.2008.4806569","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806569","url":null,"abstract":"A mobile robot must know its position in order to operate autonomously. The process of determining the robot's absolute position from sensor data is called robot localization. Sonar, inertial, RF, and laser sensors can all be used for navigation and localization purposes. These sensors can achieve good accuracy when operating in certain conditions. For example, sonar is useful when operating in a mapped environment containing known obstacles. Inertial sensors have trouble with drift, which is accentuated when moving continuously for long periods of time. By merging the results from multiple sensors, the accuracy over a wider range of conditions can be obtained. This work proposes a technique of merging heterogeneous signals from inertial and RF sensors. Since sensors have errors associated with their readings, the robot's state will be represented probabilistically. Based on the sensors used in this work, the robot's position, velocity, and acceleration will be estimated using a joint probability distribution function (PDF). At each time step, this PDF will be updated based on the RF readings and then updated again based on the readings from the inertial sensor. The proposed algorithm will be applied to simulation of an uncluttered, level environment. The accuracy of the localization algorithm is compared to the accuracies obtained by other localization algorithms. The results show better localization accuracy when using the RF and inertial sensors together.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121035349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806536
V. Sundaresan, S. Rammohan, R. Vemuri
Side-channel power analysis attacks have become a potent threat to the security of embedded cryptographic devices in microelectronic systems. In this paper, we present an overview of the various side-channel power analysis attacks and defenses (countermeasures) against side-channel power analysis attacks. We introduce these countermeasures and present analyses based on security strength, ease of integration with EDA flows, and hardware characteristics like area, performance and power consumption. This paper is intended as a stepping stone towards developing more practical security-centric design methods that can be efficiently integrated with existing commercially viable designs and EDA flows, resulting in secure as well as hardware optimal implementations of side-channel power analysis attack resistant cryptographic devices.
{"title":"Defense against Side-Channel Power Analysis Attacks on Microelectronic Systems","authors":"V. Sundaresan, S. Rammohan, R. Vemuri","doi":"10.1109/NAECON.2008.4806536","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806536","url":null,"abstract":"Side-channel power analysis attacks have become a potent threat to the security of embedded cryptographic devices in microelectronic systems. In this paper, we present an overview of the various side-channel power analysis attacks and defenses (countermeasures) against side-channel power analysis attacks. We introduce these countermeasures and present analyses based on security strength, ease of integration with EDA flows, and hardware characteristics like area, performance and power consumption. This paper is intended as a stepping stone towards developing more practical security-centric design methods that can be efficiently integrated with existing commercially viable designs and EDA flows, resulting in secure as well as hardware optimal implementations of side-channel power analysis attack resistant cryptographic devices.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"600 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132184467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806527
K.M. Singh, L. Brott, J. Grote, R. Naik
Biopolymers have received much attention lately for use in electronic applications. Salmon DNA complexed with cetyltrimethyl ammonium chloride (DNA-CTMA) produces a material soluble in organic solvents, enhancing the ease of processing. DNA-CTMA has shown promise as an electron blocking layer in organic light emitting diodes (OLEDs) and potential as a gate insulating material in field effect transistors (FETs). To realize an all bio-based FET, we are continuing to investigate the use of DNA as the semiconducting layer. In addition to tailoring the properties of the biomaterial to increase the conductivity, we are also trying to better characterize these materials and explore different deposition techniques. Inkjet printing offers an unique ability to reproducibly deposit materials in a spatially controlled fashion, using picoliter amounts with high throughput. This paper will present how parameters such as solvent evaporation rate and substrate influence film properties. The characterization of the resulting DNA films includes atomic force microscopy (AFM) and white light interferometry.
{"title":"Inkjet Printing of DNA for Use in Bioelectronic Applications","authors":"K.M. Singh, L. Brott, J. Grote, R. Naik","doi":"10.1109/NAECON.2008.4806527","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806527","url":null,"abstract":"Biopolymers have received much attention lately for use in electronic applications. Salmon DNA complexed with cetyltrimethyl ammonium chloride (DNA-CTMA) produces a material soluble in organic solvents, enhancing the ease of processing. DNA-CTMA has shown promise as an electron blocking layer in organic light emitting diodes (OLEDs) and potential as a gate insulating material in field effect transistors (FETs). To realize an all bio-based FET, we are continuing to investigate the use of DNA as the semiconducting layer. In addition to tailoring the properties of the biomaterial to increase the conductivity, we are also trying to better characterize these materials and explore different deposition techniques. Inkjet printing offers an unique ability to reproducibly deposit materials in a spatially controlled fashion, using picoliter amounts with high throughput. This paper will present how parameters such as solvent evaporation rate and substrate influence film properties. The characterization of the resulting DNA films includes atomic force microscopy (AFM) and white light interferometry.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124562809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806552
D. Walker, L. Hogrebe, B. Fortener, D. Lucking
Since the initiation of JPEG in the mid-to-late 1980's, the JPEG standard has remained a viable solution for image compression in many applications. However, many modern applications seek significant improvements in image compression, particularly for compressed image representations at higher compression gains. Coupled with the growing interest in improving compression technology is the fact that bigger image sizes have become increasingly popular. In addition to the combined challenges of higher compression gains, large image sizes, and extremely long image sequences (e.g. in persistent surveillance durations consisting of hours, days, or months), many applications desire real-time or near real-time availability of compressed images for viewing and distribution. JPEG2000 is an often sought compression solution and is being increasingly adopted for future compression systems. However, for real-time compression systems one of the major challenges JPEG2000 presents is its very demanding computational intensity. It is this high computational intensity that mitigates much of the current interest in expanding JPEG2000's use in embedded and real-time applications. Planning for the implementation of a JPEG2000 system requires addressing all of the challenges listed above, particularly the computational needs. Fortunately, this intensive processing can be partitioned into concurrent processing modules that are suitable for FPGA implementation. This paper focuses on providing an outline of the major components of a JPEG2000 encoder and the requirements they impose for an example embedded application.
{"title":"Planning for a Real-Time JPEG2000 Compression System","authors":"D. Walker, L. Hogrebe, B. Fortener, D. Lucking","doi":"10.1109/NAECON.2008.4806552","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806552","url":null,"abstract":"Since the initiation of JPEG in the mid-to-late 1980's, the JPEG standard has remained a viable solution for image compression in many applications. However, many modern applications seek significant improvements in image compression, particularly for compressed image representations at higher compression gains. Coupled with the growing interest in improving compression technology is the fact that bigger image sizes have become increasingly popular. In addition to the combined challenges of higher compression gains, large image sizes, and extremely long image sequences (e.g. in persistent surveillance durations consisting of hours, days, or months), many applications desire real-time or near real-time availability of compressed images for viewing and distribution. JPEG2000 is an often sought compression solution and is being increasingly adopted for future compression systems. However, for real-time compression systems one of the major challenges JPEG2000 presents is its very demanding computational intensity. It is this high computational intensity that mitigates much of the current interest in expanding JPEG2000's use in embedded and real-time applications. Planning for the implementation of a JPEG2000 system requires addressing all of the challenges listed above, particularly the computational needs. Fortunately, this intensive processing can be partitioned into concurrent processing modules that are suitable for FPGA implementation. This paper focuses on providing an outline of the major components of a JPEG2000 encoder and the requirements they impose for an example embedded application.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129356967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806550
Y. Shiyanovskii, F. Wolff, C. Papachristou, D. McIntyre
Self-reconfigurable and evolvable hardware is a new emerging technology which will enable adaptation of computing systems to changing environments. This paper deals with the design architecture of an autonomous on-board system and the development of a real-time scheduler for the adaptation manager of reconfigurable hardware fabric. Our approach employs computer architecture with two key layers: the adaptation manager and the real time configuration kernel. This has significant advantages in terms of flexibility, scalability, cost, and compatibility with embedded technology. Some preliminary results are presented.
{"title":"Reconfigurable and Evolvable Architecture for Autonomous on-board systems","authors":"Y. Shiyanovskii, F. Wolff, C. Papachristou, D. McIntyre","doi":"10.1109/NAECON.2008.4806550","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806550","url":null,"abstract":"Self-reconfigurable and evolvable hardware is a new emerging technology which will enable adaptation of computing systems to changing environments. This paper deals with the design architecture of an autonomous on-board system and the development of a real-time scheduler for the adaptation manager of reconfigurable hardware fabric. Our approach employs computer architecture with two key layers: the adaptation manager and the real time configuration kernel. This has significant advantages in terms of flexibility, scalability, cost, and compatibility with embedded technology. Some preliminary results are presented.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117353964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806546
S. Craven, P. Athanas
The dynamic reconfigurability of field programmable gate arrays offers great benefits to software defined radio applications. Leveraging these benefits is difficult, owing to a lack of tool support and the detailed architectural knowledge required. To fully exploit the potential of dynamic hardware, a high-level development environment has been created. This development environment has been validated by implementing a reconfigurable AM radio on a software defined radio platform.
{"title":"Dynamically Reconfigurable Radios from a High-Level Specification","authors":"S. Craven, P. Athanas","doi":"10.1109/NAECON.2008.4806546","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806546","url":null,"abstract":"The dynamic reconfigurability of field programmable gate arrays offers great benefits to software defined radio applications. Leveraging these benefits is difficult, owing to a lack of tool support and the detailed architectural knowledge required. To fully exploit the potential of dynamic hardware, a high-level development environment has been created. This development environment has been validated by implementing a reconfigurable AM radio on a software defined radio platform.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115479675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806580
Hyoung-Kook Kim, W. Jone
This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the syncronizer, and HSPICE is used to perform circuit analysis. The defects are exhaustively injected and simulated to find all possible faults that might occur in the synchronizer. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains.
{"title":"Fault Modeling and Analysis for Bridging Defects in a Synchronizer","authors":"Hyoung-Kook Kim, W. Jone","doi":"10.1109/NAECON.2008.4806580","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806580","url":null,"abstract":"This paper presents fault modeling and analysis for bridging defects in a synchronizer that is implemented by two D flip-flops. Bridging defects are injected into any two nodes of the syncronizer, and HSPICE is used to perform circuit analysis. The defects are exhaustively injected and simulated to find all possible faults that might occur in the synchronizer. The results obtained can be used to develop methods for testing the interfacing circuits between different clock domains.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121967952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806561
R. Vemuri, M. Borowczak, A. Avakian
This paper describes a methodology for safety-centric development of distributed embedded avionics realized as sense-actuate-control (SAC) networks. The methodology has consists of two parts. First, formal methods are used in defining and deriving families of SAC node architectures. This methodology eliminates redundant verification and validation (V&V) efforts across members of the same family of architectures. Second, proof-directed run-time error-monitor generation methodology is presented. This methodology links design-time verification with run-time error checking. Robust error monitors can be derived and reused across the members of a family of architectures.
{"title":"Safety-Centric Design of Distributed Embedded Avionics","authors":"R. Vemuri, M. Borowczak, A. Avakian","doi":"10.1109/NAECON.2008.4806561","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806561","url":null,"abstract":"This paper describes a methodology for safety-centric development of distributed embedded avionics realized as sense-actuate-control (SAC) networks. The methodology has consists of two parts. First, formal methods are used in defining and deriving families of SAC node architectures. This methodology eliminates redundant verification and validation (V&V) efforts across members of the same family of architectures. Second, proof-directed run-time error-monitor generation methodology is presented. This methodology links design-time verification with run-time error checking. Robust error monitors can be derived and reused across the members of a family of architectures.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116454439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806554
M. Jamali, B. Tran
Modern flight control systems process data from various sensors, execute control algorithms, and send data to various output devices and actuators. All control operations must be processed in real-time. Implementation of this system in embedded form would require the use of modern technology such as, DSPs, FPGAs or ASICs.
{"title":"FPGA Based Sensory/Actuation Embedded System","authors":"M. Jamali, B. Tran","doi":"10.1109/NAECON.2008.4806554","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806554","url":null,"abstract":"Modern flight control systems process data from various sensors, execute control algorithms, and send data to various output devices and actuators. All control operations must be processed in real-time. Implementation of this system in embedded form would require the use of modern technology such as, DSPs, FPGAs or ASICs.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132065489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-07-16DOI: 10.1109/NAECON.2008.4806559
B. Kahler, Erik Blasch
System control includes sensor management, user refinement, and mission accomplishment (SUM). An example of simultaneous tracking and identification includes (1) mission goals of resource appropriation and goal priorities, (2) user selection of targets and areas of coverage, and (3) fusion of data and sensory information. Many sensor management (SM) approaches are data-driven which includes filtering, aggregation, and normalization; however that does not include intelligent design. A top-down approach would facilitate the use of the right sensor, collecting the needed information, at the correct time. In order to better design SM algorithms, we utilize sensor, target, environmental, and automatic target recognition performance models for automatic target exploitation (ATE) prediction. Similar to pruning nodes in a Bayes net aggregation, a sensor manager can utilize the operating conditions (OCs) {i.e. sensor, target, environment} to condition the cost function, sensor-to-target assignment constraints, and scheduling times. An example is presented of determining task value of electro-optical sensor selection and scheduling based on the range to target, target size, and environmental conditions (e.g. occlusions). The key aspect of the SMOC provides accurate assignment and scheduling based on up-to-date database information, a capabilities matrix, and pragmatic sensor use to improve task satisfaction.
{"title":"Sensor Management Fusion Using Operating Conditions","authors":"B. Kahler, Erik Blasch","doi":"10.1109/NAECON.2008.4806559","DOIUrl":"https://doi.org/10.1109/NAECON.2008.4806559","url":null,"abstract":"System control includes sensor management, user refinement, and mission accomplishment (SUM). An example of simultaneous tracking and identification includes (1) mission goals of resource appropriation and goal priorities, (2) user selection of targets and areas of coverage, and (3) fusion of data and sensory information. Many sensor management (SM) approaches are data-driven which includes filtering, aggregation, and normalization; however that does not include intelligent design. A top-down approach would facilitate the use of the right sensor, collecting the needed information, at the correct time. In order to better design SM algorithms, we utilize sensor, target, environmental, and automatic target recognition performance models for automatic target exploitation (ATE) prediction. Similar to pruning nodes in a Bayes net aggregation, a sensor manager can utilize the operating conditions (OCs) {i.e. sensor, target, environment} to condition the cost function, sensor-to-target assignment constraints, and scheduling times. An example is presented of determining task value of electro-optical sensor selection and scheduling based on the range to target, target size, and environmental conditions (e.g. occlusions). The key aspect of the SMOC provides accurate assignment and scheduling based on up-to-date database information, a capabilities matrix, and pragmatic sensor use to improve task satisfaction.","PeriodicalId":254758,"journal":{"name":"2008 IEEE National Aerospace and Electronics Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116269985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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