Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176999
K. Sengupta, A. Hajimiri
Up until recently, the terahertz frequency range (0.3 to 3THz) has been mostly addressed by high-mobility custom III-V processes, bulky and expensive nonlinear optics, or cryogenically cooled quantum cascade lasers. A low-cost room temperature alternative will enable a wide range of applications in security, defense, ultra-high-speed wireless communication, sensors, and biomedical imaging not currently accessible due to cost and size limitations. CMOS can potentially provide such a low-cost platform, but it requires novel techniques and architectures to generate, manipulate, radiate, and detect signals above transistor fmax, which are in the sub-THz frequency region in most of today's nodes.
{"title":"A 0.28THz 4×4 power-generation and beam-steering array","authors":"K. Sengupta, A. Hajimiri","doi":"10.1109/ISSCC.2012.6176999","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176999","url":null,"abstract":"Up until recently, the terahertz frequency range (0.3 to 3THz) has been mostly addressed by high-mobility custom III-V processes, bulky and expensive nonlinear optics, or cryogenically cooled quantum cascade lasers. A low-cost room temperature alternative will enable a wide range of applications in security, defense, ultra-high-speed wireless communication, sensors, and biomedical imaging not currently accessible due to cost and size limitations. CMOS can potentially provide such a low-cost platform, but it requires novel techniques and architectures to generate, manipulate, radiate, and detect signals above transistor fmax, which are in the sub-THz frequency region in most of today's nodes.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"390 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123714533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177013
Chien-Wei Kuan, Hung-Chih Lin
For minimizing the power consumption in portable devices, efficient DC-DC converters with a wide range of regulated voltages and currents are needed. Considering the required footprint area, cost, and chip count, integration of single-inductor-multiple-output (SIMO) DC-DC converters into the system, particularly in scaled CMOS processes, is highly desirable. However, the cross regulation and low power density of SIMO solutions are obstacles to system integration [1-5]. Another problem is the capability of handling high battery voltage in advanced CMOS processes. This paper presents control and circuit techniques used in a 65nm CMOS SIMO buck converter with near-independently regulated five outputs and high power density.
{"title":"Near-independently regulated 5-output single-inductor DC-DC buck converter delivering 1.2W/mm2 in 65nm CMOS","authors":"Chien-Wei Kuan, Hung-Chih Lin","doi":"10.1109/ISSCC.2012.6177013","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177013","url":null,"abstract":"For minimizing the power consumption in portable devices, efficient DC-DC converters with a wide range of regulated voltages and currents are needed. Considering the required footprint area, cost, and chip count, integration of single-inductor-multiple-output (SIMO) DC-DC converters into the system, particularly in scaled CMOS processes, is highly desirable. However, the cross regulation and low power density of SIMO solutions are obstacles to system integration [1-5]. Another problem is the capability of handling high battery voltage in advanced CMOS processes. This paper presents control and circuit techniques used in a 65nm CMOS SIMO buck converter with near-independently regulated five outputs and high power density.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122162083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177044
Zushu Yan, Pui-in Mak, M. Law, R. Martins
High-color-depth LCD drivers require nF-range capacitors as the charge reservoirs to handle the glitch energy during the conversion of the DAC [1]. The reference buffers based on multi-stage amplifiers can enhance the precision under low-voltage supplies, but are exposed to instability when loaded by such large capacitive loads (CL). Frequency compensation via damping-factor control [2] is capable of extending the CL-drivability up to 1nF, however, at the cost of penalizing the power (426μW) and area (0.14mm2). Although recent works [3-4] have enhanced gain-bandwidth product (GBW) and slew rate (SR) showing better FOMS (=GBW·CL/Power) and FOML (=SR·CL/Power), the CL-drivability has not been improved (i.e., 0.8nF in [3] and 0.15nF in [4]). This paper describes a three-stage amplifier managed to afford particularly large and wide range of CL (1 to 15nF) with optimized power (144μW) and die size (0.016mm2), being very suitable for compact LCD drivers [5] with different resolution targets. The design barriers are methodically surmounted via local feedback loop (LFL) analysis expanded from [6], which is an insightful control-centric method. Measured at 15nF CL, the attained FOMS (FOML) is >;4.48× (>;2.55×) beyond that of the state-of-the-art (Fig. 21.6.1).
{"title":"A 0.016mm2 144μW three-stage amplifier capable of driving 1-to-15nF capacitive load with >0.95MHz GBW","authors":"Zushu Yan, Pui-in Mak, M. Law, R. Martins","doi":"10.1109/ISSCC.2012.6177044","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177044","url":null,"abstract":"High-color-depth LCD drivers require nF-range capacitors as the charge reservoirs to handle the glitch energy during the conversion of the DAC [1]. The reference buffers based on multi-stage amplifiers can enhance the precision under low-voltage supplies, but are exposed to instability when loaded by such large capacitive loads (C<sub>L</sub>). Frequency compensation via damping-factor control [2] is capable of extending the C<sub>L</sub>-drivability up to 1nF, however, at the cost of penalizing the power (426μW) and area (0.14mm<sup>2</sup>). Although recent works [3-4] have enhanced gain-bandwidth product (GBW) and slew rate (SR) showing better FOM<sub>S</sub> (=GBW·C<sub>L</sub>/Power) and FOM<sub>L</sub> (=SR·C<sub>L</sub>/Power), the C<sub>L</sub>-drivability has not been improved (i.e., 0.8nF in [3] and 0.15nF in [4]). This paper describes a three-stage amplifier managed to afford particularly large and wide range of C<sub>L</sub> (1 to 15nF) with optimized power (144μW) and die size (0.016mm<sup>2</sup>), being very suitable for compact LCD drivers [5] with different resolution targets. The design barriers are methodically surmounted via local feedback loop (LFL) analysis expanded from [6], which is an insightful control-centric method. Measured at 15nF C<sub>L</sub>, the attained FOM<sub>S</sub> (FOM<sub>L</sub>) is >;4.48× (>;2.55×) beyond that of the state-of-the-art (Fig. 21.6.1).","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124040801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176936
A. Ghaffari, E. Klumperink, B. Nauta
The huge growth of the number of wireless devices makes wireless coexistence an increasingly relevant issue. If radios operate in close proximity, blockers as strong as 0dBm may occur, driving almost any receiver in compression (note that 0dBm in 50Ω corresponds to a peak-to-peak voltage of half a 1.2V supply). Thus RF blocker filtering is highly wanted. However, fixed filters are undesired when aiming for multiband, software-defined or cognitive radio transceivers. Passive LC filters show limited Q and tunability. Recently frequency translated filtering has been proposed as a potential solution direction for high-Q filtering. We showed that by applying the “N-path concept”, more than a decade of center frequency range with good linearity, compression point (P1dB>;0dBm, IIP3 >;14dBm) and low noise is feasible for a bandpass (BP) filter. A notch filter with a combination of active and passive mixers is applied in a feedforward path realizing a BP filter. The low input impedance of a transimpedance amplifier with feedback is upconverted to create a notch filter at low frequencies (80MHz) suppressing TX leakage in an FDD system. In this work we explore the possibility to realize a notch filter applying the N-path concept at RF frequencies and in a completely passive way. A single-ended (SE) and a differential 8-path notch filter with passive frequency mixing are presented. The filters are power-matched in the input and output in the passband and provide a low insertion loss, high compression point and also low noise property, thus they can be utilized in front of a receiver to provide rejection of high-power blockers with a large frequency tuning range.
{"title":"8-Path tunable RF notch filters for blocker suppression","authors":"A. Ghaffari, E. Klumperink, B. Nauta","doi":"10.1109/ISSCC.2012.6176936","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176936","url":null,"abstract":"The huge growth of the number of wireless devices makes wireless coexistence an increasingly relevant issue. If radios operate in close proximity, blockers as strong as 0dBm may occur, driving almost any receiver in compression (note that 0dBm in 50Ω corresponds to a peak-to-peak voltage of half a 1.2V supply). Thus RF blocker filtering is highly wanted. However, fixed filters are undesired when aiming for multiband, software-defined or cognitive radio transceivers. Passive LC filters show limited Q and tunability. Recently frequency translated filtering has been proposed as a potential solution direction for high-Q filtering. We showed that by applying the “N-path concept”, more than a decade of center frequency range with good linearity, compression point (P1dB>;0dBm, IIP3 >;14dBm) and low noise is feasible for a bandpass (BP) filter. A notch filter with a combination of active and passive mixers is applied in a feedforward path realizing a BP filter. The low input impedance of a transimpedance amplifier with feedback is upconverted to create a notch filter at low frequencies (80MHz) suppressing TX leakage in an FDD system. In this work we explore the possibility to realize a notch filter applying the N-path concept at RF frequencies and in a completely passive way. A single-ended (SE) and a differential 8-path notch filter with passive frequency mixing are presented. The filters are power-matched in the input and output in the passband and provide a low insertion loss, high compression point and also low noise property, thus they can be utilized in front of a receiver to provide rejection of high-power blockers with a large frequency tuning range.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128336532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176950
K. Kaviani, A. Amirkhany, Charlie Huang, P. Le, C. Madden, Keisuke Saito, Koji Sano, V. Murugan, W. Beyene, Ken Chang, Xingchao Yuan
The growing demand for low-power and high-fidelity chip-to-chip data communication has motivated the use of near-ground or low-common-mode voltage (LCM) signaling [1-2]. However, deployment of such signaling for high-speed applications such as graphics memory interfaces has been hampered by complications of the transmitter and receiver designs. Recent techniques have enhanced the performance of source-series terminated transmitters by accommodating impedance and equalization calibration at a low power cost [3]. This work advances LCM receiver high-frequency operation by introducing an accurate termination calibration, taking into account the receiver loading on the data link channel. Our receiver also incorporates common-mode-to-differential-gain cancellation and in-situ equalization calibration for reliable data reception at 16Gb/s over a 3” FR4 PCB memory link with 15dB loss at Nyquist frequency.
{"title":"A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration","authors":"K. Kaviani, A. Amirkhany, Charlie Huang, P. Le, C. Madden, Keisuke Saito, Koji Sano, V. Murugan, W. Beyene, Ken Chang, Xingchao Yuan","doi":"10.1109/ISSCC.2012.6176950","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176950","url":null,"abstract":"The growing demand for low-power and high-fidelity chip-to-chip data communication has motivated the use of near-ground or low-common-mode voltage (LCM) signaling [1-2]. However, deployment of such signaling for high-speed applications such as graphics memory interfaces has been hampered by complications of the transmitter and receiver designs. Recent techniques have enhanced the performance of source-series terminated transmitters by accommodating impedance and equalization calibration at a low power cost [3]. This work advances LCM receiver high-frequency operation by introducing an accurate termination calibration, taking into account the receiver loading on the data link channel. Our receiver also incorporates common-mode-to-differential-gain cancellation and in-situ equalization calibration for reliable data reception at 16Gb/s over a 3” FR4 PCB memory link with 15dB loss at Nyquist frequency.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128638725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176902
D. Walter, S. Höppner, H. Eisenreich, G. Ellguth, S. Henker, Stefan Hänzsche, R. Schüffny, M. Winter, G. Fettweis
While continued scaling of feature sizes allows for an ever increasing number of cores in modern MPSoCs, power reduction and meeting on-chip bandwidth requirements are pressing concerns. Energy efficiency can be increased by per-core dynamic voltage and frequency scaling (DVFS) and by employing a globally-asynchronous, locally-synchronous (GALS) system architecture in which distribution of a synchronous high-speed clock is not required. For global on-chip communication this presents major challenges due to the need for reliable data synchronization, high bandwidth requirements and speed limiting RC effects on long wires. It has been shown recently that low-swing differential on-chip links provide highest bandwidth, low energy-per-bit and uninterrupted transfers over lengths up to 10mm [1-3, 6]. Capacitively-driven links are promising because of their built-in pre-emphasis thereby countervailing the low-pass behavior of long on-chip wires [1, 4-5]. However, all of these existing implementations focus mainly on the transmission line itself. The capacitively-driven links are not able to forward a stoppable clock signal as there is no well defined differential DC level on the wires with no data or clock activity. In addition, clocking is not reported [5] or fully synchronous, which means a high-speed clock must be distributed globally on-chip. This work provides a solution for capacitively-driven links with a parallel DC resistive divider to allow forwarded clocking with complete gating capability.
{"title":"A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS","authors":"D. Walter, S. Höppner, H. Eisenreich, G. Ellguth, S. Henker, Stefan Hänzsche, R. Schüffny, M. Winter, G. Fettweis","doi":"10.1109/ISSCC.2012.6176902","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176902","url":null,"abstract":"While continued scaling of feature sizes allows for an ever increasing number of cores in modern MPSoCs, power reduction and meeting on-chip bandwidth requirements are pressing concerns. Energy efficiency can be increased by per-core dynamic voltage and frequency scaling (DVFS) and by employing a globally-asynchronous, locally-synchronous (GALS) system architecture in which distribution of a synchronous high-speed clock is not required. For global on-chip communication this presents major challenges due to the need for reliable data synchronization, high bandwidth requirements and speed limiting RC effects on long wires. It has been shown recently that low-swing differential on-chip links provide highest bandwidth, low energy-per-bit and uninterrupted transfers over lengths up to 10mm [1-3, 6]. Capacitively-driven links are promising because of their built-in pre-emphasis thereby countervailing the low-pass behavior of long on-chip wires [1, 4-5]. However, all of these existing implementations focus mainly on the transmission line itself. The capacitively-driven links are not able to forward a stoppable clock signal as there is no well defined differential DC level on the wires with no data or clock activity. In addition, clocking is not reported [5] or fully synchronous, which means a high-speed clock must be distributed globally on-chip. This work provides a solution for capacitively-driven links with a parallel DC resistive divider to allow forwarded clocking with complete gating capability.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129091030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176930
E. Harari
In the past two decades Flash memory grew from a novelty technology to a powerful disruptor that has profoundly transformed consumer electronics and mobile computing. This was made possible through relentless cost reductions leveraging technology scaling through 19 generations of Flash memory in just 24 years, outpacing Moore's Law. NAND Flash, System-Flash, and multilevel cells (MLC) were critical elements in establishing the foundations for today's $25 billion Flash industry. Flash enabled, and in turn benefitted from new mega markets in digital consumer electronics, and more recently, from the ascendency of mobile phones and tablets as the ultimate convergence device for billions of consumers worldwide. The author began working in the semiconductor industry in the early 1970s and participated in the growth of the non volatile memory (NVM) industry [1], first as a device physicist, then as an entrepreneur and businessman. Section 2 of this paper provides the author's personal recollections of the key milestones and innovation breakthroughs that made Flash memory such a game changer. Section 3 describes the enormous impact that Flash memory has had on Consumer Electronics and Mobile Computing. Section 4 discusses some of the major challenges and opportunities ahead for the Flash industry.
{"title":"Flash memory — The great disruptor!","authors":"E. Harari","doi":"10.1109/ISSCC.2012.6176930","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176930","url":null,"abstract":"In the past two decades Flash memory grew from a novelty technology to a powerful disruptor that has profoundly transformed consumer electronics and mobile computing. This was made possible through relentless cost reductions leveraging technology scaling through 19 generations of Flash memory in just 24 years, outpacing Moore's Law. NAND Flash, System-Flash, and multilevel cells (MLC) were critical elements in establishing the foundations for today's $25 billion Flash industry. Flash enabled, and in turn benefitted from new mega markets in digital consumer electronics, and more recently, from the ascendency of mobile phones and tablets as the ultimate convergence device for billions of consumers worldwide. The author began working in the semiconductor industry in the early 1970s and participated in the growth of the non volatile memory (NVM) industry [1], first as a device physicist, then as an entrepreneur and businessman. Section 2 of this paper provides the author's personal recollections of the key milestones and innovation breakthroughs that made Flash memory such a game changer. Section 3 describes the enormous impact that Flash memory has had on Consumer Electronics and Mobile Computing. Section 4 discusses some of the major challenges and opportunities ahead for the Flash industry.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125681140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176875
Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, N. Miura, H. Ishikuro, T. Kuroda
As computing power and speed increases, the demand for higher memory bandwidth increases as well. Recently, the memory interface has been improved up to 20Gb/s/link [1]. Considering PCB routing area, a multi-drop bus architecture is still preferable for large memory capacity to the point-to-point connection. However, the multi-drop approach suffers from performance degradations due to reflections at each stub. To mitigate this problem, reference [2] proposes an impedance-matched bidirectional multi-drop DQ bus architecture that is difficult to realize due to smaller series resistor if more than 4 modules are used. To avoid multi-reflections from each stub, other approaches have used coupled transmission lines (CTL) [3, 4]. While a horizontal directional coupler buried in the PCB was used [3], coupled traces on the bent loop of flex fixed to a module were used for signal delivery in vertical direction [4]. In [3], a long coupler with long main bus line was used so that the signal integrity degrades at the far-end coupler. In [4], the coupling traces on the motherboard and the flex have zigzag geometries for better misalignment tolerance, which result in large area of routing due to the minimum required pitch between traces. In [5], the CTL needs to be placed close to a Tx/Rx chip, as there are no extended transmission lines for signal lead. Therefore, it cannot be used for memory modules. DRAM multi-drop bus interface technology mapping is described in Fig. 2.8.1.
{"title":"A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line","authors":"Won-Joo Yun, Shinya Nakano, Wataru Mizuhara, Atsutake Kosuge, N. Miura, H. Ishikuro, T. Kuroda","doi":"10.1109/ISSCC.2012.6176875","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176875","url":null,"abstract":"As computing power and speed increases, the demand for higher memory bandwidth increases as well. Recently, the memory interface has been improved up to 20Gb/s/link [1]. Considering PCB routing area, a multi-drop bus architecture is still preferable for large memory capacity to the point-to-point connection. However, the multi-drop approach suffers from performance degradations due to reflections at each stub. To mitigate this problem, reference [2] proposes an impedance-matched bidirectional multi-drop DQ bus architecture that is difficult to realize due to smaller series resistor if more than 4 modules are used. To avoid multi-reflections from each stub, other approaches have used coupled transmission lines (CTL) [3, 4]. While a horizontal directional coupler buried in the PCB was used [3], coupled traces on the bent loop of flex fixed to a module were used for signal delivery in vertical direction [4]. In [3], a long coupler with long main bus line was used so that the signal integrity degrades at the far-end coupler. In [4], the coupling traces on the motherboard and the flex have zigzag geometries for better misalignment tolerance, which result in large area of routing due to the minimum required pitch between traces. In [5], the CTL needs to be placed close to a Tx/Rx chip, as there are no extended transmission lines for signal lead. Therefore, it cannot be used for memory modules. DRAM multi-drop bus interface technology mapping is described in Fig. 2.8.1.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126960246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176980
Se-Hyun Yang, Seogjun Lee, Jae Young Lee, J. Cho, Hoi-Jin Lee, D. Cho, Junghun Heo, Sung-Yong Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, S. Hwang
Samsung's next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.
{"title":"A 32nm high-k metal gate application processor with GHz multi-core CPU","authors":"Se-Hyun Yang, Seogjun Lee, Jae Young Lee, J. Cho, Hoi-Jin Lee, D. Cho, Junghun Heo, Sung-Yong Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae-Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, S. Hwang","doi":"10.1109/ISSCC.2012.6176980","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176980","url":null,"abstract":"Samsung's next-generation 32nm dual/quad-core Exynos™ processor integrates 2 or 4 ARM-v7A architecture cores, a 2-port DRAM controller and numerous multimedia accelerators and connectivity blocks on the same die. It is an application processor (AP) designed to cover a wide variety of mobile applications and handle unprecedented data-processing throughput and multimedia performance, without sacrificing the battery life or exceeding the thermal power dissipation envelope. The architecture diagram is shown in Fig. 12.1.1 and the die photo for the quad-core configuration is shown in Fig. 12.1.7.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126357360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177022
A. Wong, M. Dawkins, Gabriele Devita, Nick Kasparidis, A. Katsiamis, Oliver King, Franco Lauria, J. Schiff, A. Burdett
In recent years there has been significant interest and growth in low-power wireless technologies beyond traditional consumer use cases into medical applications [1]. Previously a bastion for application specific wireless propriety protocols, the WBAN community has worked together to develop a communication standard IEEE802.15.6 optimised for low power devices in and around the human body offering the levels of QoS required for personal medical data. Additionally, the consumer electronic industry has migrated existing standardised wireless protocols such as Bluetooth to meet the demanding low energy yet robust needs of WBAN. This paper presents a transceiver chip for both IEEE802.15.6 Narrow-Band (NB) PHY draft [2] and Bluetooth Low Energy (LE) 4.0 standards as well as proprietary protocols. Multi-mode operation offers the best solution in terms of flexibility and interoperability between devices and networks, and the appropriate protocol can be chosen to optimise power consumption in numerous applications scenarios where data throughput varies dramatically; such as streaming multi-lead ECG or episodic temperature measurements. The chip operates in the 2.36GHz MBANs spectrum, specifically allocated for medical devices, and the worldwide 2.4GHz ISM band. A TX for the 780/868/915/950MHz licence-free bands in China, EU, North America and Japan respectively, is also included. The chip is architected and designed for 5mW peak active power dissipation for compatibility with 1V button cells, hence enabling small-form factor non-intrusive body worn applications.
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