Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177032
M. Harwood, S. Nielsen, A. Szczepanek, Richard Allred, Sean Batty, M. Case, S. Forey, K. Gopalakrishnan, Larry Kan, B. Killips, Parmanand Mishra, Rohit Pande, H. Rategh, A. Ren, Jeff Sanders, A. Schoy, Richard Ward, Martin Wetterhorn, N. Yeung
A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches . This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2.
{"title":"A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications","authors":"M. Harwood, S. Nielsen, A. Szczepanek, Richard Allred, Sean Batty, M. Case, S. Forey, K. Gopalakrishnan, Larry Kan, B. Killips, Parmanand Mishra, Rohit Pande, H. Rategh, A. Ren, Jeff Sanders, A. Schoy, Richard Ward, Martin Wetterhorn, N. Yeung","doi":"10.1109/ISSCC.2012.6177032","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177032","url":null,"abstract":"A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches . This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125513878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177110
J. Hurwitz, J. Savoj
Sometimes a new technology or technique comes along that is just plain different to the incumbent solutions or conventional approaches. They can often take a while to make their mark, as the conventional state of the art keeps moving, or there is resistance to change because of the exotic nature of the solution being offered, or the crossover condition in the market for the technology to be justified has not yet been reached. This session looks at a number of ideas that are currently asking us to re-assess the way things are done. The five talks in this session cover the following topics: MEMS; thermal diffusivity sensor; VCO-based quantizer; continuous time DSP; and analog synthesis.
{"title":"Technologies that could change the world — You decide!","authors":"J. Hurwitz, J. Savoj","doi":"10.1109/ISSCC.2012.6177110","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177110","url":null,"abstract":"Sometimes a new technology or technique comes along that is just plain different to the incumbent solutions or conventional approaches. They can often take a while to make their mark, as the conventional state of the art keeps moving, or there is resistance to change because of the exotic nature of the solution being offered, or the crossover condition in the market for the technology to be justified has not yet been reached. This session looks at a number of ideas that are currently asking us to re-assess the way things are done. The five talks in this session cover the following topics: MEMS; thermal diffusivity sensor; VCO-based quantizer; continuous time DSP; and analog synthesis.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116795057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177105
R. Pawlowski, Evgeni Krimer, Joseph Crop, J. Postman, N. M. Madani, M. Erez, P. Chiang
Near-threshold computing exhibits improved energy efficiency compared to nominal super-threshold operation [1, 2]. Two critical bottlenecks prevent mainstream adoption of low-VDD operation: degraded logic delay resulting in significantly lower throughput than at super-threshold, and excessive, unpredictable delay variation caused by increased sensitivity to process and dynamic variations.
{"title":"A 530mV 10-lane SIMD processor with variation resiliency in 45nm SOI","authors":"R. Pawlowski, Evgeni Krimer, Joseph Crop, J. Postman, N. M. Madani, M. Erez, P. Chiang","doi":"10.1109/ISSCC.2012.6177105","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177105","url":null,"abstract":"Near-threshold computing exhibits improved energy efficiency compared to nominal super-threshold operation [1, 2]. Two critical bottlenecks prevent mainstream adoption of low-VDD operation: degraded logic delay resulting in significantly lower throughput than at super-threshold, and excessive, unpredictable delay variation caused by increased sensitivity to process and dynamic variations.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116981652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177039
F. Opteynde
Bang-Bang all-digital PLLs [1] for applications such as digital clock multiplication have existed for a long time, but show limited phase noise performance. Pioneering recent work [2-5] has demonstrated frequency synthesizers that meet the performance requirements of wireless communications systems, while containing no analog circuits except for an LC-oscillator. In order to build an All-Digital Phase-Locked Loop (ADPLL), it is necessary to measure the oscillator's momentary phase accurately, in a digital way, since the output phase noise at frequencies within the PLL loop bandwidth is ultimately limited by the time quantisation step Δt of this phase measurement [6]: L=20.log10 (Δt·ωosc/√12·√fsample) [dBc/Hz] (1) In [2-5], a Time-to-Digital Converter (TDC) is used to measure the oscillator's phase with a resolution of a single inverter delay. However, this approach requires calibration of the TDC conversion gain. Previous work [2] included a small microprocessor incorporated in the PLL circuit, to perform all necessary calculations related to the calibration. Obviously, this renders the circuit complex, is prone to calibration errors and consumes power and area. In this paper, an alternative approach is presented, allowing all-digital frequency synthesizers that meet the requirements for wireless communications standards, that benefit from the benign scaling properties, porting properties, process independence and controlled design flow, inherent to digital circuits, but that, on the other hand, do not require the burden of calibration and associated calculations.
{"title":"A 40nm CMOS all-digital fractional-N synthesizer without requiring calibration","authors":"F. Opteynde","doi":"10.1109/ISSCC.2012.6177039","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177039","url":null,"abstract":"Bang-Bang all-digital PLLs [1] for applications such as digital clock multiplication have existed for a long time, but show limited phase noise performance. Pioneering recent work [2-5] has demonstrated frequency synthesizers that meet the performance requirements of wireless communications systems, while containing no analog circuits except for an LC-oscillator. In order to build an All-Digital Phase-Locked Loop (ADPLL), it is necessary to measure the oscillator's momentary phase accurately, in a digital way, since the output phase noise at frequencies within the PLL loop bandwidth is ultimately limited by the time quantisation step Δt of this phase measurement [6]: L=20.log10 (Δt·ωosc/√12·√fsample) [dBc/Hz] (1) In [2-5], a Time-to-Digital Converter (TDC) is used to measure the oscillator's phase with a resolution of a single inverter delay. However, this approach requires calibration of the TDC conversion gain. Previous work [2] included a small microprocessor incorporated in the PLL circuit, to perform all necessary calculations related to the calibration. Obviously, this renders the circuit complex, is prone to calibration errors and consumes power and area. In this paper, an alternative approach is presented, allowing all-digital frequency synthesizers that meet the requirements for wireless communications standards, that benefit from the benign scaling properties, porting properties, process independence and controlled design flow, inherent to digital circuits, but that, on the other hand, do not require the burden of calibration and associated calculations.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131148390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177088
Xiongchuan Huang, A. Ba, P. Harpe, G. Dolmans, H. D. Groot, J. Long
Minimizing the power consumption while maintaining performance is paramount in radio transceiver design for low-power wireless sensor network (WSN) applications. Given a sub-mW power budget, many radios have utilized amplitude modulation and envelope detection to eliminate the need for accurate frequency references and to reduce power consumption [1-4]. However, such radios suffer from poor frequency selectivity. They rely on front-end filters to reject out-of-band interference, while in-band interferers still corrupt the desired signal.
{"title":"A 915MHz 120μW-RX/900μW-TX envelope-detection transceiver with 20dB in-band interference tolerance","authors":"Xiongchuan Huang, A. Ba, P. Harpe, G. Dolmans, H. D. Groot, J. Long","doi":"10.1109/ISSCC.2012.6177088","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177088","url":null,"abstract":"Minimizing the power consumption while maintaining performance is paramount in radio transceiver design for low-power wireless sensor network (WSN) applications. Given a sub-mW power budget, many radios have utilized amplitude modulation and envelope detection to eliminate the need for accurate frequency references and to reduce power consumption [1-4]. However, such radios suffer from poor frequency selectivity. They rely on front-end filters to reject out-of-band interference, while in-band interferers still corrupt the desired signal.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132221060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177068
T. Gupta, Frank Yang, Dong Wang, A. Tabatabaei, Ramesh Singh, H. A. Aslanzadeh, Alireza Khalili, S. Vats, S. Arno, S. Campeau
The IEEE802.3an 10GBase-T standard [1] provides full duplex transmission and reception over 4 twisted pairs in a 100M UTP cable. Earlier AFE implementations for this standard have utilized a transmitter hybrid configuration requiring multiple DACs with stringent inter-DAC matching requirements [2-3]. This paper describes a new AFE architecture using a single DAC and line-driver to achieve better echo-cancellation linearity. The design achieves >;59dB TX SFDR and >;68dB echo-cancellation (EC) SFDR across 400MHz bandwidth. The AFE receiver circuitry consists of PGA and 2× time-interleaved SHA-less 11b pipelined ADC operating at 800MS/s. Measured receive noise floor and SFDR is <;-144dBm/Hz and >;53dB, respectively. The AFE dissipates less than 2W power, occupies 17mm2 silicon area including 4 lanes with clocking circuitry, and is implemented in a 40nm triple-gate 0.9V/1.2V/2.5V CMOS process.
{"title":"A sub-2W 10GBase-T analog front-end in 40nm CMOS process","authors":"T. Gupta, Frank Yang, Dong Wang, A. Tabatabaei, Ramesh Singh, H. A. Aslanzadeh, Alireza Khalili, S. Vats, S. Arno, S. Campeau","doi":"10.1109/ISSCC.2012.6177068","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177068","url":null,"abstract":"The IEEE802.3an 10GBase-T standard [1] provides full duplex transmission and reception over 4 twisted pairs in a 100M UTP cable. Earlier AFE implementations for this standard have utilized a transmitter hybrid configuration requiring multiple DACs with stringent inter-DAC matching requirements [2-3]. This paper describes a new AFE architecture using a single DAC and line-driver to achieve better echo-cancellation linearity. The design achieves >;59dB TX SFDR and >;68dB echo-cancellation (EC) SFDR across 400MHz bandwidth. The AFE receiver circuitry consists of PGA and 2× time-interleaved SHA-less 11b pipelined ADC operating at 800MS/s. Measured receive noise floor and SFDR is <;-144dBm/Hz and >;53dB, respectively. The AFE dissipates less than 2W power, occupies 17mm2 silicon area including 4 lanes with clocking circuitry, and is implemented in a 40nm triple-gate 0.9V/1.2V/2.5V CMOS process.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133119152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176934
Yee William Li, C. Ornelas, Hyung Seok Kim, H. Lakdawala, A. Ravi, K. Soumyanath
Diverse spread spectrum clocking (SSC) generation requirements necessitate multiple reference clocks, extra pins, and off-chip components. With analog integer-n PLL-based clock generators, it is difficult to meet all these needs with a common reference clock. One disadvantage is that the frequency resolution in an integer-n PLL is limited by the reference frequency. A lower reference frequency limits the bandwidth and lock time, amplifies jitter from the reference, and increases the loop filter area. Additionally, analog PLLs suffer from unpredictable loop dynamics and clock skews with PVT, mismatch, and transistor leakage, further exacerbated by process scaling. Turning off and waking up an analog PLL requires charging or discharging loop filter capacitors which is inherently slow. This paper presents an all-digital clock generation architecture which (1) provides fractional-n capability in the digital domain; (2) implements SSC within the PLL loop; (3) performs digital clock deskew; and (4) provides dynamic loop bandwidth adjustment to shorten lock time.
{"title":"A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS","authors":"Yee William Li, C. Ornelas, Hyung Seok Kim, H. Lakdawala, A. Ravi, K. Soumyanath","doi":"10.1109/ISSCC.2012.6176934","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176934","url":null,"abstract":"Diverse spread spectrum clocking (SSC) generation requirements necessitate multiple reference clocks, extra pins, and off-chip components. With analog integer-n PLL-based clock generators, it is difficult to meet all these needs with a common reference clock. One disadvantage is that the frequency resolution in an integer-n PLL is limited by the reference frequency. A lower reference frequency limits the bandwidth and lock time, amplifies jitter from the reference, and increases the loop filter area. Additionally, analog PLLs suffer from unpredictable loop dynamics and clock skews with PVT, mismatch, and transistor leakage, further exacerbated by process scaling. Turning off and waking up an analog PLL requires charging or discharging loop filter capacitors which is inherently slow. This paper presents an all-digital clock generation architecture which (1) provides fractional-n capability in the digital domain; (2) implements SSC within the PLL loop; (3) performs digital clock deskew; and (4) provides dynamic loop bandwidth adjustment to shorten lock time.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131777375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176984
Yasuki Tanabe, M. Sumiyoshi, Manabu Nishiyama, I. Yamazaki, Shinsuke Fujii, K. Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, T. Miyamori
The use of image recognition technologies is becoming more popular recently in a variety of industries such as automotive, surveillance, and others. SoCs for such image recognition applications are required to be powerful enough to support real-time multiple object recognition, with power consumption not exceeding a few Watts. Adaptability to a range of applications is also desirable. In this context, massively parallel processors and heterogeneous many-core processors with 200GOPS have been proposed. However, rising demands for simultaneous execution of multiple applications leads to even higher performance requirements. In advanced driver-assistance systems for automotive, for example, forward collision warning and traffic sign recognition should execute simultaneously to improve safety of the system. In addition, the accuracy of recognition is also important. With its high accuracy (96% detection rate/0.1% false-positive rate), object recognition using co-occurrence histograms of oriented gradients (CoHOG) is a promising algorithm. However, the algorithm requires an extensive amount of computation. For example, a desktop computer with a 3GHz quad-core processor is needed for CoHOG-based pedestrian detection in a backover prevention (BOP) application. Considering these requirements, we have developed an image recognition SoC with the following features: 1) a multi-core processor to provide adaptability to various applications; 2) accelerators for image processing tasks and image recognition tasks to realize high performance at low power consumption; and, 3) a hardware accelerator for a CoHOG based real-time recognition.
{"title":"A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications","authors":"Yasuki Tanabe, M. Sumiyoshi, Manabu Nishiyama, I. Yamazaki, Shinsuke Fujii, K. Kimura, Takuma Aoyama, Moriyasu Banno, Hiroo Hayashi, T. Miyamori","doi":"10.1109/ISSCC.2012.6176984","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176984","url":null,"abstract":"The use of image recognition technologies is becoming more popular recently in a variety of industries such as automotive, surveillance, and others. SoCs for such image recognition applications are required to be powerful enough to support real-time multiple object recognition, with power consumption not exceeding a few Watts. Adaptability to a range of applications is also desirable. In this context, massively parallel processors and heterogeneous many-core processors with 200GOPS have been proposed. However, rising demands for simultaneous execution of multiple applications leads to even higher performance requirements. In advanced driver-assistance systems for automotive, for example, forward collision warning and traffic sign recognition should execute simultaneously to improve safety of the system. In addition, the accuracy of recognition is also important. With its high accuracy (96% detection rate/0.1% false-positive rate), object recognition using co-occurrence histograms of oriented gradients (CoHOG) is a promising algorithm. However, the algorithm requires an extensive amount of computation. For example, a desktop computer with a 3GHz quad-core processor is needed for CoHOG-based pedestrian detection in a backover prevention (BOP) application. Considering these requirements, we have developed an image recognition SoC with the following features: 1) a multi-core processor to provide adaptability to various applications; 2) accelerators for image processing tasks and image recognition tasks to realize high performance at low power consumption; and, 3) a hardware accelerator for a CoHOG based real-time recognition.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"221 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113958952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177015
P. Malcovati, M. Belloni, F. Gozzini, Cristiano Bazzani, A. Baschirotto
Several emerging portable applications require high-efficiency LED drivers [1-4]. An LED driver is basically a current source that forces the current required for achieving the desired light emission into the LED. In order to increase the LED driver efficiency, besides controlling the LED current, it is necessary to regulate the voltage applied to the LED itself, to minimize the voltage drop across the driver current source and, hence, the power consumption. Depending on the kind of LED and on the current forced through the LED itself (0.1 to 2A in this design) and, hence, on the desired light emission, the voltage required to drive the LED, while maintaining the voltage headroom across the driver current source to the minimum, varies over a wide range (0 to 5V). Starting from a standard voltage supply in the range 2.7 to 5.5V, a buck-boost DC-DC converter is then required (Fig. 16.4.1). The buck-boost DC-DC converter includes the LED in the control feedback loop and has to provide fast turn-on and load transients (on the order of 20μs), in order to allow pulsed operation of the LED itself.
{"title":"A 0.18μm CMOS 91%-efficiency 0.1-to-2A scalable buck-boost DC-DC converter for LED drivers","authors":"P. Malcovati, M. Belloni, F. Gozzini, Cristiano Bazzani, A. Baschirotto","doi":"10.1109/ISSCC.2012.6177015","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177015","url":null,"abstract":"Several emerging portable applications require high-efficiency LED drivers [1-4]. An LED driver is basically a current source that forces the current required for achieving the desired light emission into the LED. In order to increase the LED driver efficiency, besides controlling the LED current, it is necessary to regulate the voltage applied to the LED itself, to minimize the voltage drop across the driver current source and, hence, the power consumption. Depending on the kind of LED and on the current forced through the LED itself (0.1 to 2A in this design) and, hence, on the desired light emission, the voltage required to drive the LED, while maintaining the voltage headroom across the driver current source to the minimum, varies over a wide range (0 to 5V). Starting from a standard voltage supply in the range 2.7 to 5.5V, a buck-boost DC-DC converter is then required (Fig. 16.4.1). The buck-boost DC-DC converter includes the LED in the control feedback loop and has to provide fast turn-on and load transients (on the order of 20μs), in order to allow pulsed operation of the LED itself.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122361134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177021
Kiseok Song, Hyungwoo Lee, Sunjoo Hong, Hyunwoo Cho, H. Yoo
Electro-acupuncture (EA), a combination of acupuncture and electrical stimulation, has been widely used for its effectiveness in pain relief since the 1970s [1] and later for treatment of various diseases such as depression, addiction, and gastrointestinal disorders [2], and non-medical applications including obesity treatment [3]. For stimulation, most EA systems use a pair of needles with long, thick wires connected to an external power supply to form a closed current loop. The thin (φ=2mm) needle may suffer from the inconvenient and unstable connection to the thick wire and if there are many needles, it is difficult to supply power to all needles [4]. Recently, a wirelessly-powered EA system was proposed in [4] to remove the wire connections for convenient treatment, but its wireless power harvesting generated only 8μW which is not enough for various applications [1-3]. Most EA systems use bi-phase stimulation to reduce tissue damage, electrolysis, and electrolytic degradation [5]. However, the high-precision balancing of a bi-phase current pulse is difficult to achieve because the required offset, <;10nA [6], is only on the order of 10<;sup>;-5<;/sup>; of the stimulation current level, ~1mA. Furthermore, none of the previous EA systems have any feedback mechanism to enable adaptive stimulation by showing the real-time status of the EA stimulation to the patient.
{"title":"A sub-10nA DC-balanced adaptive stimulator IC with multimodal sensor for compact electro-acupuncture system","authors":"Kiseok Song, Hyungwoo Lee, Sunjoo Hong, Hyunwoo Cho, H. Yoo","doi":"10.1109/ISSCC.2012.6177021","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177021","url":null,"abstract":"Electro-acupuncture (EA), a combination of acupuncture and electrical stimulation, has been widely used for its effectiveness in pain relief since the 1970s [1] and later for treatment of various diseases such as depression, addiction, and gastrointestinal disorders [2], and non-medical applications including obesity treatment [3]. For stimulation, most EA systems use a pair of needles with long, thick wires connected to an external power supply to form a closed current loop. The thin (φ=2mm) needle may suffer from the inconvenient and unstable connection to the thick wire and if there are many needles, it is difficult to supply power to all needles [4]. Recently, a wirelessly-powered EA system was proposed in [4] to remove the wire connections for convenient treatment, but its wireless power harvesting generated only 8μW which is not enough for various applications [1-3]. Most EA systems use bi-phase stimulation to reduce tissue damage, electrolysis, and electrolytic degradation [5]. However, the high-precision balancing of a bi-phase current pulse is difficult to achieve because the required offset, <;10nA [6], is only on the order of 10<;sup>;-5<;/sup>; of the stimulation current level, ~1mA. Furthermore, none of the previous EA systems have any feedback mechanism to enable adaptive stimulation by showing the real-time status of the EA stimulation to the patient.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"618 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122695169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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