Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177033
D. Crivelli, M. Hueda, H. Carrer, Jeff Zachan, V. Gutnik, Martin Del Barco, Ramiro R. Lopez, G. Hatcher, J. Finochietto, Michael Yeo, Andre Chartrand, N. Swenson, P. Voois, O. Agazzi
Optical communication technology in long-haul and metropolitan links is experiencing a transition to coherent techniques and high spectral efficiency modulation formats such as dual-polarization (DP) QPSK, DP-QAM and OFDM. The combination of coherent demodulation and DSP allows costly optical signal-processing hardware used to compensate fiber optic impairments such as chromatic dispersion (CD) and polarization-mode dispersion (PMD) to be replaced by DSP-based techniques [1]. Economic large-scale deployment of coherent systems requires the integration of the optical transceiver functions in CMOS technology.
{"title":"A 40nm CMOS single-chip 50Gb/s DP-QPSK/BPSK transceiver with electronic dispersion compensation for coherent optical channels","authors":"D. Crivelli, M. Hueda, H. Carrer, Jeff Zachan, V. Gutnik, Martin Del Barco, Ramiro R. Lopez, G. Hatcher, J. Finochietto, Michael Yeo, Andre Chartrand, N. Swenson, P. Voois, O. Agazzi","doi":"10.1109/ISSCC.2012.6177033","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177033","url":null,"abstract":"Optical communication technology in long-haul and metropolitan links is experiencing a transition to coherent techniques and high spectral efficiency modulation formats such as dual-polarization (DP) QPSK, DP-QAM and OFDM. The combination of coherent demodulation and DSP allows costly optical signal-processing hardware used to compensate fiber optic impairments such as chromatic dispersion (CD) and polarization-mode dispersion (PMD) to be replaced by DSP-based techniques [1]. Economic large-scale deployment of coherent systems requires the integration of the optical transceiver functions in CMOS technology.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123006580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177029
A. Tang, F. Hsiao, D. Murphy, I-Ning Ku, J. Liu, Sandeep D'Souza, N. Wang, Hao Wu, Yen-Hsiang Wang, Mandy Tang, G. Virbila, Mike Pham, Derek Yang, Q. Gu, Yi-Cheng Wu, Yen-Cheng Kuan, C. Chien, Mau-Chung Frank Chang
The available ISM band from 57-65GHz has become attractive for high-speed wireless applications including mass data transfer, streaming high-definition video and even biomedical applications. While silicon based data transceivers at mm-wave frequencies have become increasingly mature in recent years [1,2,3], the primary focus of the circuit community remains on the design of mm-wave front-ends to achieve higher data rates through higher-order modulation and beamforming techniques. However, the sustainability of such mm-wave systems when integrated in a SoC has not been addressed in the context of die performance yield and device aging. This problem is especially challenging for the implementation of mm-wave SoC's in deep sub-micron technology due to its process & operating temperature variations and limited ft / fmax with respect to the operation frequency.
{"title":"A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip","authors":"A. Tang, F. Hsiao, D. Murphy, I-Ning Ku, J. Liu, Sandeep D'Souza, N. Wang, Hao Wu, Yen-Hsiang Wang, Mandy Tang, G. Virbila, Mike Pham, Derek Yang, Q. Gu, Yi-Cheng Wu, Yen-Cheng Kuan, C. Chien, Mau-Chung Frank Chang","doi":"10.1109/ISSCC.2012.6177029","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177029","url":null,"abstract":"The available ISM band from 57-65GHz has become attractive for high-speed wireless applications including mass data transfer, streaming high-definition video and even biomedical applications. While silicon based data transceivers at mm-wave frequencies have become increasingly mature in recent years [1,2,3], the primary focus of the circuit community remains on the design of mm-wave front-ends to achieve higher data rates through higher-order modulation and beamforming techniques. However, the sustainability of such mm-wave systems when integrated in a SoC has not been addressed in the context of die performance yield and device aging. This problem is especially challenging for the implementation of mm-wave SoC's in deep sub-micron technology due to its process & operating temperature variations and limited ft / fmax with respect to the operation frequency.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129183871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177113
E. Klumperink, D. Leenaerts, Gabriel M. Rebeiz
Phased arrays exploit electronic beamforming to create an electronically steerable beam pattern. This renders antenna gain in certain directions and rejection in others, i.e. spatial filtering. Until recently, phased array systems exploited dedicated RF technologies leading to relatively costly systems, e.g. for nautical, airplane radar systems, and satellite communication. More recently, low-cost highly integrated beamforming concepts received considerable interest in academia but also industry, enabling consumer applications e.g. in base-stations for macro- and femto-cells, car-radar and 60GHz wideband radio links. (Bi-)CMOS beamforming techniques are at the heart of such systems. This forum reviews beamforming techniques suitable for IC-integration, and discusses related (Bi-)CMOS transceiver designs. Several techniques will be discussed, e.g. RF phase-shifting, LO-phase shifting, I/Q Vector modulation and digital processing. Also the relation between key radar and communication system requirements and transceiver-IC requirements will be considered. Finally, trends and challenges will be discussed in a panel.
{"title":"Beamforming techniques and RF transceiver design","authors":"E. Klumperink, D. Leenaerts, Gabriel M. Rebeiz","doi":"10.1109/ISSCC.2012.6177113","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177113","url":null,"abstract":"Phased arrays exploit electronic beamforming to create an electronically steerable beam pattern. This renders antenna gain in certain directions and rejection in others, i.e. spatial filtering. Until recently, phased array systems exploited dedicated RF technologies leading to relatively costly systems, e.g. for nautical, airplane radar systems, and satellite communication. More recently, low-cost highly integrated beamforming concepts received considerable interest in academia but also industry, enabling consumer applications e.g. in base-stations for macro- and femto-cells, car-radar and 60GHz wideband radio links. (Bi-)CMOS beamforming techniques are at the heart of such systems. This forum reviews beamforming techniques suitable for IC-integration, and discusses related (Bi-)CMOS transceiver designs. Several techniques will be discussed, e.g. RF phase-shifting, LO-phase shifting, I/Q Vector modulation and digital processing. Also the relation between key radar and communication system requirements and transceiver-IC requirements will be considered. Finally, trends and challenges will be discussed in a panel.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129370613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177098
Sudhir K. Satpathy, Korey Sewell, Thomas Manville, Yen-Po Chen, R. Dreslinski, D. Sylvester, T. Mudge, D. Blaauw
High-speed and low-power routers form the basic building blocks of on-die interconnect fabrics that are critical to overall throughput and energy efficiency of high performance systems. Conventional routers use distinct logic blocks for routing data and handling arbitration. At higher radices, connections between these blocks become a bottleneck, limiting router scalability and degrading performance. Recently, two switch topologies merged the data routing fabric with arbitration control, avoiding this bottleneck. However, relies on centralized control for channel allocation, limiting performance, while restricted to a small set of fixed priorities, rendering input ports prone to starvation. In addition, ever larger CMPs will require continued increases in bandwidth over previous designs. To address these issues, we present a 64x64 single-stage swizzle-switch network (SSN) with 128b data buses (8192 total input/output wires). The SSN can connect any input to any output, including multicast. It has a peak measured throughput of 4.5Tb/s at 1.1V in 45nm SOI CMOS at 25°C. The SSN's key features are: 1) a single-cycle least-recently granted (LRG) priority arbitration technique that reuses the already present input and output data buses and their drivers and sense amps; 2) an additional 4-level message-based priority arbitration for quality of service (QoS) with 2% logic and 3% wiring overhead; 3) a bidirectional bitline repeater that allows the router to scale to >;8000 wires. These features result in a compact fabric (4.06mm2) with throughput gain of 2.1 x over at 3.4Tb/s/W efficiency, which improves to 7.4Tb/s/W at 600mV.
高速和低功耗路由器构成片上互连结构的基本组成部分，对高性能系统的整体吞吐量和能源效率至关重要。传统路由器使用不同的逻辑块来路由数据和处理仲裁。在更高的基数下，这些块之间的连接成为瓶颈，限制了路由器的可扩展性并降低了性能。最近，有两种交换机拓扑将数据路由结构与仲裁控制合并，从而避免了这一瓶颈。然而，它依赖于通道分配的集中控制，限制了性能，同时限制了一小部分固定优先级，使得输入端口容易出现饥饿。此外，更大的cmp将需要比以前的设计持续增加带宽。为了解决这些问题，我们提出了一个带有128b数据总线(总共8192根输入/输出线)的64x64单级搅拌开关网络(SSN)。SSN可以将任何输入连接到任何输出，包括组播。它在25°C下，在45nm SOI CMOS中，在1.1V下的峰值测量吞吐量为4.5Tb/s。SSN的主要特点是:1)单周期最近最少授予(LRG)优先仲裁技术，重用已经存在的输入和输出数据总线及其驱动器和感测放大器;2)额外的4级基于消息的服务质量(QoS)优先级仲裁，具有2%的逻辑和3%的布线开销;3)一个双向位线中继器，允许路由器扩展到8000根线。这些特性导致结构紧凑(4.06mm2)，在3.4Tb/s/W效率下吞吐量增益为2.1倍，在600mV效率下提高到7.4Tb/s/W。
{"title":"A 4.5Tb/s 3.4Tb/s/W 64×64 switch fabric with self-updating least-recently-granted priority and quality-of-service arbitration in 45nm CMOS","authors":"Sudhir K. Satpathy, Korey Sewell, Thomas Manville, Yen-Po Chen, R. Dreslinski, D. Sylvester, T. Mudge, D. Blaauw","doi":"10.1109/ISSCC.2012.6177098","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177098","url":null,"abstract":"High-speed and low-power routers form the basic building blocks of on-die interconnect fabrics that are critical to overall throughput and energy efficiency of high performance systems. Conventional routers use distinct logic blocks for routing data and handling arbitration. At higher radices, connections between these blocks become a bottleneck, limiting router scalability and degrading performance. Recently, two switch topologies merged the data routing fabric with arbitration control, avoiding this bottleneck. However, relies on centralized control for channel allocation, limiting performance, while restricted to a small set of fixed priorities, rendering input ports prone to starvation. In addition, ever larger CMPs will require continued increases in bandwidth over previous designs. To address these issues, we present a 64x64 single-stage swizzle-switch network (SSN) with 128b data buses (8192 total input/output wires). The SSN can connect any input to any output, including multicast. It has a peak measured throughput of 4.5Tb/s at 1.1V in 45nm SOI CMOS at 25°C. The SSN's key features are: 1) a single-cycle least-recently granted (LRG) priority arbitration technique that reuses the already present input and output data buses and their drivers and sense amps; 2) an additional 4-level message-based priority arbitration for quality of service (QoS) with 2% logic and 3% wiring overhead; 3) a bidirectional bitline repeater that allows the router to scale to >;8000 wires. These features result in a compact fabric (4.06mm2) with throughput gain of 2.1 x over at 3.4Tb/s/W efficiency, which improves to 7.4Tb/s/W at 600mV.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116399369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177077
Daeyeal Lee, I. Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, ByungJun Min, Sung-Won Yun, Ji-Sang Lee, I. Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yongdeok Cho, Kyung-Min Kang, Sanghoon Joo, Jin-Young Chun, Jung-No Im, S. Kwon, Seo-Hyeon Ham, Ansoo Park, Jaemin Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, B. Jeon, Kihwan Choi, Jin-Man Han, K. Kyung, Y. Lim, Young-Hyun Jun
The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].
{"title":"A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology","authors":"Daeyeal Lee, I. Chang, Sangyong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, Doo-Gon Kim, Chiweon Yoon, Bong-Soon Lim, ByungJun Min, Sung-Won Yun, Ji-Sang Lee, I. Park, Kyung-Ryun Kim, Jeong-Yun Yun, Youse Kim, Yongdeok Cho, Kyung-Min Kang, Sanghoon Joo, Jin-Young Chun, Jung-No Im, S. Kwon, Seo-Hyeon Ham, Ansoo Park, Jaemin Yu, Nam-Hee Lee, Tae-Sung Lee, Moosung Kim, Hoosung Kim, Ki-Whan Song, B. Jeon, Kihwan Choi, Jin-Man Han, K. Kyung, Y. Lim, Young-Hyun Jun","doi":"10.1109/ISSCC.2012.6177077","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177077","url":null,"abstract":"The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116710807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176971
Hiroyuki Miyazaki, Yoshihiro Kusano, H. Okano, Tatsumi Nakada, Ken Seki, T. Shimizu, Naoki Shinjo, F. Shoji, Atsuya Uno, M. Kurokawa
Many high-performance CPUs employ a multicore architecture with a moderate clock frequency and wide instruction issue, including SIMD extensions, to achieve high performance while retaining a practical power consumption. As demand for supercomputer performance grows faster than the rate that improvements are made to CPU performance, the total number of cores of high-end supercomputers has increased tremendously. Efficient handling of large numbers of cores is a key aspect in the design of supercomputers. Building a supercomputer with lower power consumption and significant reliability is also important from the viewpoints of cost and availability.
{"title":"K computer: 8.162 PetaFLOPS massively parallel scalar supercomputer built with over 548k cores","authors":"Hiroyuki Miyazaki, Yoshihiro Kusano, H. Okano, Tatsumi Nakada, Ken Seki, T. Shimizu, Naoki Shinjo, F. Shoji, Atsuya Uno, M. Kurokawa","doi":"10.1109/ISSCC.2012.6176971","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176971","url":null,"abstract":"Many high-performance CPUs employ a multicore architecture with a moderate clock frequency and wide instruction issue, including SIMD extensions, to achieve high performance while retaining a practical power consumption. As demand for supercomputer performance grows faster than the rate that improvements are made to CPU performance, the total number of cores of high-end supercomputers has increased tremendously. Efficient handling of large numbers of cores is a key aspect in the design of supercomputers. Building a supercomputer with lower power consumption and significant reliability is also important from the viewpoints of cost and availability.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117055687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176931
Zhiyi Yu, K. You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng
Almost all multicore processors use a shared-memory architecture due to its simple programming model. Recently, however, the message-passing mechanism is also drawing attention due to its potentially better scalability. In this work, we demonstrate that a hybrid communication mechanism supporting both message passing and shared memory can provide both higher performance and energy efficiency. This 16-core processor has 3 key features: (1) A cluster-based hierarchical architecture supporting both shared-memory and message-passing communication. (2) A cache-free memory hierarchy with an extended register file, small private memory and moderate shared memory to avoid complex cache coherence issues and achieve high energy efficiency by keeping data accesses local. (3) A hardware-aided mailbox mechanism to accelerate the synchronization procedure between different processor nodes. With these techniques, our multicore processor can provide high performance for many applications. Chip test results show that its maximum clock frequency is 800MHz and typical power consumption is 320mW, when running basic applications with clock gating at 1.2V at room temperature.
{"title":"An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms","authors":"Zhiyi Yu, K. You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying, Haofan Yang, Ming-e Jing, Xiaoyang Zeng","doi":"10.1109/ISSCC.2012.6176931","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176931","url":null,"abstract":"Almost all multicore processors use a shared-memory architecture due to its simple programming model. Recently, however, the message-passing mechanism is also drawing attention due to its potentially better scalability. In this work, we demonstrate that a hybrid communication mechanism supporting both message passing and shared memory can provide both higher performance and energy efficiency. This 16-core processor has 3 key features: (1) A cluster-based hierarchical architecture supporting both shared-memory and message-passing communication. (2) A cache-free memory hierarchy with an extended register file, small private memory and moderate shared memory to avoid complex cache coherence issues and achieve high energy efficiency by keeping data accesses local. (3) A hardware-aided mailbox mechanism to accelerate the synchronization procedure between different processor nodes. With these techniques, our multicore processor can provide high performance for many applications. Chip test results show that its maximum clock frequency is 800MHz and typical power consumption is 320mW, when running basic applications with clock gating at 1.2V at room temperature.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115510086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177073
N. Shibata, K. Kanda, Toshiki Hisada, K. Isobe, Manabu Sato, Y. Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, K. Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, J. Nakai, K. Iwasa, M. Kojima, Toshihiro Suzuki, Yuya Suzuki, S. Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, M. Miakashi, N. Kobayashi, M. Inagaki, Yuuki Matsumoto, S. Inoue, Yoshinao Suzuki, D. He, Yasuhiko Honda, Junji Musha, M. Nakagawa, M. Honma, N. Abiko, M. Koyanagi, Masahiro Yoshihara, K. Ino, M. Noguchi, T. Kamei, Yosuke Kato, S. Zaitsu, H. Nasu, Takuya Ariki, H. Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita, G. Liang, G. Hemink, F. Moogat, Cuong Trinh, M. Higashitani, T. Pham, K. Kanazawa
NAND flash memory is widely used in digital cameras, USB devices, cell phones, camcorders and solid-state drives. Continuous lowering of bit cost, increasing flash-memory-die densities and improving performance have helped to expand flash markets. Recently, there are two different directions to meet market demands. One is lowering bit cost and increase memory density to the utmost limit, which is achieved by 4b/cell [1] or 3b/cell [2]. The other is focusing on high performance and high reliability. To meet both demands, we develop a 19nm 112.8mm2 64Gb 2b/cell NAND flash memory with the smallest die size ever reported. 15MB/s programming throughput and 400Mb/s/pin 1.8V Toggle Mode interface [3] are achieved for the first time. Die Micrograph and features are shown in Figure 25.1.1.
{"title":"A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface","authors":"N. Shibata, K. Kanda, Toshiki Hisada, K. Isobe, Manabu Sato, Y. Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, K. Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, J. Nakai, K. Iwasa, M. Kojima, Toshihiro Suzuki, Yuya Suzuki, S. Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, M. Miakashi, N. Kobayashi, M. Inagaki, Yuuki Matsumoto, S. Inoue, Yoshinao Suzuki, D. He, Yasuhiko Honda, Junji Musha, M. Nakagawa, M. Honma, N. Abiko, M. Koyanagi, Masahiro Yoshihara, K. Ino, M. Noguchi, T. Kamei, Yosuke Kato, S. Zaitsu, H. Nasu, Takuya Ariki, H. Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita, G. Liang, G. Hemink, F. Moogat, Cuong Trinh, M. Higashitani, T. Pham, K. Kanazawa","doi":"10.1109/ISSCC.2012.6177073","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177073","url":null,"abstract":"NAND flash memory is widely used in digital cameras, USB devices, cell phones, camcorders and solid-state drives. Continuous lowering of bit cost, increasing flash-memory-die densities and improving performance have helped to expand flash markets. Recently, there are two different directions to meet market demands. One is lowering bit cost and increase memory density to the utmost limit, which is achieved by 4b/cell [1] or 3b/cell [2]. The other is focusing on high performance and high reliability. To meet both demands, we develop a 19nm 112.8mm2 64Gb 2b/cell NAND flash memory with the smallest die size ever reported. 15MB/s programming throughput and 400Mb/s/pin 1.8V Toggle Mode interface [3] are achieved for the first time. Die Micrograph and features are shown in Figure 25.1.1.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"271 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116151882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176892
Gerard Villar Pique
This work presents a switched-capacitor power converter (SCPC) with a power density of 38.6mW/mm2 at 81% efficiency and 3.8mV output voltage ripple (ΔV0) in baseline 90nm CMOS. The design implements two different conversion ratios to maximize efficiency for a wide range of input voltages, and the use of 41 phases results in a very low output voltage ripple and low input current spikes.
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Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176870
K. Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dongkyun Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong Kang, K. Park, Byunghoon Jeong
We present a sensing scheme with local bitline sense amplifier (L-BLSA) for sub-1V DRAM core operation, which activates a low-Vt latch locally in time, the same as [1] but shares a common ground with a high-Vt latch. Hybrid LIO sense amplifier (H-LSA) is developed for robust LIO read operation at low voltage and high clock frequency. In order to reduce the die area, we develop a dummy-less 6F2 array architecture with no edge dummy array. These schemes are employed in a 1.2V 23nm 6F2 4Gb DDR3 SDRAM.
{"title":"A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture","authors":"K. Lim, Woong-Ju Jang, Hyung-Sik Won, Kang-Yeol Lee, Hyungsoo Kim, Dongkyun Kim, Mi-Hyun Cho, Seung-Lo Kim, Jong Kang, K. Park, Byunghoon Jeong","doi":"10.1109/ISSCC.2012.6176870","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176870","url":null,"abstract":"We present a sensing scheme with local bitline sense amplifier (L-BLSA) for sub-1V DRAM core operation, which activates a low-Vt latch locally in time, the same as [1] but shares a common ground with a high-Vt latch. Hybrid LIO sense amplifier (H-LSA) is developed for robust LIO read operation at low voltage and high clock frequency. In order to reduce the die area, we develop a dummy-less 6F2 array architecture with no edge dummy array. These schemes are employed in a 1.2V 23nm 6F2 4Gb DDR3 SDRAM.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123745707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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