Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176938
S. K. Garakoui, E. Klumperink, B. Nauta, F. V. Vliet
Electronically variable delays for beamforming are generally realized by phase shifters. Although a constant phase shift can approximate a time delay in a limited frequency band, this does not hold for larger arrays that scan over wide angles and have a large instantaneous bandwidth. In this case true time delays are wanted to avoid effects such as beam-squinting. In this paper we aim at compactly integrating a delay based phased-array receiver in standard CMOS IC technology. This is for instance relevant for synthetic aperture radars, which require large instantaneous bandwidths often in excess of 1GHz, either as RF or as IF bandwidth in a superheterodyne system. We target low-GHz radar frequencies, assuming sub-arrays of four elements and up to 550ps delay.
{"title":"A 1-to-2.5GHz phased-array IC based on gm-RC all-pass time-delay cells","authors":"S. K. Garakoui, E. Klumperink, B. Nauta, F. V. Vliet","doi":"10.1109/ISSCC.2012.6176938","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176938","url":null,"abstract":"Electronically variable delays for beamforming are generally realized by phase shifters. Although a constant phase shift can approximate a time delay in a limited frequency band, this does not hold for larger arrays that scan over wide angles and have a large instantaneous bandwidth. In this case true time delays are wanted to avoid effects such as beam-squinting. In this paper we aim at compactly integrating a delay based phased-array receiver in standard CMOS IC technology. This is for instance relevant for synthetic aperture radars, which require large instantaneous bandwidths often in excess of 1GHz, either as RF or as IF bandwidth in a superheterodyne system. We target low-GHz radar frequencies, assuming sub-arrays of four elements and up to 550ps delay.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"163 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129216434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177117
C. Hoof, W. Dehaene, Wentai Liu, T. Denison, M. Je, H. Yoo
The aim of this forum is to translate the challenge of sustainable healthcare into a set of application challenges, from which design, circuit and technology needs can be derived. By means of examples, the role of advanced circuit design in solving the application challenges will be clarified. Enabling circuit paradigms will be presented and discussed.
{"title":"Bioelectronics for sustainable healthcare","authors":"C. Hoof, W. Dehaene, Wentai Liu, T. Denison, M. Je, H. Yoo","doi":"10.1109/ISSCC.2012.6177117","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177117","url":null,"abstract":"The aim of this forum is to translate the challenge of sustainable healthcare into a set of application challenges, from which design, circuit and technology needs can be derived. By means of examples, the role of advanced circuit design in solving the application challenges will be clarified. Enabling circuit paradigms will be presented and discussed.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"127 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124236977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176944
N. V. Helleputte, Sunyoung Kim, Hyejung Kim, Jong Pal Kim, C. Hoof, R. Yazicioglu
There exists a growing interest in wearable/portable biopotential monitoring systems. These systems have very strict requirements in terms of power dissipation, high signal quality, small area (minimal use of externals) and robust operation during ambulatory use. The latter is emerging as an especially important problem since in real-life ambulatory conditions, motion artifacts can disturb and potentially saturate the readout channel. In addition, requirements for multimodal information acquisition require even more functionality with minimal power dissipation.
{"title":"A 160μA biopotential acquisition ASIC with fully integrated IA and motion-artifact suppression","authors":"N. V. Helleputte, Sunyoung Kim, Hyejung Kim, Jong Pal Kim, C. Hoof, R. Yazicioglu","doi":"10.1109/ISSCC.2012.6176944","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176944","url":null,"abstract":"There exists a growing interest in wearable/portable biopotential monitoring systems. These systems have very strict requirements in terms of power dissipation, high signal quality, small area (minimal use of externals) and robust operation during ambulatory use. The latter is emerging as an especially important problem since in real-life ambulatory conditions, motion artifacts can disturb and potentially saturate the readout channel. In addition, requirements for multimodal information acquisition require even more functionality with minimal power dissipation.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124520457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177056
C. Birk, Gerard Mora-Puchalt
This paper describes the implementation of a 60V programmable-gain amplifier (PGA) with ±10V differential input range and a 5V output compatible with many commercially available ADCs. While there is a wide range of possible applications, this design is particularly well suited for ±24V supply industrial process control applications, where small voltage signals need to be acquired in the presence of very large common-mode voltages.
{"title":"A 60V capacitive gain 27nV/√Hz 137dB CMRR PGA with ±10V inputs","authors":"C. Birk, Gerard Mora-Puchalt","doi":"10.1109/ISSCC.2012.6177056","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177056","url":null,"abstract":"This paper describes the implementation of a 60V programmable-gain amplifier (PGA) with ±10V differential input range and a 5V output compatible with many commercially available ADCs. While there is a wide range of possible applications, this design is particularly well suited for ±24V supply industrial process control applications, where small voltage signals need to be acquired in the presence of very large common-mode voltages.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126282990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176992
Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Taekwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park
As digital CMOS technology scales to 32nm and below, small and low-voltage clock and timing generators are in high demand to avoid complex analog operations and to meet stringent phase noise requirements. There have been sever- al approaches to convert analog systems to their digital counterparts and a high- resolution time-to-digital converter (TDC) is a key element for the digitalization of analog circuits. Recently TDCs using a noise shaping technique with oversampling have been introduced to improve resolution. However, they tend to be power hungry or require analog-intensive circuitry as they convert signals from the time domain to the voltage domain in order to perform arithmetic operations. A digital PLL (DPLL) is another crucial SoC component, and low-power area-efficient DPLLs are challenging to design. This paper presents a time-domain low-power ΔΣ TDC with a time-difference accumulator and an area-efficient, low-power, and fast-lock DPLL composed of a synthesizable bang-bang phase and frequency detector (BB-PFD), with a gain boosting mode and a pseudo-random number generator (PRNG).
{"title":"A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications","authors":"Jong-Phil Hong, Sung-Jin Kim, Jenlung Liu, Nan Xing, Taekwang Jang, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park","doi":"10.1109/ISSCC.2012.6176992","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176992","url":null,"abstract":"As digital CMOS technology scales to 32nm and below, small and low-voltage clock and timing generators are in high demand to avoid complex analog operations and to meet stringent phase noise requirements. There have been sever- al approaches to convert analog systems to their digital counterparts and a high- resolution time-to-digital converter (TDC) is a key element for the digitalization of analog circuits. Recently TDCs using a noise shaping technique with oversampling have been introduced to improve resolution. However, they tend to be power hungry or require analog-intensive circuitry as they convert signals from the time domain to the voltage domain in order to perform arithmetic operations. A digital PLL (DPLL) is another crucial SoC component, and low-power area-efficient DPLLs are challenging to design. This paper presents a time-domain low-power ΔΣ TDC with a time-difference accumulator and an area-efficient, low-power, and fast-lock DPLL composed of a synthesizable bang-bang phase and frequency detector (BB-PFD), with a gain boosting mode and a pseudo-random number generator (PRNG).","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126340173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177048
K. Chandrashekar, S. Pellerano, P. Madoglio, A. Ravi, Y. Palaskas
A VCO used in a PLL inside a wireless transceiver can be sensitive to interference from other radio circuitry (e.g. on-chip PA), components of the SoC system (e.g. clocks and their harmonics) and nearby radios. To prevent VCO pulling by the PA, fractional dividers can be used to offset the VCO frequency (fVCO) with respect to the PA. Multistandard radios covering, for example, WiFi 2.4 to 2.5GHz and 5 to 5.8GHz, and WiMAX 2.3 to 2.7GHz and 3.3 to 3.8GHz, may require multiple VCOs and/or multiple fractional dividers to cover all bands [1], resulting in complexity and area overhead. This paper proposes a versatile reconfigurable fractional divider capable of covering the above standards with a single VCO with 20% tuning range. The divider is all-digital, hence scaling-friendly, and uses digital calibration to eliminate the need for filtering and area-intensive inductors. The versatility afforded by the reconfigurable fractional divider allows for the transceiver's LO generation (LOG) frequency plan to be adjusted on-the-fly. This can avoid VCO pulling from interferers which may not be known a-priori, like SoC-CPU clocks that are adjusted dynamically for best performance.
{"title":"A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management","authors":"K. Chandrashekar, S. Pellerano, P. Madoglio, A. Ravi, Y. Palaskas","doi":"10.1109/ISSCC.2012.6177048","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177048","url":null,"abstract":"A VCO used in a PLL inside a wireless transceiver can be sensitive to interference from other radio circuitry (e.g. on-chip PA), components of the SoC system (e.g. clocks and their harmonics) and nearby radios. To prevent VCO pulling by the PA, fractional dividers can be used to offset the VCO frequency (fVCO) with respect to the PA. Multistandard radios covering, for example, WiFi 2.4 to 2.5GHz and 5 to 5.8GHz, and WiMAX 2.3 to 2.7GHz and 3.3 to 3.8GHz, may require multiple VCOs and/or multiple fractional dividers to cover all bands [1], resulting in complexity and area overhead. This paper proposes a versatile reconfigurable fractional divider capable of covering the above standards with a single VCO with 20% tuning range. The divider is all-digital, hence scaling-friendly, and uses digital calibration to eliminate the need for filtering and area-intensive inductors. The versatility afforded by the reconfigurable fractional divider allows for the transceiver's LO generation (LOG) frequency plan to be adjusted on-the-fly. This can avoid VCO pulling from interferers which may not be known a-priori, like SoC-CPU clocks that are adjusted dynamically for best performance.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128128814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176981
M. Winter, S. Kunze, Esther P. Adeva, B. Mennenga, E. Matús, G. Fettweis, H. Eisenreich, G. Ellguth, S. Höppner, Stefan Scholze, R. Schüffny, T. Kobori
In current and future wireless standards, such as WiMAX, 3GPP-LTE or LTE-Advanced, receiver terminals have to support numerous operating modes for each protocol [1], as well as sophisticated transmission techniques, especially enhanced MIMO detection and iterative forward error correction (FEC). MIMO detection and FEC belong to the most computationally complex parts of the receiver-side baseband signal processing chain. Implementations thereof must have low power consumption, but also be able to interact in a flexible and efficient way in the detection-decoding engine, while at the same time not compromising on the challenging throughput and flexibility requirements associated with 4G standards. In this paper, we present a chip implementation of a MIMO sphere detector combined with a flexible FEC engine, realizing a detection-decoding engine in silicon capable of satisfying 4G requirements with a data rate of 335Mb/s.
{"title":"A 335Mb/s 3.9mm2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates","authors":"M. Winter, S. Kunze, Esther P. Adeva, B. Mennenga, E. Matús, G. Fettweis, H. Eisenreich, G. Ellguth, S. Höppner, Stefan Scholze, R. Schüffny, T. Kobori","doi":"10.1109/ISSCC.2012.6176981","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176981","url":null,"abstract":"In current and future wireless standards, such as WiMAX, 3GPP-LTE or LTE-Advanced, receiver terminals have to support numerous operating modes for each protocol [1], as well as sophisticated transmission techniques, especially enhanced MIMO detection and iterative forward error correction (FEC). MIMO detection and FEC belong to the most computationally complex parts of the receiver-side baseband signal processing chain. Implementations thereof must have low power consumption, but also be able to interact in a flexible and efficient way in the detection-decoding engine, while at the same time not compromising on the challenging throughput and flexibility requirements associated with 4G standards. In this paper, we present a chip implementation of a MIMO sphere detector combined with a flexible FEC engine, realizing a detection-decoding engine in silicon capable of satisfying 4G requirements with a data rate of 335Mb/s.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121786497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176939
Bonhoon Koo, T. Joo, Yoosam Na, Songcheol Hong
Integrating a CMOS RF power amplifier (PA) into a single-chip transceiver is one of the most challenging works in implementing radio front-ends, which presents many advantages in handheld applications. Especially, low-power efficiency enhancement (LPEE) techniques, considering the probability distribution function of the practical wireless communication environments, extend the battery lifetime in handheld devices. Therefore, there are many studies for the LPEE in handheld CMOS PAs using transmission-line transformers (TLTs) with parallel amplifiers. Designing a series/parallel-combining transformer (SCT/PCT) is one of the key factors in the implementation of a dual-mode CMOS PA. However, the dual-mode performances of the PA must be optimized by using one output TLT structure. It is expected that there are difficulties in designing a highly efficient dual-mode PA. Therefore, this paper introduces a fully integrated dual-mode CMOS PA with a proposed output TLT with 2 control switches, which allows an LPEE with a back-off region of 10dB or more with a very low quiescent current.
{"title":"A fully integrated dual-mode CMOS power amplifier for WCDMA applications","authors":"Bonhoon Koo, T. Joo, Yoosam Na, Songcheol Hong","doi":"10.1109/ISSCC.2012.6176939","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176939","url":null,"abstract":"Integrating a CMOS RF power amplifier (PA) into a single-chip transceiver is one of the most challenging works in implementing radio front-ends, which presents many advantages in handheld applications. Especially, low-power efficiency enhancement (LPEE) techniques, considering the probability distribution function of the practical wireless communication environments, extend the battery lifetime in handheld devices. Therefore, there are many studies for the LPEE in handheld CMOS PAs using transmission-line transformers (TLTs) with parallel amplifiers. Designing a series/parallel-combining transformer (SCT/PCT) is one of the key factors in the implementation of a dual-mode CMOS PA. However, the dual-mode performances of the PA must be optimized by using one output TLT structure. It is expected that there are difficulties in designing a highly efficient dual-mode PA. Therefore, this paper introduces a fully integrated dual-mode CMOS PA with a proposed output TLT with 2 control switches, which allows an LPEE with a back-off region of 10dB or more with a very low quiescent current.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123907629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177042
A. Visweswaran, R. Staszewski, J. Long
Base-station (BTS) RX oscillator phase noise requirements between 600kHz and 3MHz are difficult to satisfy using a fully monolithic VCO fabricated in bulk-CMOS technology. The GSM-900-BTS and the DCS-1800-BTS RX specifications at 800kHz of -147dBc/Hz and -138dBc/Hz, respectively, are considered the most difficult to meet. In GSM mobile stations (MS), the transmit and receive bands are 20MHz apart, which sets a stringent TX phase noise requirement of -162dBc/Hz at 20MHz offset [1]. A VCO satisfying this inadvertently meets the relatively relaxed RX specification.
{"title":"A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations","authors":"A. Visweswaran, R. Staszewski, J. Long","doi":"10.1109/ISSCC.2012.6177042","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177042","url":null,"abstract":"Base-station (BTS) RX oscillator phase noise requirements between 600kHz and 3MHz are difficult to satisfy using a fully monolithic VCO fabricated in bulk-CMOS technology. The GSM-900-BTS and the DCS-1800-BTS RX specifications at 800kHz of -147dBc/Hz and -138dBc/Hz, respectively, are considered the most difficult to meet. In GSM mobile stations (MS), the transmit and receive bands are 20MHz apart, which sets a stringent TX phase noise requirement of -162dBc/Hz at 20MHz offset [1]. A VCO satisfying this inadvertently meets the relatively relaxed RX specification.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115017705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176952
Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Y. Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong-June Park, J. Sim
In high-speed wireline communication, full-rate clocking for chip-to-chip interface has been widely adopted since it eliminates clock-induced deterministic jitter. Design with standard digital CMOS technologies, however, often limits the maximum frequency of circuit operation. The increase in power and circuit complexity in full-rate clocking makes the problem even worse in the design of a parallel transceiver whose clock tree travels through long interconnects. As an alternative to the full-rate clocking, frequency generation with a multiphase PLL has been also considered to relax the tight requirements of operating frequency of oscillator and flip-flops. DRAM interface, as a representative of high-speed parallel links, has adopted quadruple data rate (QDR) schemes for high-speed graphic applications [1-2]. However, as the data rate of DRAM interface increases up to multi-Gb/s range, skew in quadrature clock phases presents one of the most serious performance degradation factors.
{"title":"An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface","authors":"Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Y. Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong-June Park, J. Sim","doi":"10.1109/ISSCC.2012.6176952","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176952","url":null,"abstract":"In high-speed wireline communication, full-rate clocking for chip-to-chip interface has been widely adopted since it eliminates clock-induced deterministic jitter. Design with standard digital CMOS technologies, however, often limits the maximum frequency of circuit operation. The increase in power and circuit complexity in full-rate clocking makes the problem even worse in the design of a parallel transceiver whose clock tree travels through long interconnects. As an alternative to the full-rate clocking, frequency generation with a multiphase PLL has been also considered to relax the tight requirements of operating frequency of oscillator and flip-flops. DRAM interface, as a representative of high-speed parallel links, has adopted quadruple data rate (QDR) schemes for high-speed graphic applications [1-2]. However, as the data rate of DRAM interface increases up to multi-Gb/s range, skew in quadrature clock phases presents one of the most serious performance degradation factors.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114723830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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