Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176973
S. Xia, K. Makinwa, S. Nihtianov
In precision mechatronic systems, such as wafer steppers, the position of critical mechanical components must be dynamically stabilized with sub-nanometer precision. This can be achieved by a servo loop consisting of a displacement sensor and an actuator. Compared to optical interferometers, capacitive displacement sensors offer smaller size and lower cost. However, mechanical tolerances limit their electrode spacing to about 10μm [1], while the targeted resolution is below 100pmrms. This requires a capacitance-to-digital converter (CDC) with more than 17b resolution. Furthermore, its latency must be low enough (20μs) to avoid compromising servo-loop stability. Lastly, it should be stable enough to maintain measurement accuracy during the intervals between system calibrations.
{"title":"A capacitance-to-digital converter for displacement sensing with 17b resolution and 20μs conversion time","authors":"S. Xia, K. Makinwa, S. Nihtianov","doi":"10.1109/ISSCC.2012.6176973","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176973","url":null,"abstract":"In precision mechatronic systems, such as wafer steppers, the position of critical mechanical components must be dynamically stabilized with sub-nanometer precision. This can be achieved by a servo loop consisting of a displacement sensor and an actuator. Compared to optical interferometers, capacitive displacement sensors offer smaller size and lower cost. However, mechanical tolerances limit their electrode spacing to about 10μm [1], while the targeted resolution is below 100pmrms. This requires a capacitance-to-digital converter (CDC) with more than 17b resolution. Furthermore, its latency must be low enough (20μs) to avoid compromising servo-loop stability. Lastly, it should be stable enough to maintain measurement accuracy during the intervals between system calibrations.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114312393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177012
Liang Wu, A. Li, H. Luong
Millimeter-Wave (MMW) phased-array receivers are used not only to overcome the large path loss and thus to relax the link budget but also to electrically steer the beam direction to suppress unwanted signals. Each element of the array requires a variable phase shift to compensate for the time difference between adjacent elements depending on the angle of the incident signals such that a maximum gain is achieved in that particular direction. Conventionally, this phase shift is controlled by the baseband with exhaustive tuning algorithms resulting in very long tuning time as the beam direction is changed, which grows exponentially with the number of elements used. This paper proposes an LO generation scheme with automatic successive phase tuning to achieve a resolution of 22.5° and an RMS error of 0.93°.
{"title":"A 4-path 42.8-to-49.5GHz LO generation with automatic phase tuning for 60GHz phased-array receivers","authors":"Liang Wu, A. Li, H. Luong","doi":"10.1109/ISSCC.2012.6177012","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177012","url":null,"abstract":"Millimeter-Wave (MMW) phased-array receivers are used not only to overcome the large path loss and thus to relax the link budget but also to electrically steer the beam direction to suppress unwanted signals. Each element of the array requires a variable phase shift to compensate for the time difference between adjacent elements depending on the angle of the incident signals such that a maximum gain is achieved in that particular direction. Conventionally, this phase shift is controlled by the baseband with exhaustive tuning algorithms resulting in very long tuning time as the beam direction is changed, which grows exponentially with the number of elements used. This paper proposes an LO generation scheme with automatic successive phase tuning to achieve a resolution of 22.5° and an RMS error of 0.93°.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114476811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177046
Yasuhisa Tochigi, Katsuhiko Hanzawa, Yuri Kato, R. Kuroda, H. Mutoh, Ryuta Hirose, H. Tominaga, K. Takubo, Y. Kondo, S. Sugawa
This paper presents a 400H×256V pixel CMOS image sensor including 128 on-chip memory/pixel with 1Tpixel/s in burst operation without cooling and 780Mpixel/s in continuous operation. To improve the read-out speed from the chip, a noise-reduction circuit in pixel and relay buffers is introduced.
{"title":"A global-shutter CMOS image sensor with readout speed of 1Tpixel/s burst and 780Mpixel/s continuous","authors":"Yasuhisa Tochigi, Katsuhiko Hanzawa, Yuri Kato, R. Kuroda, H. Mutoh, Ryuta Hirose, H. Tominaga, K. Takubo, Y. Kondo, S. Sugawa","doi":"10.1109/ISSCC.2012.6177046","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177046","url":null,"abstract":"This paper presents a 400H×256V pixel CMOS image sensor including 128 on-chip memory/pixel with 1Tpixel/s in burst operation without cooling and 780Mpixel/s in continuous operation. To improve the read-out speed from the chip, a noise-reduction circuit in pixel and relay buffers is introduced.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117282997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177035
C. Menolfi, J. Hertle, T. Toifl, T. Morf, Daniele Gardellini, M. Braendli, P. Buchmann, M. Kossel
Upcoming standards such as OIF CEI-25LR and CEI-28SR demand transmitter circuits above 20Gb/s [1]-[3] with stringent jitter requirements. The SST driver topology, which has been previously demonstrated at lower data rates [4], is an attractive solution as it enables multiple termination options and low power consumption. In addition, its single-ended topology facilitates an architecture in which the delay mismatch between true and complementary output can be adjusted, as is desirable for data transmission over long cables. In this contribution, the architecture and design of the key components of a half-rate 28Gb/s SST TX are presented.
{"title":"A 28Gb/s source-series terminated TX in 32nm CMOS SOI","authors":"C. Menolfi, J. Hertle, T. Toifl, T. Morf, Daniele Gardellini, M. Braendli, P. Buchmann, M. Kossel","doi":"10.1109/ISSCC.2012.6177035","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177035","url":null,"abstract":"Upcoming standards such as OIF CEI-25LR and CEI-28SR demand transmitter circuits above 20Gb/s [1]-[3] with stringent jitter requirements. The SST driver topology, which has been previously demonstrated at lower data rates [4], is an attractive solution as it enables multiple termination options and low power consumption. In addition, its single-ended topology facilitates an architecture in which the delay mismatch between true and complementary output can be adjusted, as is desirable for data transmission over long cables. In this contribution, the architecture and design of the key components of a half-rate 28Gb/s SST TX are presented.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124771083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176975
M. Rocznik, F. Henrici, Remigius Has
Pressure sensors used in automotive applications are subject to increasingly harsh environments such as acid containing gases in vehicle exhausts or exhaust gas recirculation. State-of-the-art gel protection for sensing elements and their electronics is reaching its limit. A circuit's exposed aluminum bond pads are especially vulnerable to corrosion and failure. In response to these issues, we report an approach to eliminate bond pads and bonds between the sensor and IC altogether.
{"title":"ASIC for a resonant wireless pressure-sensing system for harsh environments achieving ±2% error between −40 and 150°C using Q-based temperature compensation","authors":"M. Rocznik, F. Henrici, Remigius Has","doi":"10.1109/ISSCC.2012.6176975","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176975","url":null,"abstract":"Pressure sensors used in automotive applications are subject to increasingly harsh environments such as acid containing gases in vehicle exhausts or exhaust gas recirculation. State-of-the-art gel protection for sensing elements and their electronics is reaching its limit. A circuit's exposed aluminum bond pads are especially vulnerable to corrosion and failure. In response to these issues, we report an approach to eliminate bond pads and bonds between the sensor and IC altogether.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123654042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177020
Taehwan Roh, Sunjoo Hong, Hyunwoo Cho, H. Yoo
In this paper, we present a wearable mental health measurement system incorporating the nonlinear analysis of physiological rhythm including HRV and EEG signals together for high accuracy. The proposed system is implemented in a 31g headband that measures scalp signals and performs nonlinear-chaotic analysis to measure the stress levels. Using a 1.2V 40mAhr coin-battery (11.7χ5.35mm21.7g), the proposed system is able to operate for more than 7 days.
{"title":"A 259.6μW nonlinear HRV-EEG chaos processor with body channel communication interface for mental health monitoring","authors":"Taehwan Roh, Sunjoo Hong, Hyunwoo Cho, H. Yoo","doi":"10.1109/ISSCC.2012.6177020","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177020","url":null,"abstract":"In this paper, we present a wearable mental health measurement system incorporating the nonlinear analysis of physiological rhythm including HRV and EEG signals together for high accuracy. The proposed system is implemented in a 31g headband that measures scalp signals and performs nonlinear-chaotic analysis to measure the stress levels. Using a 1.2V 40mAhr coin-battery (11.7χ5.35mm21.7g), the proposed system is able to operate for more than 7 days.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121760098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177097
Ho-Young Lee, B. Lee, U. Moon
Analog-to-digital conversion with a signal bandwidth of 10 to 20MHz and ENOB of 11 to 12b has become a common requirement in many modern wireless communication systems where low power consumption is always a necessity. Typically, the traditional 2-step pipelined ADC is not considered a good candidate to meet these design specifications, since it is implemented with a power-hungry high-resolution flash sub-ADC and high-gain residue amplifier. Recently, however, low-power SAR architectures have been proposed as efficient replacements for flash-based sub-ADCs [1], especially since the conversion rate may be improved with the use of asynchronous clocking [2].
{"title":"A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V two-step pipelined ADC in 0.13μm CMOS","authors":"Ho-Young Lee, B. Lee, U. Moon","doi":"10.1109/ISSCC.2012.6177097","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177097","url":null,"abstract":"Analog-to-digital conversion with a signal bandwidth of 10 to 20MHz and ENOB of 11 to 12b has become a common requirement in many modern wireless communication systems where low power consumption is always a necessity. Typically, the traditional 2-step pipelined ADC is not considered a good candidate to meet these design specifications, since it is implemented with a power-hungry high-resolution flash sub-ADC and high-gain residue amplifier. Recently, however, low-power SAR architectures have been proposed as efficient replacements for flash-based sub-ADCs [1], especially since the conversion rate may be improved with the use of asynchronous clocking [2].","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126168867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177043
Dongmin Yoon, D. Sylvester, D. Blaauw
There is a growing interest in ultra-low-power wireless microsystems [1]. Synchronization between different nodes in a wireless sensor network plays an important role in the overall node energy budget due to the high power demand of wireless communication. One synchronization approach is to employ a realtime clock (RTC) on each node, with nodes awakening periodically to communicate and re-synchronize. With recent work on ultra-low-power microsystems demonstrating average power consumption of several nW [2], there is a need for ultra-low-power timers that can synchronize communication events and serve as frequency references for radios.
{"title":"A 5.58nW 32.768kHz DLL-assisted XO for real-time clocks in wireless sensing applications","authors":"Dongmin Yoon, D. Sylvester, D. Blaauw","doi":"10.1109/ISSCC.2012.6177043","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177043","url":null,"abstract":"There is a growing interest in ultra-low-power wireless microsystems [1]. Synchronization between different nodes in a wireless sensor network plays an important role in the overall node energy budget due to the high power demand of wireless communication. One synchronization approach is to employ a realtime clock (RTC) on each node, with nodes awakening periodically to communicate and re-synchronize. With recent work on ultra-low-power microsystems demonstrating average power consumption of several nW [2], there is a need for ultra-low-power timers that can synchronize communication events and serve as frequency references for radios.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116123256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6177034
Yusuke Tanaka, Yasufumi Hino, Y. Okada, Takahiro Takeda, Sho Ohashi, H. Yamagishi, K. Kawasaki, A. Hajimiri
Serial data links are often designed targeting a specific transmission medium. High-speed links using different predetermined transmission media have been demonstrated in the past [1-3]. This, however, restricts user's ability to use an integrated link interface with other transmission media once the chip is fabricated. For example, traditional transceivers for copper interconnects typically transmit baseband data, which is incompatible with a free-space wireless channel that is bandpass in nature and often uses RF carriers. A multi-modality transceiver block compatible with different transmission media is highly desirable as it offers great versatility by allowing the exact same interface circuitry to be used with different transmission media. Such a versatile interface can relax the board and system design requirements and enable the reuse of the same transceiver core with different media, reducing the time and cost overhead of re-designing and re-manufacturing.
{"title":"A versatile multi-modality serial link","authors":"Yusuke Tanaka, Yasufumi Hino, Y. Okada, Takahiro Takeda, Sho Ohashi, H. Yamagishi, K. Kawasaki, A. Hajimiri","doi":"10.1109/ISSCC.2012.6177034","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6177034","url":null,"abstract":"Serial data links are often designed targeting a specific transmission medium. High-speed links using different predetermined transmission media have been demonstrated in the past [1-3]. This, however, restricts user's ability to use an integrated link interface with other transmission media once the chip is fabricated. For example, traditional transceivers for copper interconnects typically transmit baseband data, which is incompatible with a free-space wireless channel that is bandpass in nature and often uses RF carriers. A multi-modality transceiver block compatible with different transmission media is highly desirable as it offers great versatility by allowing the exact same interface circuitry to be used with different transmission media. Such a versatile interface can relax the board and system design requirements and enable the reuse of the same transceiver core with different media, reducing the time and cost overhead of re-designing and re-manufacturing.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122272429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-04-03DOI: 10.1109/ISSCC.2012.6176969
Daehyun Kim, K. Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, G. Kumar, Young-Joon Lee, D. L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, M. Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, G. Loh, H. Lee, S. Lim
Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration, but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM. Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5x5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.
{"title":"3D-MAPS: 3D Massively parallel processor with stacked memory","authors":"Daehyun Kim, K. Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, G. Kumar, Young-Joon Lee, D. L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, M. Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, G. Loh, H. Lee, S. Lim","doi":"10.1109/ISSCC.2012.6176969","DOIUrl":"https://doi.org/10.1109/ISSCC.2012.6176969","url":null,"abstract":"Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration, but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM. Fabrication is done using 130nm GlobalFoundries device technology and Tezzaron TSV and bonding technology. Packaging is done by Amkor. This processor contains 33M transistors, 50K TSVs, and 50K face-to-face connections in 5x5mm2 footprint. The chip runs at 1.5V and consumes up to 4W, resulting in 16W/cm2 power density. The core architecture is developed from scratch to benefit from single-cycle access to SRAM.","PeriodicalId":255282,"journal":{"name":"2012 IEEE International Solid-State Circuits Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127083362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：