Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520179
Bin Gu, J. Dominic, J. Lai, Hongbo Ma
This paper presents a high boost ratio dc-dc converter with hybrid transformer for non-isolated photovoltaic (PV) microinverters. The proposed converter incorporates the resonant operation mode into the traditional high boost ratio active-clamp coupled-inductor PWM converter, achieving ZVS turn-on of the switches and ZCS turn-off of the diodes. As a result of the inductive and capacitive energy being transferred simultaneously within both turn-on and turn-off intervals of the main switch, the dc bias of the magnetizing current is reduced and hence the size of magnetics can be reduced. The magnetizing inductance is designed with a small value to utilize ripple magnetizing current to assist ZVS of main switch, while maintaining low RMS conduction losses. The voltage stresses on the active switches and diodes are maintained at a low level and are independent of the wide changing input PV voltages as a result of the resonant capacitor in series in the energy transfer loop. The experimental results based on 250 W prototype circuit show system CEC efficiencies greater than 96.7% over 20 V to 45 V PV voltage range.
{"title":"Hybrid transformer ZVS/ZCS DC-DC converter for photovoltaic microinverters","authors":"Bin Gu, J. Dominic, J. Lai, Hongbo Ma","doi":"10.1109/APEC.2013.6520179","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520179","url":null,"abstract":"This paper presents a high boost ratio dc-dc converter with hybrid transformer for non-isolated photovoltaic (PV) microinverters. The proposed converter incorporates the resonant operation mode into the traditional high boost ratio active-clamp coupled-inductor PWM converter, achieving ZVS turn-on of the switches and ZCS turn-off of the diodes. As a result of the inductive and capacitive energy being transferred simultaneously within both turn-on and turn-off intervals of the main switch, the dc bias of the magnetizing current is reduced and hence the size of magnetics can be reduced. The magnetizing inductance is designed with a small value to utilize ripple magnetizing current to assist ZVS of main switch, while maintaining low RMS conduction losses. The voltage stresses on the active switches and diodes are maintained at a low level and are independent of the wide changing input PV voltages as a result of the resonant capacitor in series in the energy transfer loop. The experimental results based on 250 W prototype circuit show system CEC efficiencies greater than 96.7% over 20 V to 45 V PV voltage range.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"30 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124654532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520644
X. Gong, J. Ferreira
This paper investigates the conducted EMI in SiC JFETs based inverters for motor drives under the influence of capacitive coupling from two types of substrates - Insulated Metal Substrate (IMS) and heat sinks. The inverter prototypes are implemented with the discrete SiC Transistors attached on top of the two substrates, which creates capacitive coupling between the device drain plate and the substrate base plate. The resulting EMC differences are analyzed and compared. It is found that the employment of IMS significantly deteriorates the EMC performance due to the extensive capacitive coupling magnitude. The method of using another substrate layout - each SiC JFET is placed on top of a separated heat sink to minimize the coupling is proposed. The EMI spectrums of the above inverters are compared under unfiltered and filtered conditions. It is found that the inverter version of using separated heat sinks reduces EMI both in the middle and high frequency ranges, which greatly releases the filtering effort. Finally, their different EMI filter requirements are analyzed and implemented, which effectively suppresses the conducted EMI to comply with the standard prescribed by IEC61800-3 C2 Qp.
{"title":"Conducted EMI in SiC JFET inverters due to substrate capacitive coupling","authors":"X. Gong, J. Ferreira","doi":"10.1109/APEC.2013.6520644","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520644","url":null,"abstract":"This paper investigates the conducted EMI in SiC JFETs based inverters for motor drives under the influence of capacitive coupling from two types of substrates - Insulated Metal Substrate (IMS) and heat sinks. The inverter prototypes are implemented with the discrete SiC Transistors attached on top of the two substrates, which creates capacitive coupling between the device drain plate and the substrate base plate. The resulting EMC differences are analyzed and compared. It is found that the employment of IMS significantly deteriorates the EMC performance due to the extensive capacitive coupling magnitude. The method of using another substrate layout - each SiC JFET is placed on top of a separated heat sink to minimize the coupling is proposed. The EMI spectrums of the above inverters are compared under unfiltered and filtered conditions. It is found that the inverter version of using separated heat sinks reduces EMI both in the middle and high frequency ranges, which greatly releases the filtering effort. Finally, their different EMI filter requirements are analyzed and implemented, which effectively suppresses the conducted EMI to comply with the standard prescribed by IEC61800-3 C2 Qp.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130515908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520425
S. Harb, R. Balog
This paper proposes a new technique for double-frequency ripple-power decoupling in a single-phase PWM rectifier that does not require an electrolytic capacitor, which improves the reliability of the system for long-life applications such as LED lighting. A ripple-port is added in parallel with the output of the PWM rectifier to filter the double-line-frequency ripple using the minimum capacitance necessary for power buffering. Hence, a very small, highly reliable film capacitor is used, which will improve the reliability dramatically compared to the bulky electrolytic capacitor option, which increased the power density of the system. The proposed topology doubles the MTBF increases the lifetime by one order of magnitude. Moreover, the design and control of the ripple-port is independent from the PWM rectifier circuit, so it can be dropped in as an auxiliary circuit to an existing design.
{"title":"Single-phase PWM rectifier with power decoupling ripple-port for double-line-frequency ripple cancellation","authors":"S. Harb, R. Balog","doi":"10.1109/APEC.2013.6520425","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520425","url":null,"abstract":"This paper proposes a new technique for double-frequency ripple-power decoupling in a single-phase PWM rectifier that does not require an electrolytic capacitor, which improves the reliability of the system for long-life applications such as LED lighting. A ripple-port is added in parallel with the output of the PWM rectifier to filter the double-line-frequency ripple using the minimum capacitance necessary for power buffering. Hence, a very small, highly reliable film capacitor is used, which will improve the reliability dramatically compared to the bulky electrolytic capacitor option, which increased the power density of the system. The proposed topology doubles the MTBF increases the lifetime by one order of magnitude. Moreover, the design and control of the ripple-port is independent from the PWM rectifier circuit, so it can be dropped in as an auxiliary circuit to an existing design.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"601 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123193650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520234
Y. Liao, Hung-Chi Chen, Hsiu-Che Cheng
In this paper, the analysis of circulating currents of a paralleled single-phase boost rectifier system is presented. The DC loop and AC loop circulating currents are clearly explained. Based on the analysis of circulating currents, common mode circulating current (CMCC) and differential mode circulating current (DMCC) are clearly defined. Then, CMCC and DMCC compensators in a centralized control scheme are proposed to reduce the common-mode and differential-mode circulating currents in the parallel rectifier system. Finally, a prototype system is constructed and some experimental results are carried out to verify the validity of the proposed control scheme. From experimental results, the proposed control scheme can indeed reduce the circulating currents under different power rating condition in the parallel system.
{"title":"Common mode and differential mode circulating-current control in paralleled single-phase boost rectifiers","authors":"Y. Liao, Hung-Chi Chen, Hsiu-Che Cheng","doi":"10.1109/APEC.2013.6520234","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520234","url":null,"abstract":"In this paper, the analysis of circulating currents of a paralleled single-phase boost rectifier system is presented. The DC loop and AC loop circulating currents are clearly explained. Based on the analysis of circulating currents, common mode circulating current (CMCC) and differential mode circulating current (DMCC) are clearly defined. Then, CMCC and DMCC compensators in a centralized control scheme are proposed to reduce the common-mode and differential-mode circulating currents in the parallel rectifier system. Finally, a prototype system is constructed and some experimental results are carried out to verify the validity of the proposed control scheme. From experimental results, the proposed control scheme can indeed reduce the circulating currents under different power rating condition in the parallel system.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123213452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520537
Seung-Hwan Lee, R. Lorenz
It was demonstrated that a surface spiral winding coil has low skin- and proximity effect losses in MHz, high power wireless power transfer systems. However, it was not clearly explained why the surface spiral winding coil is appropriate to use in kW level, low flux density, and safe wireless power transfer systems. Furthermore, research has not focused on the losses of a dielectric substrate of a surface spiral winding coil, even though the dielectric loss can overwhelm the skin- and proximity effect losses at MHz frequencies. In the first part of this paper, the benefits of the surface spiral winding coils for large air-gap, kW level wireless power transfer systems are discussed. In the following section, various sources of the power dissipation in surface spiral coils are identified. The discussion focuses on the dielectric losses in the substrates of surface spiral winding coils. Low-loss substrate design guidelines are proposed using the investigation results. The proposed design guidelines are evaluated by means of FEA simulation.
{"title":"Surface spiral coil design methodologies for high efficiency, high power, low flux density, large air-gap wireless power transfer systems","authors":"Seung-Hwan Lee, R. Lorenz","doi":"10.1109/APEC.2013.6520537","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520537","url":null,"abstract":"It was demonstrated that a surface spiral winding coil has low skin- and proximity effect losses in MHz, high power wireless power transfer systems. However, it was not clearly explained why the surface spiral winding coil is appropriate to use in kW level, low flux density, and safe wireless power transfer systems. Furthermore, research has not focused on the losses of a dielectric substrate of a surface spiral winding coil, even though the dielectric loss can overwhelm the skin- and proximity effect losses at MHz frequencies. In the first part of this paper, the benefits of the surface spiral winding coils for large air-gap, kW level wireless power transfer systems are discussed. In the following section, various sources of the power dissipation in surface spiral coils are identified. The discussion focuses on the dielectric losses in the substrates of surface spiral winding coils. Low-loss substrate design guidelines are proposed using the investigation results. The proposed design guidelines are evaluated by means of FEA simulation.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120965607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520335
Bin Li, Ming Zhang, Long Huang, L. Hang, L. Tolbert
An averaged switching model of grid-connected inverter using dual-loop current control with LCL-filter in discrete domain is built under stationary frame. A proportional resonant (PR) regulator is adopted in the current-loop to track the given fundamental sinusoidal current without steady state error. In addition, in order to reduce the low frequency harmonics, the resonance of 5th harmonics is adopted. Because the system is of high order and complex, the theory of root locus is proposed to analyze the influence of parameters in PR regulator, the influence of digital delay, and the LCL-filter. Based on the theoretical analysis, the poles can be properly selected to guarantee the stability of the system and the performance of current-loop during wide grid-fed power. Finally, a 10 kW prototype of grid-connected inverter with LCL-filter is set up to verify the effectiveness, practicality, and robustness of the proposed design method.
{"title":"A robust multi-resonant PR regulator for three-phase grid-connected VSI using direct pole placement design strategy","authors":"Bin Li, Ming Zhang, Long Huang, L. Hang, L. Tolbert","doi":"10.1109/APEC.2013.6520335","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520335","url":null,"abstract":"An averaged switching model of grid-connected inverter using dual-loop current control with LCL-filter in discrete domain is built under stationary frame. A proportional resonant (PR) regulator is adopted in the current-loop to track the given fundamental sinusoidal current without steady state error. In addition, in order to reduce the low frequency harmonics, the resonance of 5th harmonics is adopted. Because the system is of high order and complex, the theory of root locus is proposed to analyze the influence of parameters in PR regulator, the influence of digital delay, and the LCL-filter. Based on the theoretical analysis, the poles can be properly selected to guarantee the stability of the system and the performance of current-loop during wide grid-fed power. Finally, a 10 kW prototype of grid-connected inverter with LCL-filter is set up to verify the effectiveness, practicality, and robustness of the proposed design method.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121285638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520546
A. Vázquez, Alberto Rodríguez, Marcos Fernandez, M. Hernando, †. EnriqueMasset, Javier Sebastián, Edificio Departamental
The new wide band-gap semiconductor devices provide new properties to be explored. Normally-on Silicon Carbide (SiC) JFET power devices have several advantages, in particular low switching losses, high temperature operation and high reverse voltage capability. Looking for improve the overall efficiency in power converters, new structures based on these power devices might be studied. In this paper, a cascode rectifier based on normally-on SiC JFET is presented and analyzed. This new rectification structure can be applied as front-end rectifier stage for AC-DC power converters, increasing the overall efficiency of these topologies. A second cascode rectifier based on Silicon (Si) MOSFET is also studied, as a low cost alternative. Both cascode structures are compared with traditional Si rectifier diodes and front-end rectifiers, using three different test circuits: a full bridge rectifier, a passive Power Factor Corrector (PFC) voltage doubler and an active PFC interleaved boost converter. As a result of this comparison, an efficiency improvement as high as two points is obtained on each tested circuit.
{"title":"On the use of front-end cascode rectifiers based on normally-on SiC JFET and Si MOSFET","authors":"A. Vázquez, Alberto Rodríguez, Marcos Fernandez, M. Hernando, †. EnriqueMasset, Javier Sebastián, Edificio Departamental","doi":"10.1109/APEC.2013.6520546","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520546","url":null,"abstract":"The new wide band-gap semiconductor devices provide new properties to be explored. Normally-on Silicon Carbide (SiC) JFET power devices have several advantages, in particular low switching losses, high temperature operation and high reverse voltage capability. Looking for improve the overall efficiency in power converters, new structures based on these power devices might be studied. In this paper, a cascode rectifier based on normally-on SiC JFET is presented and analyzed. This new rectification structure can be applied as front-end rectifier stage for AC-DC power converters, increasing the overall efficiency of these topologies. A second cascode rectifier based on Silicon (Si) MOSFET is also studied, as a low cost alternative. Both cascode structures are compared with traditional Si rectifier diodes and front-end rectifiers, using three different test circuits: a full bridge rectifier, a passive Power Factor Corrector (PFC) voltage doubler and an active PFC interleaved boost converter. As a result of this comparison, an efficiency improvement as high as two points is obtained on each tested circuit.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114213944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520697
N. Lima, L. D. de Freitas, G. M. Buiatti, J. Vieira, L. Freitas, E. Coelho
This paper presents a low complexity system for characterizing Photovoltaic (PV) modules and strings in real-time, allowing accurate measurements and analysis of the actual power production of PV systems in real operation conditions. Applicability of this characterization system is in the real-time condition monitoring of such PV systems when suitable algorithms that make use of such current-voltage information (here in called I-V curve) are applied. For this purpose, a classical Boost converter is used operating as a controlled electronic load. The I-V points obtained from the load variation between the electrical terminals of the PV module or string are used to trace the whole I-V curve. The values obtained by the proposed system are compared with reference values obtained through a high accuracy I-V curve tracer available in the market, in order to validate the accuracy of the here proposed characterization system. The availability of such data makes possible to identify the presence of partial shadows that may lead to more than one local and global Maximum Power Point (MPP). It is even possible to quantify the power loss production that might raise-up due to the shadow presence, depending on Maximum Power Point Tracking (MPPT) algorithm adopted by the power converter between the PV strings and the grid or load connected to the latter one.
{"title":"Low complexity system for real-time determination of current-voltage characteristic of PV modules and strings","authors":"N. Lima, L. D. de Freitas, G. M. Buiatti, J. Vieira, L. Freitas, E. Coelho","doi":"10.1109/APEC.2013.6520697","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520697","url":null,"abstract":"This paper presents a low complexity system for characterizing Photovoltaic (PV) modules and strings in real-time, allowing accurate measurements and analysis of the actual power production of PV systems in real operation conditions. Applicability of this characterization system is in the real-time condition monitoring of such PV systems when suitable algorithms that make use of such current-voltage information (here in called I-V curve) are applied. For this purpose, a classical Boost converter is used operating as a controlled electronic load. The I-V points obtained from the load variation between the electrical terminals of the PV module or string are used to trace the whole I-V curve. The values obtained by the proposed system are compared with reference values obtained through a high accuracy I-V curve tracer available in the market, in order to validate the accuracy of the here proposed characterization system. The availability of such data makes possible to identify the presence of partial shadows that may lead to more than one local and global Maximum Power Point (MPP). It is even possible to quantify the power loss production that might raise-up due to the shadow presence, depending on Maximum Power Point Tracking (MPPT) algorithm adopted by the power converter between the PV strings and the grid or load connected to the latter one.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114324114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520274
P. Ning, Zhenxian Liang, F. Wang
A novel packaging structure for medium power modules featuring power semiconductor switches sandwiched between two symmetric substrates that fulfill electrical conduction and insulation functions is presented. Large bonding areas between dies and substrates allow this packaging technology to offer significant improvements in electrical, thermal performance. Double-sided cooling system was dedicatedly analyzed and designed for different applications.
{"title":"Double-sided cooling design for novel planar module","authors":"P. Ning, Zhenxian Liang, F. Wang","doi":"10.1109/APEC.2013.6520274","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520274","url":null,"abstract":"A novel packaging structure for medium power modules featuring power semiconductor switches sandwiched between two symmetric substrates that fulfill electrical conduction and insulation functions is presented. Large bonding areas between dies and substrates allow this packaging technology to offer significant improvements in electrical, thermal performance. Double-sided cooling system was dedicatedly analyzed and designed for different applications.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114872892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-17DOI: 10.1109/APEC.2013.6520660
B. McDonald, D. Freeman
This paper will present a method to model and characterize a typical LLC dc-dc converter transformer with a center tapped secondary. The emphasis of the model will be on the ease of characterization using practical lab equipment and its subsequent suitability for simulation in a number of practical venues (e.g. Saber, Simplis, Pspice [9][10][11]). Practical design implications for the LLC converter will also be explored.
{"title":"Practical transformer modeling and characterization for a high performance LLC converter","authors":"B. McDonald, D. Freeman","doi":"10.1109/APEC.2013.6520660","DOIUrl":"https://doi.org/10.1109/APEC.2013.6520660","url":null,"abstract":"This paper will present a method to model and characterize a typical LLC dc-dc converter transformer with a center tapped secondary. The emphasis of the model will be on the ease of characterization using practical lab equipment and its subsequent suitability for simulation in a number of practical venues (e.g. Saber, Simplis, Pspice [9][10][11]). Practical design implications for the LLC converter will also be explored.","PeriodicalId":256756,"journal":{"name":"2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124505986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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