When testing sequential circuits with scan chains, the test patterns are generated on their combinational parts assuming that all value combinations can be used for flip-flops. On the other hands, if target circuits have initial values for flip-flops, it is well known that the sets of reachable states may be much smaller than the entire state space, and there are lots of value combinations for flip-flops which can never be realized in the normal operations starting with the initial states. Therefore, there are possibilities that the values used for the flip-flops in the set of test patterns cannot be realized through normal operations, and there may be over testing issues, as some of the detectable faults by the given test patterns are actually non-detectable under the normal operations. In this paper, we first give a quick way to generate super sets of reachable states on the values of the given subset of flipflops based on QBF (Quantified Boolean Formula) formulation. By limiting the numbers of flipflops in the subset to small, such as 6 or so, we can generate an inductive-invariant for the values of the given subset of flipflops in less than a second for any ISCAS89 circuits. The generated invariant corresponds to a superset of reachable states assuming that the initial state is the one where all flipflop values are zero (or some specific values), and the complement of an invariant is a subset of unreachable states. It is shown that close to the half of a typical set of compacted test patterns for stuck-at (single and multiple) faults on ISCAS89 circuits are using the values from the computed unreachable states, i.e., possibly over testing the circuits, if the initial state is the all zero state. Then we generate the sets of test patterns for stuck-at faults (single and multiple) which never use the values inside the subset of unreachable states. The resulting sets of test patterns become several times larger than a compacted test patterns without considering unreachable states.
{"title":"Detection of test Patterns with Unreachable States through Efficient Inductive-Invariant Identification","authors":"M. Fujita","doi":"10.1109/ATS.2015.13","DOIUrl":"https://doi.org/10.1109/ATS.2015.13","url":null,"abstract":"When testing sequential circuits with scan chains, the test patterns are generated on their combinational parts assuming that all value combinations can be used for flip-flops. On the other hands, if target circuits have initial values for flip-flops, it is well known that the sets of reachable states may be much smaller than the entire state space, and there are lots of value combinations for flip-flops which can never be realized in the normal operations starting with the initial states. Therefore, there are possibilities that the values used for the flip-flops in the set of test patterns cannot be realized through normal operations, and there may be over testing issues, as some of the detectable faults by the given test patterns are actually non-detectable under the normal operations. In this paper, we first give a quick way to generate super sets of reachable states on the values of the given subset of flipflops based on QBF (Quantified Boolean Formula) formulation. By limiting the numbers of flipflops in the subset to small, such as 6 or so, we can generate an inductive-invariant for the values of the given subset of flipflops in less than a second for any ISCAS89 circuits. The generated invariant corresponds to a superset of reachable states assuming that the initial state is the one where all flipflop values are zero (or some specific values), and the complement of an invariant is a subset of unreachable states. It is shown that close to the half of a typical set of compacted test patterns for stuck-at (single and multiple) faults on ISCAS89 circuits are using the values from the computed unreachable states, i.e., possibly over testing the circuits, if the initial state is the all zero state. Then we generate the sets of test patterns for stuck-at faults (single and multiple) which never use the values inside the subset of unreachable states. The resulting sets of test patterns become several times larger than a compacted test patterns without considering unreachable states.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121123522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Grzegorz Mrugalski, J. Rajski, J. Solecki, J. Tyszer, Chen Wang
This paper presents a novel scan-based DFT paradigm. Compared to conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage, or allows applying much larger number of vectors within the same time interval. An equally important factor is the power dissipated during test - with the new scheme it remains similar to that of the mission mode. Several techniques are introduced that allow easy integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. Experimental results obtained for large and complex industrial ASIC designs illustrate feasibility of the proposed test schemes and are reported herein.
{"title":"TestExpress - New Time-Effective Scan-Based Deterministic Test Paradigm","authors":"Grzegorz Mrugalski, J. Rajski, J. Solecki, J. Tyszer, Chen Wang","doi":"10.1109/ATS.2015.11","DOIUrl":"https://doi.org/10.1109/ATS.2015.11","url":null,"abstract":"This paper presents a novel scan-based DFT paradigm. Compared to conventional scan, the presented approach either significantly reduces test application time while preserving high fault coverage, or allows applying much larger number of vectors within the same time interval. An equally important factor is the power dissipated during test - with the new scheme it remains similar to that of the mission mode. Several techniques are introduced that allow easy integration of the proposed scheme with the state-of-the-art test generation and application methods. In particular, the new scheme uses redesigned scan cells to dynamically configure scan chains into different modes of operation for use with the underlying test-per-clock principle. Experimental results obtained for large and complex industrial ASIC designs illustrate feasibility of the proposed test schemes and are reported herein.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117341996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Satyadev Ahlawat, Jaynarayan T. Tudu, A. Matrosova, Virendra Singh
The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits.
{"title":"A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan","authors":"Satyadev Ahlawat, Jaynarayan T. Tudu, A. Matrosova, Virendra Singh","doi":"10.1109/ATS.2015.12","DOIUrl":"https://doi.org/10.1109/ATS.2015.12","url":null,"abstract":"The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational depth decreases, the performance degradation caused by scan multiplexer delay become more critical. Elimination of the scan multiplexer delay off the functional path has become crucial in maintaining the circuit performance. In this work we propose a new transistor level scan cell design to eliminate the scan multiplexer off the functional path. The proposed scan cell uses separate master latch for functional and test mode where as the slave latch is same in both the modes. Our proposed scan flip-flop fully comply with the conventional test flow. Post layout experimental results justify the effectiveness of the proposed scan cell design in eliminating the performance penalty of scan, and thus in improving the timing performance of integrated circuits.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115464875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Integrated circuits are being used in different applications which are not always known at the time of specification and design creation. Safety standards specify that certain design processes be followed to guarantee safety of the applications in which these circuits are being used. As a result, the design phase is followed (often mandated) by an evaluation phase, wherein the safety worthiness of the circuit must be ascertained. In this paper, we perform a detailed study of such an evaluation as practised in the industry, understand the limitations, and propose techniques to improve the existing methodology. The improvements proposed are: (i) Capturing workload diversity as input constraints (values and sequence). (ii) Modelling application specific performance tolerance. (iii) Illustrating how physical system can be included into this analysis using a suitable representation. (iv) Budgeting of tolerance across various interacting modules to reduce computational complexity of safety analysis. Experimental results to illustrate suitability of the proposed methods are presented using a set of ITC benchmark circuits and two representative industrial circuits.
{"title":"Improved Methods for Accurate Safety Analysis of Real-Life Systems","authors":"V. Prasanth, R. Parekhji, B. Amrutur","doi":"10.1109/ATS.2015.37","DOIUrl":"https://doi.org/10.1109/ATS.2015.37","url":null,"abstract":"Integrated circuits are being used in different applications which are not always known at the time of specification and design creation. Safety standards specify that certain design processes be followed to guarantee safety of the applications in which these circuits are being used. As a result, the design phase is followed (often mandated) by an evaluation phase, wherein the safety worthiness of the circuit must be ascertained. In this paper, we perform a detailed study of such an evaluation as practised in the industry, understand the limitations, and propose techniques to improve the existing methodology. The improvements proposed are: (i) Capturing workload diversity as input constraints (values and sequence). (ii) Modelling application specific performance tolerance. (iii) Illustrating how physical system can be included into this analysis using a suitable representation. (iv) Budgeting of tolerance across various interacting modules to reduce computational complexity of safety analysis. Experimental results to illustrate suitability of the proposed methods are presented using a set of ITC benchmark circuits and two representative industrial circuits.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128051664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang
As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.
{"title":"Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction","authors":"Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang","doi":"10.1109/ATS.2015.8","DOIUrl":"https://doi.org/10.1109/ATS.2015.8","url":null,"abstract":"As a scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of scan cells lead to excessive power consumption and it produces a low shifting frequency during the scan shifting mode. In this paper, we present a new scan shift power reduction method based on a scan chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the scan shift power, just a little routing overhead. Experimental results show that this method improves scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132088004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a test infrastructure development and test scheduling strategy for 3D-SICs under resource (test pins and TSVs) and power constraints. Depending upon the various scheduling restrictions, two test scheduling strategies have been proposed with an objective to minimize the overall test time (TT) of the stack. A step-by-step approach deals with the individual dies separately and develops power-restricted test schedules for each die and finally decides test concurrency between the dies satisfying the resources and power limits of the stack. Particle Swarm Optimization (PSO) based meta search technique has been used to select the resource allocation and power distribution to individual dies and also their internal test schedules. Incorporation of PSO in two stages of optimization produces a notable reduction in the overall test time of the SIC. Another integrated approach uses PSO to generate power-constrained test schedule of the entire SIC in a single optimization step. Integrated approach produces better results than the step-by-step approach because of its higher flexibility with lesser restrictions. User may select any of the scheduling strategies depending upon the scheduling criteria.
{"title":"Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints","authors":"R. Karmakar, Aditya Agarwal, S. Chattopadhyay","doi":"10.1109/ATS.2015.20","DOIUrl":"https://doi.org/10.1109/ATS.2015.20","url":null,"abstract":"This paper presents a test infrastructure development and test scheduling strategy for 3D-SICs under resource (test pins and TSVs) and power constraints. Depending upon the various scheduling restrictions, two test scheduling strategies have been proposed with an objective to minimize the overall test time (TT) of the stack. A step-by-step approach deals with the individual dies separately and develops power-restricted test schedules for each die and finally decides test concurrency between the dies satisfying the resources and power limits of the stack. Particle Swarm Optimization (PSO) based meta search technique has been used to select the resource allocation and power distribution to individual dies and also their internal test schedules. Incorporation of PSO in two stages of optimization produces a notable reduction in the overall test time of the SIC. Another integrated approach uses PSO to generate power-constrained test schedule of the entire SIC in a single optimization step. Integrated approach produces better results than the step-by-step approach because of its higher flexibility with lesser restrictions. User may select any of the scheduling strategies depending upon the scheduling criteria.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115946503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Kampmann, M. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H. Wunderlich
Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit's behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.
{"title":"Optimized Selection of Frequencies for Faster-Than-at-Speed Test","authors":"M. Kampmann, M. Kochte, E. Schneider, T. Indlekofer, S. Hellebrand, H. Wunderlich","doi":"10.1109/ATS.2015.26","DOIUrl":"https://doi.org/10.1109/ATS.2015.26","url":null,"abstract":"Small gate delay faults (SDFs) are not detectable at-speed, if they can only be propagated along short paths. These hidden delay faults (HDFs) do not influence the circuit's behavior initially, but they may indicate design marginalities leading to early-life failures, and therefore they cannot be neglected. HDFs can be detected by faster-than-at-speed test (FAST), where typically several different frequencies are used to maximize the coverage. A given set of test patterns P potentially detects a HDF if it contains a test pattern sensitizing a path through the fault site, and the efficiency of FAST can be measured as the ratio of actually detected HDFs to potentially detected HDFs. The paper at hand targets maximum test efficiency with a minimum number of frequencies. The procedure starts with a test set for transition delay faults and a set of preselected equidistant frequencies. Timing-accurate simulation of this initial setup identifies the hard-to-detect faults, which are then targeted by a more complex timing-aware ATPG procedure. For the yet undetected HDFs, a minimum number of frequencies are determined using an efficient hypergraph algorithm. Experimental results show that with this approach, the number of test frequencies required for maximum test efficiency can be reduced considerably. Furthermore, test set inflation is limited as timing-aware ATPG is only used for a small subset of HDFs.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116191142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dooyoung Kim, M. A. Ansari, Jihun Jung, Sungju Park
The scan PUF, which is based-on the power-up states of scan flip-flops, had been proposed to overcome security issues of semiconductor ICs. IC identification, one of those security issues, requires decent uniqueness along with reliability and randomness. This paper presents two efficient PUF elements' selection methods for scan PUF: uniqueunanimous selection method and unique-majority selection method. These methods classify the scan cells according to their trend of power-up states and prioritize them to extract PUF elements. For experiments, enrollment and validation is performed on 15 chips, which are fabricated with 65nm CMOS process. A statistical analysis on experiments verifies the performance of proposed selection methods.
{"title":"Scan-Puf: Puf Elements Selection Methods for Viable IC Identification","authors":"Dooyoung Kim, M. A. Ansari, Jihun Jung, Sungju Park","doi":"10.1109/ATS.2015.28","DOIUrl":"https://doi.org/10.1109/ATS.2015.28","url":null,"abstract":"The scan PUF, which is based-on the power-up states of scan flip-flops, had been proposed to overcome security issues of semiconductor ICs. IC identification, one of those security issues, requires decent uniqueness along with reliability and randomness. This paper presents two efficient PUF elements' selection methods for scan PUF: uniqueunanimous selection method and unique-majority selection method. These methods classify the scan cells according to their trend of power-up states and prioritize them to extract PUF elements. For experiments, enrollment and validation is performed on 15 chips, which are fabricated with 65nm CMOS process. A statistical analysis on experiments verifies the performance of proposed selection methods.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116965263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jun Zhou, Huawei Li, Tiancheng Wang, Sen Li, Ying Wang, Xiaowei Li
Network-on-chip (NoC) is a major communication technique for 3D integrated circuits (ICs). In order to achieve higher throughput and lower latency with less system cost, horizontal and vertical wireless links are adopted to apply in the 3D NoCs. So far, the reliable routing scheme has been regarded as a lightweight and high-efficiency mechanism to guarantee the performance of the faulty 2D/3D NoCs. In this paper, we propose a low-overhead turn-guided reliable routing scheme named TWiN for the vertical link faults in wireless 3D NoCs. TWiN is deadlock-free without any virtual channels (VCs). Experimental results show that TWiN possesses higher performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing scheme for wireless 3D NoCs.
{"title":"TWiN: A Turn-Guided Reliable Routing Scheme for Wireless 3D NoCs","authors":"Jun Zhou, Huawei Li, Tiancheng Wang, Sen Li, Ying Wang, Xiaowei Li","doi":"10.1109/ATS.2015.22","DOIUrl":"https://doi.org/10.1109/ATS.2015.22","url":null,"abstract":"Network-on-chip (NoC) is a major communication technique for 3D integrated circuits (ICs). In order to achieve higher throughput and lower latency with less system cost, horizontal and vertical wireless links are adopted to apply in the 3D NoCs. So far, the reliable routing scheme has been regarded as a lightweight and high-efficiency mechanism to guarantee the performance of the faulty 2D/3D NoCs. In this paper, we propose a low-overhead turn-guided reliable routing scheme named TWiN for the vertical link faults in wireless 3D NoCs. TWiN is deadlock-free without any virtual channels (VCs). Experimental results show that TWiN possesses higher performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing scheme for wireless 3D NoCs.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132900717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In some complex deep sub-micron designs, the variations in interconnect delay has a significant impact on the production yield of the product. In this paper, we develop a theoretical explanation for the unexpectedly higher process related timing variability shown by long interconnects that are driven by high drive strength gates. This gets even worse due to conventional gate delay variability and other random process effects. Our analysis is supported by actual silicon data and further validated by detailed Monte-Carlo (MC) simulations. Unfortunately, traditional scan based transition delay fault (TDF) timing tests can miss these variability induced delay faults on long interconnects which lies on the critical paths. We propose a methodology to identify high variability paths dominated by such long interconnects, with the aim of developing high quality delay timing tests. Specifically, we develop a heuristic based path selection algorithm to identify potentially slow paths that can contribute to test escapes in production. We further extend our approach to generate high quality delay timing tests for the target paths using the proposed "three pass" method.
{"title":"A Methodology for Identifying High Timing Variability Paths in Complex Designs","authors":"Virendra Singh, A. Singh, K. Saluja","doi":"10.1109/ATS.2015.27","DOIUrl":"https://doi.org/10.1109/ATS.2015.27","url":null,"abstract":"In some complex deep sub-micron designs, the variations in interconnect delay has a significant impact on the production yield of the product. In this paper, we develop a theoretical explanation for the unexpectedly higher process related timing variability shown by long interconnects that are driven by high drive strength gates. This gets even worse due to conventional gate delay variability and other random process effects. Our analysis is supported by actual silicon data and further validated by detailed Monte-Carlo (MC) simulations. Unfortunately, traditional scan based transition delay fault (TDF) timing tests can miss these variability induced delay faults on long interconnects which lies on the critical paths. We propose a methodology to identify high variability paths dominated by such long interconnects, with the aim of developing high quality delay timing tests. Specifically, we develop a heuristic based path selection algorithm to identify potentially slow paths that can contribute to test escapes in production. We further extend our approach to generate high quality delay timing tests for the target paths using the proposed \"three pass\" method.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125723070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：