K. Shibin, V. Chickermane, B. Keller, C. Papameletis, E. Marinissen
Inter-die connections in 2.5D-and 3D-stacked ICs require at-speed testing as their dynamic performance is crucial to the performance of the stack as a whole. In order to test at mission-mode speed and benefit from the already existing clock distribution network, our at-speed test approach for inter-die connections targets the entire register-to-register path that includes the interconnect. This forces the launching and capturing wrapper cells to be shared with functional flip-flops. In some designs, this unavoidably leads to some 'shore logic': a, typically small, amount of combinational logic outside the die's wrapper boundary register. This paper describes how we have adapted a previously developed 3D-DfT architecture and corresponding EDA tool flows to support at-speed interconnect testing, also in the presence of such 'shore logic'. The adaptations affect the DfT insertion of wrapper cells, the boundary model extraction, and the interconnect test pattern generation.
{"title":"At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic","authors":"K. Shibin, V. Chickermane, B. Keller, C. Papameletis, E. Marinissen","doi":"10.1109/ATS.2015.21","DOIUrl":"https://doi.org/10.1109/ATS.2015.21","url":null,"abstract":"Inter-die connections in 2.5D-and 3D-stacked ICs require at-speed testing as their dynamic performance is crucial to the performance of the stack as a whole. In order to test at mission-mode speed and benefit from the already existing clock distribution network, our at-speed test approach for inter-die connections targets the entire register-to-register path that includes the interconnect. This forces the launching and capturing wrapper cells to be shared with functional flip-flops. In some designs, this unavoidably leads to some 'shore logic': a, typically small, amount of combinational logic outside the die's wrapper boundary register. This paper describes how we have adapted a previously developed 3D-DfT architecture and corresponding EDA tool flows to support at-speed interconnect testing, also in the presence of such 'shore logic'. The adaptations affect the DfT insertion of wrapper cells, the boundary model extraction, and the interconnect test pattern generation.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"426 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132102282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Kochte, Atefe Dalirsani, Andrea Bernabei, M. Omaña, C. Metra, H. Wunderlich
Failure diagnosis of field returns typically requires high quality test stimuli and assumes that tests can be repeated. For intermittent faults with fault activation conditions depending on the physical environment, the repetition of tests cannot ensure that the behavior in the field is also observed during diagnosis, causing field returns diagnosed as no-trouble-found. In safety critical applications, self-checking circuits, which provide concurrent error detection, are frequently used. To diagnose intermittent and transient faulty behavior in such circuits, we use the stored encoded circuit outputs in case of a failure (called signatures) for later analysis in diagnosis. For the first time, a diagnosis algorithm is presented that is capable of performing the classification of intermittent or transient faults using only the very limited amount of functional stimuli and signatures observed during operation and stored on chip. The experimental results demonstrate that even with these harsh limitations it is possible to distinguish intermittent from transient faulty behavior. This is essential to determine whether a circuit in which failures have been observed should be subject to later physical failure analysis, since intermittent faulty behavior has been diagnosed. In case of transient faulty behavior, it may still be operated reliably.
{"title":"Intermittent and Transient Fault Diagnosis on Sparse Code Signatures","authors":"M. Kochte, Atefe Dalirsani, Andrea Bernabei, M. Omaña, C. Metra, H. Wunderlich","doi":"10.1109/ATS.2015.34","DOIUrl":"https://doi.org/10.1109/ATS.2015.34","url":null,"abstract":"Failure diagnosis of field returns typically requires high quality test stimuli and assumes that tests can be repeated. For intermittent faults with fault activation conditions depending on the physical environment, the repetition of tests cannot ensure that the behavior in the field is also observed during diagnosis, causing field returns diagnosed as no-trouble-found. In safety critical applications, self-checking circuits, which provide concurrent error detection, are frequently used. To diagnose intermittent and transient faulty behavior in such circuits, we use the stored encoded circuit outputs in case of a failure (called signatures) for later analysis in diagnosis. For the first time, a diagnosis algorithm is presented that is capable of performing the classification of intermittent or transient faults using only the very limited amount of functional stimuli and signatures observed during operation and stored on chip. The experimental results demonstrate that even with these harsh limitations it is possible to distinguish intermittent from transient faulty behavior. This is essential to determine whether a circuit in which failures have been observed should be subject to later physical failure analysis, since intermittent faulty behavior has been diagnosed. In case of transient faulty behavior, it may still be operated reliably.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127888274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Semiconductor industry has been aggressively following the Moore's Law ever since its was proposed in the late sixties in its pursuit for smaller device sizes and higher performance metrics. However, this vigorous scaling has brought in several scaling induced side effects like single event upsets into the technology regime. SRAMs are highly susceptible to such upsets since they are designed at minimum device sizes to keep the on-chip memory density high. This paper presents a novel SEU-hardened SRAM cell employing single bitline. The proposed cell is 4 times more immune than a standard 6T-SRAM cell and also achieves 68% reduction in bitline leakage.
{"title":"A Soft Error Resilient Low Leakage SRAM Cell Design","authors":"M. AdithyalalP., S. Balachandran, Virendra Singh","doi":"10.1109/ATS.2015.30","DOIUrl":"https://doi.org/10.1109/ATS.2015.30","url":null,"abstract":"Semiconductor industry has been aggressively following the Moore's Law ever since its was proposed in the late sixties in its pursuit for smaller device sizes and higher performance metrics. However, this vigorous scaling has brought in several scaling induced side effects like single event upsets into the technology regime. SRAMs are highly susceptible to such upsets since they are designed at minimum device sizes to keep the on-chip memory density high. This paper presents a novel SEU-hardened SRAM cell employing single bitline. The proposed cell is 4 times more immune than a standard 6T-SRAM cell and also achieves 68% reduction in bitline leakage.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sabyasachi Deyati, B. Muldrey, A. Singh, A. Chatterjee
In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures for silicon authentication. While prior PUF designs have been largely digital, in this work we propose a novel PUF design based on transfer function variability of an analog push-pull amplifier under process variations. A differential amplifier architecture is proposed with digital interfaces to allow the PUF to be used in digital as well as mixed-signal SoCs. A key innovation is digital stimulus engineering for the analog amplifier that allows 2X improvements in the uniqueness of IC signatures generated over arbiter-based digital PUF architectures, while maintaining high signature reliability over +/- 10 % voltage and -20 to 120 degree Celsius temperature variation. The proposed PUF is also resistive to model building attacks as the internal analog operation of the PUF is difficult to reverse-engineer due to the continuum of internal states involved. We show the benefits of the proposed PUF through comparison with a traditional arbiter-based digital PUF using simulation experiments.
{"title":"Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security","authors":"Sabyasachi Deyati, B. Muldrey, A. Singh, A. Chatterjee","doi":"10.1109/ATS.2015.29","DOIUrl":"https://doi.org/10.1109/ATS.2015.29","url":null,"abstract":"In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures for silicon authentication. While prior PUF designs have been largely digital, in this work we propose a novel PUF design based on transfer function variability of an analog push-pull amplifier under process variations. A differential amplifier architecture is proposed with digital interfaces to allow the PUF to be used in digital as well as mixed-signal SoCs. A key innovation is digital stimulus engineering for the analog amplifier that allows 2X improvements in the uniqueness of IC signatures generated over arbiter-based digital PUF architectures, while maintaining high signature reliability over +/- 10 % voltage and -20 to 120 degree Celsius temperature variation. The proposed PUF is also resistive to model building attacks as the internal analog operation of the PUF is difficult to reverse-engineer due to the continuum of internal states involved. We show the benefits of the proposed PUF through comparison with a traditional arbiter-based digital PUF using simulation experiments.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116328420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Saikat Dutta, S. Chattopadhyay, A. Banerjee, P. Dasgupta
In this work, we propose a framework for construction of an approximate environment for compositional verification using invariants learned from dynamic traces of the system and the counterexamples generated by a model checker on verifying a property on the component in isolation. We adopt a counterexample ranking methodology for eliminating possibly fictitious counterexamples by choosing a minimal subset of the invariants. We explore the aspect of choosing a threshold for counterexamples as well as assume properties which can contribute towards further refining the subset chosen and produce a stronger abstraction. Experimental results on benchmark designs shows the efficacy of our proposal.
{"title":"A New Approach for Minimal Environment Construction for Modular Property Verification","authors":"Saikat Dutta, S. Chattopadhyay, A. Banerjee, P. Dasgupta","doi":"10.1109/ATS.2015.42","DOIUrl":"https://doi.org/10.1109/ATS.2015.42","url":null,"abstract":"In this work, we propose a framework for construction of an approximate environment for compositional verification using invariants learned from dynamic traces of the system and the counterexamples generated by a model checker on verifying a property on the component in isolation. We adopt a counterexample ranking methodology for eliminating possibly fictitious counterexamples by choosing a minimal subset of the invariants. We explore the aspect of choosing a threshold for counterexamples as well as assume properties which can contribute towards further refining the subset chosen and produce a stronger abstraction. Experimental results on benchmark designs shows the efficacy of our proposal.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124845481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Mandal, S. Sau, A. Chakrabarti, S. Pal, S. Chattopadhyay
There is an immense need of very high speed robust data communication in many critical applications like radar communication, satellite communication, high energy physics experiment (HEP) and biomedical instrumentation etc. Transient errors due to radiation and other environmental hazards are responsible to create some temporary malfunctions in such high speed communication system. Concatenated code can make the high speed communication more robust against transient errors. This paper presents a novel design of latency optimized optical communication system involving orthogonal concatenated code generated through BCH code (named after Raj Bose and D. K. Ray-Chaudhuri) and Hamming code as component code and its efficient implementation on hardware using Kintex-7 FPGA board. Our design optimizes the transmission latency of the system to a great extent and makes it extremely efficient for real time high data rate applications. We have successfully tested our design for board to board communication over latency optimized optical link at ~5 Gbps data rate. Resource utilization, power estimation and bit error rate (BER) of our implemented system are also reported.
在雷达通信、卫星通信、高能物理实验(HEP)和生物医学仪器等许多关键应用中，对高速鲁棒数据通信有着巨大的需求。在这种高速通信系统中，由于辐射和其他环境危害引起的瞬态误差造成了一些暂时的故障。连接代码可以使高速通信对瞬态错误具有更强的鲁棒性。本文提出了一种以BCH码(以Raj Bose和D. K. Ray-Chaudhuri的名字命名)和汉明码作为组件码生成正交级联码的延迟优化光通信系统的新设计，并利用Kintex-7 FPGA板在硬件上高效实现。我们的设计在很大程度上优化了系统的传输延迟，使其在实时高数据速率应用中非常高效。我们已经成功地测试了我们的设计，在延迟优化的光链路上，以~ 5gbps的数据速率进行板对板通信。文中还报道了系统的资源利用率、功率估计和误码率。
{"title":"FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code","authors":"S. Mandal, S. Sau, A. Chakrabarti, S. Pal, S. Chattopadhyay","doi":"10.1109/ATS.2015.36","DOIUrl":"https://doi.org/10.1109/ATS.2015.36","url":null,"abstract":"There is an immense need of very high speed robust data communication in many critical applications like radar communication, satellite communication, high energy physics experiment (HEP) and biomedical instrumentation etc. Transient errors due to radiation and other environmental hazards are responsible to create some temporary malfunctions in such high speed communication system. Concatenated code can make the high speed communication more robust against transient errors. This paper presents a novel design of latency optimized optical communication system involving orthogonal concatenated code generated through BCH code (named after Raj Bose and D. K. Ray-Chaudhuri) and Hamming code as component code and its efficient implementation on hardware using Kintex-7 FPGA board. Our design optimizes the transmission latency of the system to a great extent and makes it extremely efficient for real time high data rate applications. We have successfully tested our design for board to board communication over latency optimized optical link at ~5 Gbps data rate. Resource utilization, power estimation and bit error rate (BER) of our implemented system are also reported.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125010801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. Kochte, E. Schneider, H. Wunderlich, J. Qian
IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.
{"title":"Logic/Clock-Path-Aware At-Speed Scan Test Generation for Avoiding False Capture Failures and Reducing Clock Stretch","authors":"K. Asada, X. Wen, S. Holst, K. Miyase, S. Kajihara, M. Kochte, E. Schneider, H. Wunderlich, J. Qian","doi":"10.1109/ATS.2015.25","DOIUrl":"https://doi.org/10.1109/ATS.2015.25","url":null,"abstract":"IR-drop induced by launch switching activity (LSA) in capture mode during at-speed scan testing increases delay along not only logic paths (LPs) but also clock paths (Cps). Excessive extra delay along LPs compromises test yields due to false capture failures, while excessive extra delay along CPs compromises test quality due to test clock stretch. This paper is the first to mitigate the impact of LSA on both LPs and CPs with a novel LCPA (Logic/Clock Path-Aware) at-speed scan test generation scheme, featuring (1) a new metric for assessing the risk of false capture failures based on the amount of LSA around both LPs and CPs, (2) a procedure for avoiding false capture failures by reducing LSA around LPs or masking uncertain test responses, and (3) a procedure for reducing test clock stretch by reducing LSA around CPs. Experimental results demonstrate the effectiveness of the LCPA scheme in improving test yields and test quality.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116528146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wide-I/O dynamic random access memory (wide I/O DRAM) is one of promising solutions to increase the memory bandwidth. Similar to modern double-data-rate DRAMs, the minimum burst length of wide I/O DRAM is at least two. Thus, either a read or a write operation is executed, two words will be read or written at least each time. This causes that the testing of inter-word coupling faults becomes complicated. In this paper, we propose a method to modify conventional March tests into modified March tests which can fully cover inter-word coupling faults of wide I/O DRAMs with minimum burst length of two and programmable burst order. Furthermore, the test complexity of modified March tests for different burst lengths is analyzed. Results show that the test time of modified March tests is the shortest if the longest burst length is set to apply the modified March tests. Results of fault coverage analysis show that the modified March test can provide 100% fault coverage of simple inter-word coupling faults.
{"title":"Testing Inter-Word Coupling Faults of Wide I/O DRAMs","authors":"Che-Wei Chou, Yong-Xiao Chen, Jin-Fu Li","doi":"10.1109/ATS.2015.19","DOIUrl":"https://doi.org/10.1109/ATS.2015.19","url":null,"abstract":"Wide-I/O dynamic random access memory (wide I/O DRAM) is one of promising solutions to increase the memory bandwidth. Similar to modern double-data-rate DRAMs, the minimum burst length of wide I/O DRAM is at least two. Thus, either a read or a write operation is executed, two words will be read or written at least each time. This causes that the testing of inter-word coupling faults becomes complicated. In this paper, we propose a method to modify conventional March tests into modified March tests which can fully cover inter-word coupling faults of wide I/O DRAMs with minimum burst length of two and programmable burst order. Furthermore, the test complexity of modified March tests for different burst lengths is analyzed. Results show that the test time of modified March tests is the shortest if the longest burst length is set to apply the modified March tests. Results of fault coverage analysis show that the modified March test can provide 100% fault coverage of simple inter-word coupling faults.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132703209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Kimi, Go Matsukawa, Shuhei Yoshida, S. Izumi, H. Kawaguchi, M. Yoshimoto
As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.
{"title":"Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path","authors":"Y. Kimi, Go Matsukawa, Shuhei Yoshida, S. Izumi, H. Kawaguchi, M. Yoshimoto","doi":"10.1109/ATS.2015.31","DOIUrl":"https://doi.org/10.1109/ATS.2015.31","url":null,"abstract":"As technology nodes continue to shrink, the impact of radiation-induced soft error on processor reliability increases. Estimation of processor reliability and identification of vulnerable flip-flops requires accurate soft error rate (SER) analysis techniques. This paper presents a proposal for a soft error propagation analysis technique. We specifically examine single event upset (SEU) occurring at a flip-flop in sequential circuits. When SEUs propagate in sequential circuits, the faults can be masked temporally and logically. Conventional soft error propagation analysis techniques do not consider error convergent timing on re-convergent paths. The proposed technique can analyze soft error propagation while considering error-convergent timing on a re-convergent path by combinational analysis of temporal and logical effects. The proposed technique also considers the case in which the temporal masking is disabled with an enable signal of the erroneous flip-flop negated. Experimental results show that the proposed technique improves inaccuracy by 70.5%, on average, compared with conventional techniques using ITC 99 and ISCAS 89 benchmark circuits when the enable probability is 1/3, while the runtime overhead is only 1.7% on average.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116709528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, C. Li
A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.
{"title":"Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits","authors":"Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, C. Li","doi":"10.1109/ATS.2015.38","DOIUrl":"https://doi.org/10.1109/ATS.2015.38","url":null,"abstract":"A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130430966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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