As technology scales down, the density of SRAM devices increases drastically, and their storage capacity grows at the same time. Moreover, SRAMs become more prone to physical defects in each technology node, which therefore increases the need of effective tests with high fault coverage. It has been shown that resistive-bridging defects induce coupling faults that may increase defective parts per million levels if not well covered during manufacturing test. In this work, we study the reuse of read and write assist techniques, commonly applied to improve the functional margins of SRAM core-cells, to improve the coverage of coupling faults. This analysis is based on extensive injection of resistive bridging defects in core-cells of a commercial low-power SRAM. We show that assist circuits can be leveraged to increase the sensitization of defects causing coupling faults by 10-12%, however, they need to be used carefully.
{"title":"On the Use of Assist Circuits for Improved Coupling Fault Detection in SRAMs","authors":"Josef Kinseher, L. Zordan, I. Polian","doi":"10.1109/ATS.2015.18","DOIUrl":"https://doi.org/10.1109/ATS.2015.18","url":null,"abstract":"As technology scales down, the density of SRAM devices increases drastically, and their storage capacity grows at the same time. Moreover, SRAMs become more prone to physical defects in each technology node, which therefore increases the need of effective tests with high fault coverage. It has been shown that resistive-bridging defects induce coupling faults that may increase defective parts per million levels if not well covered during manufacturing test. In this work, we study the reuse of read and write assist techniques, commonly applied to improve the functional margins of SRAM core-cells, to improve the coverage of coupling faults. This analysis is based on extensive injection of resistive bridging defects in core-cells of a commercial low-power SRAM. We show that assist circuits can be leveraged to increase the sensitization of defects causing coupling faults by 10-12%, however, they need to be used carefully.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123758683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ashwin Chintaluri, A. Parihar, S. Natarajan, Helia Naeimi, A. Raychowdhury
There has been a significant interest in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) as a candidate for emerging memory technology for last-level embedded caches in the recent years. High density (3-4x of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS are the attractive properties of this technology. A few studies have expounded on the reliability in this technology but various fault manifestations have not been studied in detail in the past. This paper attempts to study the fault models in STT-MRAM under both parametric variations as well as electrical defects (opens and shorts). Sensitivity of Read, Write and Retention to material and lithographic process parameters has been studied. Also electrical defects viz. intra-cell and inter-cell opens and shorts have been considered and the corresponding fault models have been identified and classified.
{"title":"A Model Study of Defects and Faults in Embedded Spin Transfer Torque (STT) MRAM Arrays","authors":"Ashwin Chintaluri, A. Parihar, S. Natarajan, Helia Naeimi, A. Raychowdhury","doi":"10.1109/ATS.2015.39","DOIUrl":"https://doi.org/10.1109/ATS.2015.39","url":null,"abstract":"There has been a significant interest in Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) as a candidate for emerging memory technology for last-level embedded caches in the recent years. High density (3-4x of SRAM), non-volatility, nano-second Read and Write speeds, and process and voltage compatibility with CMOS are the attractive properties of this technology. A few studies have expounded on the reliability in this technology but various fault manifestations have not been studied in detail in the past. This paper attempts to study the fault models in STT-MRAM under both parametric variations as well as electrical defects (opens and shorts). Sensitivity of Read, Write and Retention to material and lithographic process parameters has been studied. Also electrical defects viz. intra-cell and inter-cell opens and shorts have been considered and the corresponding fault models have been identified and classified.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131435902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
IEEE 1687-2014 Standard provides an effective method for accessing on-chip instruments for testing, debugging and board configuration. The standard, however, causes a safety problem because anyone can access the chip instruments, set inputs and obtain safety critical information. In recent work, a lock in the segment insertion bit (SIB) and a corresponding unlocking key application procedure have been proposed for securing the 1687. This paper provides a linear feedback shift register (LFSR) based key generation mechanism that enhances the security of 1687 very significantly. By reconfiguring m (a small number) scan flip-flops into an LFSR that generates the key to unlock the SIB, we show a substantial increase in the expected break-in time.
{"title":"Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key","authors":"Hejia Liu, V. Agrawal","doi":"10.1109/ATS.2015.23","DOIUrl":"https://doi.org/10.1109/ATS.2015.23","url":null,"abstract":"IEEE 1687-2014 Standard provides an effective method for accessing on-chip instruments for testing, debugging and board configuration. The standard, however, causes a safety problem because anyone can access the chip instruments, set inputs and obtain safety critical information. In recent work, a lock in the segment insertion bit (SIB) and a corresponding unlocking key application procedure have been proposed for securing the 1687. This paper provides a linear feedback shift register (LFSR) based key generation mechanism that enhances the security of 1687 very significantly. By reconfiguring m (a small number) scan flip-flops into an LFSR that generates the key to unlock the SIB, we show a substantial increase in the expected break-in time.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130096005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep-submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation at the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to reduce the number of transitions on FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT solvers thatconducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient betweentransitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.
{"title":"A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions","authors":"Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa","doi":"10.1109/ATS.2015.10","DOIUrl":"https://doi.org/10.1109/ATS.2015.10","url":null,"abstract":"High power dissipation can occur by high launch-induced switching activity when the response to a test pattern is captured by flip-flops (FFs) in at-speed scan testing, resulting in excessive IR drop. IR drop may cause significant capture-induced yield loss in the deep-submicron era. It is known that test modification methods using X-identification and X-filling are effective to reduce power dissipation at the capture cycle. Conventional low power dissipation oriented X-filling methods consecutively select FFs and assign values to reduce the number of transitions on FFs. In this paper, we propose a novel low power dissipation oriented X-filling method using SAT solvers thatconducts simultaneous X-filling for some FFs. We also proposed a selection order of FFs based on a correlation coefficient betweentransitions of FFs and power dissipation. Experimental results show that the proposed method was effective for ISCAS'89 and ITC'99 benchmark circuits compared with justification-probability-based fill.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124988475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Error correction code (ECC) and hard repair (built-in self-repair) techniques by using redundancies have been widely used for improving the yield and reliability of memories. The target faults of these two schemes are soft errors and permanent faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneously. However, this will compromise reliability since some of the ECC protection capability is used for repairing hard defects. To cure this dilemma, we propose an ECC-enhanced BISR (EBISR) technique which uses ECC to repair single permanent faults first and spares for the remaining faults in the production/power-on test and repair stage. However, techniques are proposed to maintain the original reliability during the on-line test and repair stage. We also propose the corresponding hardware architecture of the EBISR scheme. A simulator is implemented to evaluate the hardware overhead, repair rate, and reliability. Experimental results show that the proposed EBISR scheme can improve yield and reliability significantly with negligible hardware overhead.
{"title":"Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories","authors":"Shyue-Kung Lu, Cheng-Ju Tsai, M. Hashizume","doi":"10.1109/ATS.2015.16","DOIUrl":"https://doi.org/10.1109/ATS.2015.16","url":null,"abstract":"Error correction code (ECC) and hard repair (built-in self-repair) techniques by using redundancies have been widely used for improving the yield and reliability of memories. The target faults of these two schemes are soft errors and permanent faults, respectively. In recent works, there are also some techniques integrating ECC and BISR to deal with soft errors and hard defects simultaneously. However, this will compromise reliability since some of the ECC protection capability is used for repairing hard defects. To cure this dilemma, we propose an ECC-enhanced BISR (EBISR) technique which uses ECC to repair single permanent faults first and spares for the remaining faults in the production/power-on test and repair stage. However, techniques are proposed to maintain the original reliability during the on-line test and repair stage. We also propose the corresponding hardware architecture of the EBISR scheme. A simulator is implemented to evaluate the hardware overhead, repair rate, and reliability. Experimental results show that the proposed EBISR scheme can improve yield and reliability significantly with negligible hardware overhead.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127430302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/ATS.2015.8125669
Joyati Mondal, D. K. Das, B. Bhattacharya
The emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low-power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ⩾ 1. While analyzing testability issues in a reversible circuit, the missing-gate fault model is often used for modeling physical defects in quantum k-CNOT gates. In this paper, we propose a new design-for-testability (DFT) technique for quantum reversible circuits that deploys bit-swapping using Fredkin gates. It is shown that in an (n x n) circuit implemented with k-CNOT gates, addition of only two extra inputs along with a few Fredkin gates yields easy testability in the circuit. The modified design admits a universal test set of size (n + k + 2) that detects all detectable missing gate faults in the original circuit, where k is the maximum number of controls used among all k-CNOT gates. The DFT overhead in terms of quantum cost is also much less compared to previous approaches.
可逆电路的新兴技术为超低功耗量子计算系统的合成提供了一个潜在的解决方案。可逆电路可以设想为可逆门的级联，例如Toffoli门，它具有两个组件:k控制位和目标位(k- cnot)， k大于或等于1。在分析可逆电路的可测试性问题时，经常使用缺门故障模型来模拟量子k-CNOT门的物理缺陷。在本文中，我们提出了一种新的可测试性设计(DFT)技术，用于使用弗雷德金门部署位交换的量子可逆电路。结果表明，在使用k-CNOT门实现的(n x n)电路中，仅添加两个额外输入以及几个弗雷德金门就可以在电路中易于测试。修改后的设计允许一个通用测试集(n + k + 2)，该测试集可以检测原始电路中所有可检测的缺失门故障，其中k是所有k- cnot门中使用的最大控制数。与以前的方法相比，DFT在量子成本方面的开销也少得多。
{"title":"Design-for-testability in reversible logic circuits based on bit-swapping","authors":"Joyati Mondal, D. K. Das, B. Bhattacharya","doi":"10.1109/ATS.2015.8125669","DOIUrl":"https://doi.org/10.1109/ATS.2015.8125669","url":null,"abstract":"The emerging technology of reversible circuits offers a potential solution to the synthesis of ultra low-power quantum computing systems. A reversible circuit can be envisaged as a cascade of reversible gates only, such as Toffoli gate, which has two components: k control bits and a target bit (k-CNOT), k ⩾ 1. While analyzing testability issues in a reversible circuit, the missing-gate fault model is often used for modeling physical defects in quantum k-CNOT gates. In this paper, we propose a new design-for-testability (DFT) technique for quantum reversible circuits that deploys bit-swapping using Fredkin gates. It is shown that in an (n x n) circuit implemented with k-CNOT gates, addition of only two extra inputs along with a few Fredkin gates yields easy testability in the circuit. The modified design admits a universal test set of size (n + k + 2) that detects all detectable missing gate faults in the original circuit, where k is the maximum number of controls used among all k-CNOT gates. The DFT overhead in terms of quantum cost is also much less compared to previous approaches.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133551848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/ATS.2015.7447934
R. Cantoro, Mehrdad Montazeri, M. Reorda, Farrokh Ghani Zadegan, E. Larsson
Due to the increasing usage of embedded instruments in many electronic devices, new solutions to effectively access these instruments appeared, including the new IEEE 1687 standard. The approach supported by IEEE 1687 allows a flexible access to embedded instruments through the Boundary Scan interface. The IEEE 1687 network includes a set of reconfigurable scan chains. This paper addresses the issue of testing the circuitry implementing them, checking whether any permanent hardware fault exists, affecting either the registers associated to the instruments made accessible by the network, or the configuration structures it embeds (e.g., the multiplexers and the associated flip-flops). The paper proposes an approach, in which the IEEE 1687 network undergoes a sequence of test sessions, each composed of a configuration phase and a test phase. By properly selecting the network configurations to be used, we can guarantee that the method can test any permanent fault possibly affecting the network. We also provide some experimental results gathered on a set of benchmark networks, allowing to practically evaluate the viability of the approach.
{"title":"On the testability of IEEE 1687 networks","authors":"R. Cantoro, Mehrdad Montazeri, M. Reorda, Farrokh Ghani Zadegan, E. Larsson","doi":"10.1109/ATS.2015.7447934","DOIUrl":"https://doi.org/10.1109/ATS.2015.7447934","url":null,"abstract":"Due to the increasing usage of embedded instruments in many electronic devices, new solutions to effectively access these instruments appeared, including the new IEEE 1687 standard. The approach supported by IEEE 1687 allows a flexible access to embedded instruments through the Boundary Scan interface. The IEEE 1687 network includes a set of reconfigurable scan chains. This paper addresses the issue of testing the circuitry implementing them, checking whether any permanent hardware fault exists, affecting either the registers associated to the instruments made accessible by the network, or the configuration structures it embeds (e.g., the multiplexers and the associated flip-flops). The paper proposes an approach, in which the IEEE 1687 network undergoes a sequence of test sessions, each composed of a configuration phase and a test phase. By properly selecting the network configurations to be used, we can guarantee that the method can test any permanent fault possibly affecting the network. We also provide some experimental results gathered on a set of benchmark networks, allowing to practically evaluate the viability of the approach.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122978459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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