Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350767
N. Balamurugan, K. Sankaranarayanan, M. Suguna, K. Balasubadra, Kalaivani
In this paper, the potential variation in the channel obtained from analytical solution of two-dimensional (2-D) Poisson's equation is used to calculate the drain induced barrier lowering (DIBL) and threshold voltage of SOI MESFETs with uniform doping profile. The two dimensional potential distribution in the active layer of SOI MESFET is approximated as a parabolic function with suitable boundary conditions to obtain the bottom potential at Si/oxide layer interface. The minimum bottom potential is used to monitor the DIBL effect. Further, the model for the bottom potential is extended to derive an analytical model for threshold voltage of SOI MESFET. This model can be used for low power VLSI applications
{"title":"A New Analytic Description of Short-Channel Effects in Fully Depleted Single Gate SOI MESFETs for Low Power VLSI Applications","authors":"N. Balamurugan, K. Sankaranarayanan, M. Suguna, K. Balasubadra, Kalaivani","doi":"10.1109/ICSCN.2007.350767","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350767","url":null,"abstract":"In this paper, the potential variation in the channel obtained from analytical solution of two-dimensional (2-D) Poisson's equation is used to calculate the drain induced barrier lowering (DIBL) and threshold voltage of SOI MESFETs with uniform doping profile. The two dimensional potential distribution in the active layer of SOI MESFET is approximated as a parabolic function with suitable boundary conditions to obtain the bottom potential at Si/oxide layer interface. The minimum bottom potential is used to monitor the DIBL effect. Further, the model for the bottom potential is extended to derive an analytical model for threshold voltage of SOI MESFET. This model can be used for low power VLSI applications","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124237134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350768
K. C. Ray, A. Dhar
Onus of this work is to propose a hardware efficient and flexible ASIC (application specific integrated circuit) architecture for Blackman windowing using CORDIC (co-ordinate rotation digital computer) as building block to minimize the spectral leakage and picket fence effect which are usual phenomena during spectral analysis by truncating input signals for finite length of FFT processor. A purely pipelined architecture has been adopted for the present design to ensure high throughput for real time applications with the latency equal to twice of the number of CORDIC stages plus two. The magnificence of this architecture is that window length can be changed by users for their specific applications and can be updated online for real time applications. The synthesized result of this 16 bit word size architecture with commercially available 0.18 mum CMOS technology using Synopsys Design Analyzer, shows that total estimated dynamic power to be 152 mW with an operating frequency of 125 MHz and total core area 8 mm2 (approx.)
本工作的重点是提出一种硬件高效、灵活的专用集成电路(ASIC)架构，以CORDIC(坐标旋转数字计算机)为基础，通过截断有限长度FFT处理器的输入信号，最大限度地减少频谱分析过程中常见的频谱泄漏和尖桩栅栏效应。本设计采用了纯流水线架构，以确保实时应用程序的高吞吐量，延迟等于CORDIC阶段数量的两倍加上2。这种架构的绝妙之处在于，用户可以根据自己的特定应用程序更改窗口长度，并且可以在线更新实时应用程序。采用Synopsys Design Analyzer的商用0.18 μ m CMOS技术的16位字长架构的综合结果显示，总估计动态功率为152 mW，工作频率为125 MHz，总核心区面积为8 mm2。
{"title":"ASIC Architecture for Implementing Blackman Windowing for Real Time Spectral Analysis","authors":"K. C. Ray, A. Dhar","doi":"10.1109/ICSCN.2007.350768","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350768","url":null,"abstract":"Onus of this work is to propose a hardware efficient and flexible ASIC (application specific integrated circuit) architecture for Blackman windowing using CORDIC (co-ordinate rotation digital computer) as building block to minimize the spectral leakage and picket fence effect which are usual phenomena during spectral analysis by truncating input signals for finite length of FFT processor. A purely pipelined architecture has been adopted for the present design to ensure high throughput for real time applications with the latency equal to twice of the number of CORDIC stages plus two. The magnificence of this architecture is that window length can be changed by users for their specific applications and can be updated online for real time applications. The synthesized result of this 16 bit word size architecture with commercially available 0.18 mum CMOS technology using Synopsys Design Analyzer, shows that total estimated dynamic power to be 152 mW with an operating frequency of 125 MHz and total core area 8 mm2 (approx.)","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114552329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350654
M. Dinesh Chandra, G. Kavitha
The new video coding standard MPEG-4 is enabling content-based functionalities as well as high coding efficiency considering shape information of moving objects. This paper presents a technique for detecting moving objects in a video. This technique consists of three stages-motion estimation, spatial segmentation and motion based region merging. Experimental results using traffic video sequence is presented to demonstrate the accuracy of our proposed algorithm
{"title":"A Novel and Fast Algorithm to Detect Moving Objects for Content Based Applications","authors":"M. Dinesh Chandra, G. Kavitha","doi":"10.1109/ICSCN.2007.350654","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350654","url":null,"abstract":"The new video coding standard MPEG-4 is enabling content-based functionalities as well as high coding efficiency considering shape information of moving objects. This paper presents a technique for detecting moving objects in a video. This technique consists of three stages-motion estimation, spatial segmentation and motion based region merging. Experimental results using traffic video sequence is presented to demonstrate the accuracy of our proposed algorithm","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114947346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350674
A. Sanyal, S. Das, P. Venkateswaran, S. K. Sanyal, R. Nandi
Speech compression is of paramount importance in modern day communications where bandwidth conservation is necessary to accommodate the ever increasing number of communication channels. Historically, LPC (linear predictive coding) is used for speech analysis for better results, and subband coding is used in audio compression methods, such as MPEG standards. In this paper, we combine a RELP (residual excited linear prediction) technique with subband coding to yield compression rates of upto 85% with acceptable distortion levels
{"title":"An Efficient Time Domain Speech Compression Technique and Hardware Implementation on TMS320C5416 Digital Signal Processor","authors":"A. Sanyal, S. Das, P. Venkateswaran, S. K. Sanyal, R. Nandi","doi":"10.1109/ICSCN.2007.350674","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350674","url":null,"abstract":"Speech compression is of paramount importance in modern day communications where bandwidth conservation is necessary to accommodate the ever increasing number of communication channels. Historically, LPC (linear predictive coding) is used for speech analysis for better results, and subband coding is used in audio compression methods, such as MPEG standards. In this paper, we combine a RELP (residual excited linear prediction) technique with subband coding to yield compression rates of upto 85% with acceptable distortion levels","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124017261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350735
P. Varalakshmi, S. Thamarai Selvi, A. Ashraf, K. Karthick
Trust management is an important issue in a grid environment where consumers and service providers are distributed geographically across autonomous administrative domains. In this paper, we propose reputation-based trust management architecture through the use of intermediaries, brokers. This architecture insists on multiple brokers in each domain. The entities (Consumers and the SPs) are distributed across these brokers, with each of these entities being associated with more than one broker. This improves the redundancy of information maintained at the broker sites, thereby improving the reliability. This also eases the network traffic at the broker sites while handling consumer requests and feedbacks. The issues rising out of such an arrangement of multiple brokers, namely the distribution of entities among the brokers and maintenance of consistency of information across the brokers, are addressed well in this paper. Trust-indices of SPs and consumers are evaluated and updated dynamically after the completion of each transaction. This enables the consumer to receive the response from the broker significantly quicker compared to other reputation-based-trust models where the trust-indices are computed at the request-time. To further improve the response time of each transaction, a B-tree indexing scheme has been proposed. Trust parameters such as satisfaction-value, number, cost and criticality of transactions, and different weights for past and recent transactions are considered for the trust evaluation. Our model shows a marked improvement in job success rate for various percentages of malicious entities. The selection query cost for each transaction is reduced thereby improving the overall response time is show-cased in this model. The impact of broker's feedback on the computation of trust-indices is also presented
{"title":"B-Tree Based Trust Model for Resource Selection in Grid","authors":"P. Varalakshmi, S. Thamarai Selvi, A. Ashraf, K. Karthick","doi":"10.1109/ICSCN.2007.350735","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350735","url":null,"abstract":"Trust management is an important issue in a grid environment where consumers and service providers are distributed geographically across autonomous administrative domains. In this paper, we propose reputation-based trust management architecture through the use of intermediaries, brokers. This architecture insists on multiple brokers in each domain. The entities (Consumers and the SPs) are distributed across these brokers, with each of these entities being associated with more than one broker. This improves the redundancy of information maintained at the broker sites, thereby improving the reliability. This also eases the network traffic at the broker sites while handling consumer requests and feedbacks. The issues rising out of such an arrangement of multiple brokers, namely the distribution of entities among the brokers and maintenance of consistency of information across the brokers, are addressed well in this paper. Trust-indices of SPs and consumers are evaluated and updated dynamically after the completion of each transaction. This enables the consumer to receive the response from the broker significantly quicker compared to other reputation-based-trust models where the trust-indices are computed at the request-time. To further improve the response time of each transaction, a B-tree indexing scheme has been proposed. Trust parameters such as satisfaction-value, number, cost and criticality of transactions, and different weights for past and recent transactions are considered for the trust evaluation. Our model shows a marked improvement in job success rate for various percentages of malicious entities. The selection query cost for each transaction is reduced thereby improving the overall response time is show-cased in this model. The impact of broker's feedback on the computation of trust-indices is also presented","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127212181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350723
N. Vasanthal, M. Satyam, K. Subba Rao
It is known that, excessive power dissipation can cause over heating, which reduces the life time of the chip and degrades the circuit performance. Local hot spots occur due to large instantaneous power dissipation. We propose a methodology based on reordering the input vectors to reduce the power dissipated in combinational circuits. Experimental results indicate that the proposed technique achieves reduction in average power, reduction in peak power and reduction in difference between maximum and minimum instantaneous power. In this paper, the results obtained by applying this technique to a specific circuit, an array multiplier are reported. As array multipliers are extensively used in digital signal processing (DSP) applications, we feel that this technique will have far-reaching implications in the design of low power processors
{"title":"Technique for Minimizing Power Consumption in Array Multipliers through Input Vector Ordering","authors":"N. Vasanthal, M. Satyam, K. Subba Rao","doi":"10.1109/ICSCN.2007.350723","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350723","url":null,"abstract":"It is known that, excessive power dissipation can cause over heating, which reduces the life time of the chip and degrades the circuit performance. Local hot spots occur due to large instantaneous power dissipation. We propose a methodology based on reordering the input vectors to reduce the power dissipated in combinational circuits. Experimental results indicate that the proposed technique achieves reduction in average power, reduction in peak power and reduction in difference between maximum and minimum instantaneous power. In this paper, the results obtained by applying this technique to a specific circuit, an array multiplier are reported. As array multipliers are extensively used in digital signal processing (DSP) applications, we feel that this technique will have far-reaching implications in the design of low power processors","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125425930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350747
G. Kharate, Ashok A. Ghatol, P. Rege
Recently discrete wavelet transform and wavelet packet has emerged as popular techniques for image compression. This paper compares compression performance of Daubechies, Biorthogonal, Coiflets and other wavelets along with results for different frequency images. Based on the result, we propose that proper selection of mother wavelet on the basis of nature of images and improve the quality and compression ratio remarkably
{"title":"Selection of Mother Wavelet for Image Compression on Basis of Image","authors":"G. Kharate, Ashok A. Ghatol, P. Rege","doi":"10.1109/ICSCN.2007.350747","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350747","url":null,"abstract":"Recently discrete wavelet transform and wavelet packet has emerged as popular techniques for image compression. This paper compares compression performance of Daubechies, Biorthogonal, Coiflets and other wavelets along with results for different frequency images. Based on the result, we propose that proper selection of mother wavelet on the basis of nature of images and improve the quality and compression ratio remarkably","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122314184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350692
R. Gunasekaran, V. Rhymend Uthariaraj
A major proliferating architecture, that extends its services globally in wireless networks, is ad hoc network, which endows more research areas to work with. In next generation networks, user can be accurately determined and maintained by the network on per-user basis. This paper investigates the design of ad hoc network architecture that exploits user profiles to maximize network efficiency and promote better quality of service by differentiated bandwidth reservation and resource allocation to different classes of users. A model called high-privileged and low-privileged architecture (HPLP) for the forthcoming ad hoc network is proposed through which differentiated services can be achieved for different class of users. A new MAC protocol named as D-MACAW, is also suggested for the proposed architecture. Among the various factors influencing the differentiated services, bandwidth reservation is only considered and different factors that can influence the efficiency of the bandwidth reservation are identified. Two classes of users are considered as high-privileged, a high-cost and efficient service users and low-privileged, low-cost and best effort service users. The differentiated service provided for the different classes of users is proved through simulation analysis. The results obtained using ns2 show that efficient quality of service is guaranteed to users who subscribe high-privileged profile
在无线网络中扩展其全球服务的一个主要的扩散架构是特设网络，它赋予了更多的研究领域。在下一代网络中，网络可以根据每个用户精确地确定和维护用户。本文研究了一种利用用户配置的自组织网络架构设计，通过对不同类型的用户进行差异化的带宽预留和资源分配，使网络效率最大化，提高服务质量。针对即将到来的自组织网络，提出了一种高特权和低特权架构(high-privileged and low-privileged architecture, HPLP)模型，通过该模型可以为不同类别的用户实现差异化的服务。本文还提出了一种新的MAC协议，称为D-MACAW。在影响差异化业务的各种因素中，只考虑带宽预留，识别影响带宽预留效率的各种因素。两类用户被认为是高特权、高成本和高效率的服务用户和低特权、低成本和尽最大努力的服务用户。通过仿真分析，验证了针对不同类别用户提供差异化服务的可行性。使用ns2的结果表明，对于订阅高特权配置文件的用户，有效的服务质量得到了保证
{"title":"Differentiated Bandwidth Allocation in Mobile Ad Hoc Networks (MANET) -A Profile Based Approach","authors":"R. Gunasekaran, V. Rhymend Uthariaraj","doi":"10.1109/ICSCN.2007.350692","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350692","url":null,"abstract":"A major proliferating architecture, that extends its services globally in wireless networks, is ad hoc network, which endows more research areas to work with. In next generation networks, user can be accurately determined and maintained by the network on per-user basis. This paper investigates the design of ad hoc network architecture that exploits user profiles to maximize network efficiency and promote better quality of service by differentiated bandwidth reservation and resource allocation to different classes of users. A model called high-privileged and low-privileged architecture (HPLP) for the forthcoming ad hoc network is proposed through which differentiated services can be achieved for different class of users. A new MAC protocol named as D-MACAW, is also suggested for the proposed architecture. Among the various factors influencing the differentiated services, bandwidth reservation is only considered and different factors that can influence the efficiency of the bandwidth reservation are identified. Two classes of users are considered as high-privileged, a high-cost and efficient service users and low-privileged, low-cost and best effort service users. The differentiated service provided for the different classes of users is proved through simulation analysis. The results obtained using ns2 show that efficient quality of service is guaranteed to users who subscribe high-privileged profile","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123844205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350652
N. Chithra Raj, P. Aswathy, K. V. Sagar
A combination of optimization theory, statistical learning, and kernel theory labeled as "support vector machines" (SVMs) can be applied to electromagnetic problems. Recently, popular machine learning algorithms have successfully been applied to wireless communication problems, notably spread spectrum receiver design, channel equalization, and adaptive beam forming with direction of arrival estimation (DOA). The capacity of communication systems has limitations due to co channel interference. In code division multiple access (CDMA), users can share the same frequency at the same time, but the number of users is limited by the multi-user interference (MUI). This paper presents an implementation of determination of angle of arrival (AOA) estimation based on nonlinear SVM regressors (SVR), an important component of CDMA communication systems
{"title":"Determination of Angle of Arrival using Nonlinear Support Vector Machine Regressors","authors":"N. Chithra Raj, P. Aswathy, K. V. Sagar","doi":"10.1109/ICSCN.2007.350652","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350652","url":null,"abstract":"A combination of optimization theory, statistical learning, and kernel theory labeled as \"support vector machines\" (SVMs) can be applied to electromagnetic problems. Recently, popular machine learning algorithms have successfully been applied to wireless communication problems, notably spread spectrum receiver design, channel equalization, and adaptive beam forming with direction of arrival estimation (DOA). The capacity of communication systems has limitations due to co channel interference. In code division multiple access (CDMA), users can share the same frequency at the same time, but the number of users is limited by the multi-user interference (MUI). This paper presents an implementation of determination of angle of arrival (AOA) estimation based on nonlinear SVM regressors (SVR), an important component of CDMA communication systems","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124917970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-05DOI: 10.1109/ICSCN.2007.350773
M. Sangeetha, J. RajaPaul Perinbam
Behavioral modeling for codesign system is transformed into internal model known as control/data flow graph and produces a register-transfer-level (RTL) model of the hardware implementation for a given schedule. The internal model for codesign system is partitioned after scheduling and its communication cost is evaluated. The communication between components is through the buffered channels, the size of the buffer is estimated by its edge cut-set and system delay for different models are achieved to measure the quality of partitioning as opposed to general partitioning approaches that use number of nodes in each partition as constraint. In this paper scheduling and allocation algorithm (SAA) discusses helpful optimization method for resource-constrained and time constrained system in high level synthesis tool. The approach is based on data path for CDFG model that capture the design information from the source file specified by VHDL language from its equivalent separate Control flow graph and data flow graph. The proposed algorithm is also compared with other algorithm through estimation of schedules with a benchmark example. The buffer size is calculated with different objectives in partitioning and optimum partitioning is proposed
{"title":"Optimization of Behavioral Modeling for Codesign of Embedded System","authors":"M. Sangeetha, J. RajaPaul Perinbam","doi":"10.1109/ICSCN.2007.350773","DOIUrl":"https://doi.org/10.1109/ICSCN.2007.350773","url":null,"abstract":"Behavioral modeling for codesign system is transformed into internal model known as control/data flow graph and produces a register-transfer-level (RTL) model of the hardware implementation for a given schedule. The internal model for codesign system is partitioned after scheduling and its communication cost is evaluated. The communication between components is through the buffered channels, the size of the buffer is estimated by its edge cut-set and system delay for different models are achieved to measure the quality of partitioning as opposed to general partitioning approaches that use number of nodes in each partition as constraint. In this paper scheduling and allocation algorithm (SAA) discusses helpful optimization method for resource-constrained and time constrained system in high level synthesis tool. The approach is based on data path for CDFG model that capture the design information from the source file specified by VHDL language from its equivalent separate Control flow graph and data flow graph. The proposed algorithm is also compared with other algorithm through estimation of schedules with a benchmark example. The buffer size is calculated with different objectives in partitioning and optimum partitioning is proposed","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127571205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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