V. Sambhe, Dilip S. Kale, Archana Wasule, Neema Shikha
The last few years have witnessed a dramatic boom in the wireless communications industry, hence increasing the number of users of mobile communication devices. This magnified the need for a more efficient and reliable signal scrambler. This paper deals with the mobile jamming technology. The concept of jamming technology is studied in a step-by-step approach. The mobile jammer in the frequency range of 890 MHz to 960 MHz (GSM) is developed. Its circuit analysis simulation is performed using Speace-spice Software. Antenna simulation is done by using IE3D software [8]. The jammer circuit is designed with minimum cost and high efficiency. The jammer jams the signal within five meter effective radius.
{"title":"Antenna for Mobile Phone Jammer","authors":"V. Sambhe, Dilip S. Kale, Archana Wasule, Neema Shikha","doi":"10.1109/ICETET.2008.233","DOIUrl":"https://doi.org/10.1109/ICETET.2008.233","url":null,"abstract":"The last few years have witnessed a dramatic boom in the wireless communications industry, hence increasing the number of users of mobile communication devices. This magnified the need for a more efficient and reliable signal scrambler. This paper deals with the mobile jamming technology. The concept of jamming technology is studied in a step-by-step approach. The mobile jammer in the frequency range of 890 MHz to 960 MHz (GSM) is developed. Its circuit analysis simulation is performed using Speace-spice Software. Antenna simulation is done by using IE3D software [8]. The jammer circuit is designed with minimum cost and high efficiency. The jammer jams the signal within five meter effective radius.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114714801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a physics based model of a P+ -InAs0.36Sb0.20P0.44/ n0 -InAs/n -InAs single heterostructure light emitting diode (SH-LED) suitable for use as source in gas detection and futuristic optical fiber communication systems in the mid-infrared spectral region at 300 K. The model takes into account all dominating radiative and non-radiative recombination processes, interfacial recombination and self-absorption in the active layer of the SH-LED structure. The effect of various recombination mechanisms on the quantum efficiency, modulation bandwidth and output power of the LED has been evaluated. The proposed SH- LED has been studied for its utility in mid-infrared optical fiber communication by considering the modulation bandwidth and its variation with active layer width of the SH-LED structure. The I-V characteristic of the SH-LED has been evaluated and cut-in voltage found to be 0.26 V. The output power of the SH-LED has been computed as a function of bias current and it is found to be in good agreement with the reported experimental results.
{"title":"Generic Model of SH-LED for Mid-infrared (2-5µm) Applications","authors":"Sanjeev, P. Chakrabarti","doi":"10.1109/ICETET.2008.8","DOIUrl":"https://doi.org/10.1109/ICETET.2008.8","url":null,"abstract":"In this paper, we present a physics based model of a P+ -InAs0.36Sb0.20P0.44/ n0 -InAs/n -InAs single heterostructure light emitting diode (SH-LED) suitable for use as source in gas detection and futuristic optical fiber communication systems in the mid-infrared spectral region at 300 K. The model takes into account all dominating radiative and non-radiative recombination processes, interfacial recombination and self-absorption in the active layer of the SH-LED structure. The effect of various recombination mechanisms on the quantum efficiency, modulation bandwidth and output power of the LED has been evaluated. The proposed SH- LED has been studied for its utility in mid-infrared optical fiber communication by considering the modulation bandwidth and its variation with active layer width of the SH-LED structure. The I-V characteristic of the SH-LED has been evaluated and cut-in voltage found to be 0.26 V. The output power of the SH-LED has been computed as a function of bias current and it is found to be in good agreement with the reported experimental results.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127374846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vrinda Parkhi, S. Shilaskar, Milind Tirmare, M. Jog
The primary function of any adjustable speed motor drive is to control the speed, torque, acceleration, deceleration and direction of rotation of machine. Unlike constant speed systems, the adjustable drive permits the selection of infinite number of speeds within its operating range. Most multipurpose production machines benefit from adjustable speed control, since frequently their speed must change to optimize the machine process or adapt it to various tasks for improved product quality, production speed or safety. The control circuit in FPGA clearly has an advantage of reconfiguration over the other methods.
{"title":"FPGA Implementation of PWM Control Technique for Three Phase Induction Motor Drive","authors":"Vrinda Parkhi, S. Shilaskar, Milind Tirmare, M. Jog","doi":"10.1109/ICETET.2008.115","DOIUrl":"https://doi.org/10.1109/ICETET.2008.115","url":null,"abstract":"The primary function of any adjustable speed motor drive is to control the speed, torque, acceleration, deceleration and direction of rotation of machine. Unlike constant speed systems, the adjustable drive permits the selection of infinite number of speeds within its operating range. Most multipurpose production machines benefit from adjustable speed control, since frequently their speed must change to optimize the machine process or adapt it to various tasks for improved product quality, production speed or safety. The control circuit in FPGA clearly has an advantage of reconfiguration over the other methods.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127568055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An ad hoc network is an infrastructure less network formed by a collection of wireless mobile nodes that operate as hosts as well as routers in the network. Thus a dynamic and efficient routing protocol is central to the design of ad hoc networks. In this paper we compare the performance of ad hoc routing protocols like DSDV, AODV and DSR under scalable and mobile conditions. We also analyze the results by using the different mobility models and check the performance of routing protocols under different mobility model scenarios.
{"title":"Mobility Model Perspectives for Scalability and Routing Protocol Performances in Wireless Ad-Hoc Network","authors":"S. Kulkarni, G. R. Rao","doi":"10.1109/ICETET.2008.202","DOIUrl":"https://doi.org/10.1109/ICETET.2008.202","url":null,"abstract":"An ad hoc network is an infrastructure less network formed by a collection of wireless mobile nodes that operate as hosts as well as routers in the network. Thus a dynamic and efficient routing protocol is central to the design of ad hoc networks. In this paper we compare the performance of ad hoc routing protocols like DSDV, AODV and DSR under scalable and mobile conditions. We also analyze the results by using the different mobility models and check the performance of routing protocols under different mobility model scenarios.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125313618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the comparative characteristic deflection and serviceability analysis in limit state of deflection of beam designed for given action in four different ways. The displacement samples for each beam for given loadings conditions, spans, are generated by simulation technique. Obtained samples are modeled with lognormal probability distributions. With the means and standard deviations of the samples, failure probability (total deflection>Span/250) is determined and is checked with failure probability determined by simulation technique. Characteristic deflections in all the four cases are computed. Comparative study of failure probability and characteristic deflections leads to the conclusion that designing the beam as flanged beam than the doubly reinforced beam reduces the failure probability in limit state of deflection to a grater extent further it becomes clear that in case of flanged beam steel provided in tension zone will be more effective in reducing deflection than that in compressive zone.
{"title":"Comparison of Characteristic Deflection and Serviceability Analysis in Limit State of Deflection of Simply Supported RC Beams","authors":"Ravindra P. Patil, K. Manjunath","doi":"10.1109/ICETET.2008.176","DOIUrl":"https://doi.org/10.1109/ICETET.2008.176","url":null,"abstract":"This paper addresses the comparative characteristic deflection and serviceability analysis in limit state of deflection of beam designed for given action in four different ways. The displacement samples for each beam for given loadings conditions, spans, are generated by simulation technique. Obtained samples are modeled with lognormal probability distributions. With the means and standard deviations of the samples, failure probability (total deflection>Span/250) is determined and is checked with failure probability determined by simulation technique. Characteristic deflections in all the four cases are computed. Comparative study of failure probability and characteristic deflections leads to the conclusion that designing the beam as flanged beam than the doubly reinforced beam reduces the failure probability in limit state of deflection to a grater extent further it becomes clear that in case of flanged beam steel provided in tension zone will be more effective in reducing deflection than that in compressive zone.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127059660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Kothari, A. Keskar, Allhad Gokhale, Rucha Deshpande, Pranjali P. Deshmukh
The rough set approach can be applied in pattern recognition at three different stages: pre-processing stage, training stage and in the architecture. This paper proposes the application of the Rough-Neuro Hybrid Approach in the pre-processing stage of pattern recognition. In this project, a training algorithm has been first developed based on Kohonen network. This is used as a benchmark to compare the results of the pure neural approach with the Rough-Neuro hybrid approach and to prove that the efficiency of the latter is higher. Structural and statistical features have been extracted from the images for the training process. The number of attributes is reduced by calculating reducts and core from the original attribute set, which results into reduction in convergence time. Also, the above removal in redundancy increases speed of the process reduces hardware complexity and thus enhances the overall efficiency of the pattern recognition algorithm.
{"title":"Rough Set Approach for Feature Reduction in Pattern Recognition through Unsupervised Artificial Neural Network","authors":"A. Kothari, A. Keskar, Allhad Gokhale, Rucha Deshpande, Pranjali P. Deshmukh","doi":"10.1109/ICETET.2008.230","DOIUrl":"https://doi.org/10.1109/ICETET.2008.230","url":null,"abstract":"The rough set approach can be applied in pattern recognition at three different stages: pre-processing stage, training stage and in the architecture. This paper proposes the application of the Rough-Neuro Hybrid Approach in the pre-processing stage of pattern recognition. In this project, a training algorithm has been first developed based on Kohonen network. This is used as a benchmark to compare the results of the pure neural approach with the Rough-Neuro hybrid approach and to prove that the efficiency of the latter is higher. Structural and statistical features have been extracted from the images for the training process. The number of attributes is reduced by calculating reducts and core from the original attribute set, which results into reduction in convergence time. Also, the above removal in redundancy increases speed of the process reduces hardware complexity and thus enhances the overall efficiency of the pattern recognition algorithm.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"59 34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128102759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In a mobile computing environment, users can perform on-line transaction processing independent of their physical location. In a mobile environment, multiple mobile hosts may update the data simultaneously which may result in inconsistency of data. The traditional techniques use the concept of locking for achieving the concurrency control in mobile environments. This may not be feasible in mobile environments due to variable bandwidth, frequent disconnections etc. In this paper we propose a lockless concurrency control mechanism which helps in reducing the communication overhead and enhances the transaction throughput. The waiting time for execution of the transaction is reduced and the resources are not unnecessarily locked. The simulation results specify the performance trade off benefits of the proposed approach.
{"title":"Concurrency Control without Locking in Mobile Environments","authors":"S. A. Moiz, M. K. Nizamuddin","doi":"10.1109/ICETET.2008.182","DOIUrl":"https://doi.org/10.1109/ICETET.2008.182","url":null,"abstract":"In a mobile computing environment, users can perform on-line transaction processing independent of their physical location. In a mobile environment, multiple mobile hosts may update the data simultaneously which may result in inconsistency of data. The traditional techniques use the concept of locking for achieving the concurrency control in mobile environments. This may not be feasible in mobile environments due to variable bandwidth, frequent disconnections etc. In this paper we propose a lockless concurrency control mechanism which helps in reducing the communication overhead and enhances the transaction throughput. The waiting time for execution of the transaction is reduced and the resources are not unnecessarily locked. The simulation results specify the performance trade off benefits of the proposed approach.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126787433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a simple scheme for implementing the speed control of d.c. motor using digital PID algorithm. Intel 8085 microprocessor based hardware is developed for the implementation of the controller. The system broadly involves interfacing hardware and the software for PID algorithm. A continuous PID controller is governed by an equation which describes the dynamic time varying behavior of the input or the error signal. This is digitized using numerical approximations and is programmed in the microcomputer. This system is a closed loop control system with feedback signal generated by a digital magnetic pickup, which gives a pulse output which is TTL compatible. A digital to analog converter interfaces the power control to the microcomputer. The PID algorithm along with the hardware achieves the speed control of the d.c. motor. The hardware and software are validated in real time by considering different speed settings.
{"title":"Microprocessor Based Digital PID Controller for Speed Control of D.C. Motor","authors":"M. Meenakshi","doi":"10.1109/ICETET.2008.256","DOIUrl":"https://doi.org/10.1109/ICETET.2008.256","url":null,"abstract":"This paper presents a simple scheme for implementing the speed control of d.c. motor using digital PID algorithm. Intel 8085 microprocessor based hardware is developed for the implementation of the controller. The system broadly involves interfacing hardware and the software for PID algorithm. A continuous PID controller is governed by an equation which describes the dynamic time varying behavior of the input or the error signal. This is digitized using numerical approximations and is programmed in the microcomputer. This system is a closed loop control system with feedback signal generated by a digital magnetic pickup, which gives a pulse output which is TTL compatible. A digital to analog converter interfaces the power control to the microcomputer. The PID algorithm along with the hardware achieves the speed control of the d.c. motor. The hardware and software are validated in real time by considering different speed settings.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127476780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the modern era the uses of wireless devices are becoming ubiquitous and these networks have become an increasingly important part of global communication architecture. Most of the wireless networks have fixed infrastructure and the need for mobile wireless networks are growing rapidly, which requires higher data rates. Due to high data rate in wireless networks the TCP performance has a broad and significant impact on data applications. The uses of extensive local retransmission mechanism in wireless networks are adequate. In order to improve the performance of TCP/IP, a RETSINA agent is implemented along with the Transmission Control Protocol (TCP). Performance has been analyzed for the TCP/IP with and without RETSINA agent for the metrics throughput and latency.
{"title":"Improving the Performance of TCP/IP over Wireless Networks with a RETSINA Agent","authors":"B. Sasikumar, V. Vasudevan","doi":"10.1109/ICETET.2008.157","DOIUrl":"https://doi.org/10.1109/ICETET.2008.157","url":null,"abstract":"In the modern era the uses of wireless devices are becoming ubiquitous and these networks have become an increasingly important part of global communication architecture. Most of the wireless networks have fixed infrastructure and the need for mobile wireless networks are growing rapidly, which requires higher data rates. Due to high data rate in wireless networks the TCP performance has a broad and significant impact on data applications. The uses of extensive local retransmission mechanism in wireless networks are adequate. In order to improve the performance of TCP/IP, a RETSINA agent is implemented along with the Transmission Control Protocol (TCP). Performance has been analyzed for the TCP/IP with and without RETSINA agent for the metrics throughput and latency.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126392505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Although QCA (quantum dot cellular automata) has been introduced as a new kind of technology for over a decade, it still continues to be so and its merits and flaws are yet under study for future practical use. One of the problems of this technology is the dependency of its circuit timing to its layout. An asynchronous design methodology for QCA has been offered to solve this problem. The proposed methodology uses NCL (null convention logic) to approach this issue. Since asynchronous registers play an important role in NCL methodology, to ease the problem this work is aimed to design asynchronous registers and employ them to construct a delay insensitive serial adder. The results obtained so far can be used to assess the required cell counts, and space in future QCA system design.
{"title":"Designing QCA Delay-Insensitive Serial Adder","authors":"Elham Tabrizizadeh, Hamid reza Mohaqeq, A. Vafaei","doi":"10.1109/ICETET.2008.65","DOIUrl":"https://doi.org/10.1109/ICETET.2008.65","url":null,"abstract":"Although QCA (quantum dot cellular automata) has been introduced as a new kind of technology for over a decade, it still continues to be so and its merits and flaws are yet under study for future practical use. One of the problems of this technology is the dependency of its circuit timing to its layout. An asynchronous design methodology for QCA has been offered to solve this problem. The proposed methodology uses NCL (null convention logic) to approach this issue. Since asynchronous registers play an important role in NCL methodology, to ease the problem this work is aimed to design asynchronous registers and employ them to construct a delay insensitive serial adder. The results obtained so far can be used to assess the required cell counts, and space in future QCA system design.","PeriodicalId":269929,"journal":{"name":"2008 First International Conference on Emerging Trends in Engineering and Technology","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124843536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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