Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377527
Takenori Kakutani, Yuya Suzuki, Muhammad Ali, Serhat Erdogan, M. Kathaperumal, M. Swaminathan
With the tremendous advances and increasing demand in 5G communications, the low-loss performance of RF device components becomes more critical. Two parameters that have significant impact on the low-loss RF performance are lower circuit conductor loss and dielectric loss of the build-up materials. Therefore, this study is focused on the loss tangent (Df) of the dielectric build-up material and demonstration of its electrical reliability with a low-loss substrate for high-frequency transmission. This newly developed advanced low-loss dry film build-up material exhibits a Dfvalues of < 0.003 at 39 GHz and is applicable to high frequency transmission. This build-up material also exhibits excellent electrical reliability required for advanced dielectric materials. For evaluation of the filter characteristics in the mm Wave band, a substrate with filter circuit structures was fabricated using the low loss dielectric material. Transmission characteristics of the filters were measured and demonstrated to have a minimum transmission loss of less than 1.18 dB at 39 GHz.
{"title":"Reliability and High-Frequency Filter Characteristics of a Low-Loss Material for 5G RF Modules","authors":"Takenori Kakutani, Yuya Suzuki, Muhammad Ali, Serhat Erdogan, M. Kathaperumal, M. Swaminathan","doi":"10.1109/ISSM51728.2020.9377527","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377527","url":null,"abstract":"With the tremendous advances and increasing demand in 5G communications, the low-loss performance of RF device components becomes more critical. Two parameters that have significant impact on the low-loss RF performance are lower circuit conductor loss and dielectric loss of the build-up materials. Therefore, this study is focused on the loss tangent (Df) of the dielectric build-up material and demonstration of its electrical reliability with a low-loss substrate for high-frequency transmission. This newly developed advanced low-loss dry film build-up material exhibits a Dfvalues of < 0.003 at 39 GHz and is applicable to high frequency transmission. This build-up material also exhibits excellent electrical reliability required for advanced dielectric materials. For evaluation of the filter characteristics in the mm Wave band, a substrate with filter circuit structures was fabricated using the low loss dielectric material. Transmission characteristics of the filters were measured and demonstrated to have a minimum transmission loss of less than 1.18 dB at 39 GHz.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123331238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Defect classifications are the very important steps as the in-line defect inspection of the semiconductor manufacturing procedure. The precisely identify the defect morphology based on scanning electron microscopy (SEM) images can provide crucial information to find out the root causes of those defects. The conventional defect inspection steps are usually through visual judgement by engineer or technical assistant. However, it's time-consuming and laborious. In our recent study, the Artificial Intelligence Automatic Defect Classification (AI-ADC) performs promising good accuracy and purity of the auto defect classification by deep learning method. Nevertheless, some kind of tiny defects are still difficult to classify by this method, such as multi-lines bridge defect. In this paper, we propose the novel method, called “Hi-erarchical structure AI-ADC”, which join a second binning classifier for more precise defect classification. As a result, the proposed hierarchical AI-ADC method not only can improve the multi-lines bridge defect binning purity from 56% to 88%, but also be applied to classify the similar defect types. Indeed this approach achieves high defect classification performance.
{"title":"Improvement of Multi-lines bridge Defect Classification by Hierarchical Architecture in Artificial Intelligence Automatic Defect Classification","authors":"Bing-Sheng Lin, Jung-Syuan Cheng, Hsiang-Chou Liao, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen","doi":"10.1109/ISSM51728.2020.9377510","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377510","url":null,"abstract":"Defect classifications are the very important steps as the in-line defect inspection of the semiconductor manufacturing procedure. The precisely identify the defect morphology based on scanning electron microscopy (SEM) images can provide crucial information to find out the root causes of those defects. The conventional defect inspection steps are usually through visual judgement by engineer or technical assistant. However, it's time-consuming and laborious. In our recent study, the Artificial Intelligence Automatic Defect Classification (AI-ADC) performs promising good accuracy and purity of the auto defect classification by deep learning method. Nevertheless, some kind of tiny defects are still difficult to classify by this method, such as multi-lines bridge defect. In this paper, we propose the novel method, called “Hi-erarchical structure AI-ADC”, which join a second binning classifier for more precise defect classification. As a result, the proposed hierarchical AI-ADC method not only can improve the multi-lines bridge defect binning purity from 56% to 88%, but also be applied to classify the similar defect types. Indeed this approach achieves high defect classification performance.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126462421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377537
S. Hsiao, Thi‐Thuy‐Nga Nguyen, T. Tsutsumi, K. Ishikawa, M. Sekine, M. Hori
The dependences of plasmas (CF4/D2 and CF4/H2) on etch rates of the PECVD SiN films at different substrate temperatures were investigated. The CF4/D2 plasma exhibited higher etch rates than that for the CF4/D2 plasma at room temperature and higher. The optical emission spectra showed that the CF polymerization, F and Balmer emissions were stronger in the CF4/D2 plasma, by comparing with the CF4/H2 plasma. A thinner fluorocarbon thickness with a lower F/C ratio was found in the sample proceeded by the CF4/H2 plasma. The fluorocarbon thickness and gas phase concentration were not responsible for the increase of etch rate in the CF4/D2 plasma. The abstraction of H inside the SiN films by deuterium and hydrogen dissociation were considered to be important for the etching of the Si- H bond rich SiN films.
{"title":"Etching characteristics of PECVD-prepared SiN films with CF4/D2 and CF4/H2 plasmas at different temperatures","authors":"S. Hsiao, Thi‐Thuy‐Nga Nguyen, T. Tsutsumi, K. Ishikawa, M. Sekine, M. Hori","doi":"10.1109/ISSM51728.2020.9377537","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377537","url":null,"abstract":"The dependences of plasmas (CF<inf>4</inf>/D<inf>2</inf> and CF<inf>4</inf>/H<inf>2</inf>) on etch rates of the PECVD SiN films at different substrate temperatures were investigated. The CF<inf>4</inf>/D<inf>2</inf> plasma exhibited higher etch rates than that for the CF<inf>4</inf>/D<inf>2</inf> plasma at room temperature and higher. The optical emission spectra showed that the CF polymerization, F and Balmer emissions were stronger in the CF<inf>4</inf>/D<inf>2</inf> plasma, by comparing with the CF<inf>4</inf>/H<inf>2</inf> plasma. A thinner fluorocarbon thickness with a lower F/C ratio was found in the sample proceeded by the CF<inf>4</inf>/H<inf>2</inf> plasma. The fluorocarbon thickness and gas phase concentration were not responsible for the increase of etch rate in the CF<inf>4</inf>/D<inf>2</inf> plasma. The abstraction of H inside the SiN films by deuterium and hydrogen dissociation were considered to be important for the etching of the Si- H bond rich SiN films.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115033048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377516
S. Yasuda, Tomoya Tanaka, M. Kitabata, Yuko Jisaki
This paper describes a chamber and recipe-independent FDC (fault detection and classification) indicator with an example of detecting abnormal discharge in aluminum sputtering tools. The indicator is developed using simple equations and is improved by an engineer with legacy FDC system to minimize false alarms which cause the reduction of an equipment productivity. Besides, the indicator is introduced into newly installed tools and prevent scrap wafers at minimum.
{"title":"Chamber and Recipe- Independent FDC indicator in High - mix Semiconductor Manufacturing","authors":"S. Yasuda, Tomoya Tanaka, M. Kitabata, Yuko Jisaki","doi":"10.1109/ISSM51728.2020.9377516","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377516","url":null,"abstract":"This paper describes a chamber and recipe-independent FDC (fault detection and classification) indicator with an example of detecting abnormal discharge in aluminum sputtering tools. The indicator is developed using simple equations and is improved by an engineer with legacy FDC system to minimize false alarms which cause the reduction of an equipment productivity. Besides, the indicator is introduced into newly installed tools and prevent scrap wafers at minimum.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128154983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a method for rapid resolution of parametric failure during the development period. Since the number of samples is small, it is not possible to carry out general big data analysis of white defect failures of CMOS image sensors (CISs) during the development period in the same way as can be done during the mass production period. Our feature value analysis of white defects based on device physics revealed that both a development product and mass products using big data show similar fluctuations in dark current spectroscopy and in-plane distribution in the wafer. Process step/tool identification and tool sensor data analysis revealed the degree of vacuum within the implantation tool to have a strong correlation with white defect count. We developed a virtual metrology (VM) model for white defect count and varied the degree of vacuum. As a result of our experiments, we were able to reduce white defect count during the development period by 75%. The time required for resolution of failures was 10% that of the conventional method.
{"title":"Rapid Resolution of Parametric Failures in the Process Development Period by Integrating Device Physics and Big Data","authors":"Takahiko Hashidzume, Takatoshi Yasui, Tomoya Tanaka","doi":"10.1109/ISSM51728.2020.9377521","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377521","url":null,"abstract":"This paper describes a method for rapid resolution of parametric failure during the development period. Since the number of samples is small, it is not possible to carry out general big data analysis of white defect failures of CMOS image sensors (CISs) during the development period in the same way as can be done during the mass production period. Our feature value analysis of white defects based on device physics revealed that both a development product and mass products using big data show similar fluctuations in dark current spectroscopy and in-plane distribution in the wafer. Process step/tool identification and tool sensor data analysis revealed the degree of vacuum within the implantation tool to have a strong correlation with white defect count. We developed a virtual metrology (VM) model for white defect count and varied the degree of vacuum. As a result of our experiments, we were able to reduce white defect count during the development period by 75%. The time required for resolution of failures was 10% that of the conventional method.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128287243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377534
Shota Umeda, K. Tamaki, M. Sumiya, Yoshito Kamaji
In a semiconductor plasma etcher, it is becoming increasingly necessary to improve productivity. Thus, to reduce unplanned maintenance, predictive maintenance (PdM) is typically conducted. In PdM, the planned maintenance schedule is updated on the basis of the predicted failure timing. However, in practice, the predicted failure timing has a probabilistic variability. Therefore, we propose a maintenance schedule update method on the basis of the expected maintenance cost calculated from the probabilistic variability of the failure timing. We applied our method to a dataset that model failure cases of etchers and found that our method was effective in terms of maintenance costs.
{"title":"Planned Maintenance Schedule Update Method for Predictive Maintenance of Semiconductor Plasma Etcher","authors":"Shota Umeda, K. Tamaki, M. Sumiya, Yoshito Kamaji","doi":"10.1109/ISSM51728.2020.9377534","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377534","url":null,"abstract":"In a semiconductor plasma etcher, it is becoming increasingly necessary to improve productivity. Thus, to reduce unplanned maintenance, predictive maintenance (PdM) is typically conducted. In PdM, the planned maintenance schedule is updated on the basis of the predicted failure timing. However, in practice, the predicted failure timing has a probabilistic variability. Therefore, we propose a maintenance schedule update method on the basis of the expected maintenance cost calculated from the probabilistic variability of the failure timing. We applied our method to a dataset that model failure cases of etchers and found that our method was effective in terms of maintenance costs.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133423911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377535
Gabe Villareal, Joe Lee
As we step into the era of Smart Manufacturing, a growing number of manufacturers across all industries are leveraging enabling technologies, such as Artificial intelligence (AI), Cloud, and Internet of Things (IOT), to help them improve productivity and profitability. Through an actual use case, this paper illustrates how one of these enabling technologies, Cloud computing, helps a semiconductor manufacturer overcome various challenges allowing them to be more productive and cost efficient.
{"title":"The Benefits of Real-time Cloud Analytics in Semiconductor","authors":"Gabe Villareal, Joe Lee","doi":"10.1109/ISSM51728.2020.9377535","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377535","url":null,"abstract":"As we step into the era of Smart Manufacturing, a growing number of manufacturers across all industries are leveraging enabling technologies, such as Artificial intelligence (AI), Cloud, and Internet of Things (IOT), to help them improve productivity and profitability. Through an actual use case, this paper illustrates how one of these enabling technologies, Cloud computing, helps a semiconductor manufacturer overcome various challenges allowing them to be more productive and cost efficient.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123320668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377520
J. Pyo, H. Morita, A. Ihara, Ohmi Shun-ichiro
This paper investigated Ar/N2-plasma sputtering pressure dependence on electrical characteristics of HfON tunneling layer (TL) formed by the plasma oxidation of HfN for Hf-based Metal-Oxide-Nitride-Oxide-Silicon (MONOS) diodes. The HfON formed by the Ar/O2 plasma oxidation of HfN deposited at 0.04 Pa showed improved film quality and small equivalent oxide thickness of 0.84 nm, which realized excellent MONOS characteristics such as negligible hysteresis, and memory window of 4 V at the program and erase voltage/time of ±8 V/100 ms. Moreover, HfON TL formed by Ar/O2 plasma oxidation of HfN deposited at 0.04 Pa MONOS diode shows improved endurance and retention characteristics.
{"title":"Ar/N2-plasma Sputtering Pressure Dependence on Electrical Characteristics of HfON Tunneling Layer Formed by the Plasma Oxidation of HfN for Hf-Based MONOS Diodes","authors":"J. Pyo, H. Morita, A. Ihara, Ohmi Shun-ichiro","doi":"10.1109/ISSM51728.2020.9377520","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377520","url":null,"abstract":"This paper investigated Ar/N2-plasma sputtering pressure dependence on electrical characteristics of HfON tunneling layer (TL) formed by the plasma oxidation of HfN for Hf-based Metal-Oxide-Nitride-Oxide-Silicon (MONOS) diodes. The HfON formed by the Ar/O2 plasma oxidation of HfN deposited at 0.04 Pa showed improved film quality and small equivalent oxide thickness of 0.84 nm, which realized excellent MONOS characteristics such as negligible hysteresis, and memory window of 4 V at the program and erase voltage/time of ±8 V/100 ms. Moreover, HfON TL formed by Ar/O2 plasma oxidation of HfN deposited at 0.04 Pa MONOS diode shows improved endurance and retention characteristics.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131404483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377533
Yuichi Watanabe, Hirofumi Ikawa, Shota Suzuki, T. Isobe, Tatsuhiko Hirano, K. Sugai
A material removal rate in CMP process is affected by a frequency of contact between the abrasives and the wafer because of the electrostatic interaction. Control of ζpotential in a micro region was considered to be a key for slurry design, and research on its measurement method was conducted. FD curve was measured in liquid using AFM. As a result, it was found that load of the cantilever observed during the jump-in strongly reflects the ζpotential. Furthermore, we achieved to measure microscopic ζpotential on the patterned wafer.
{"title":"Study on Measurement Method of Microscopic $zeta$ Potential","authors":"Yuichi Watanabe, Hirofumi Ikawa, Shota Suzuki, T. Isobe, Tatsuhiko Hirano, K. Sugai","doi":"10.1109/ISSM51728.2020.9377533","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377533","url":null,"abstract":"A material removal rate in CMP process is affected by a frequency of contact between the abrasives and the wafer because of the electrostatic interaction. Control of ζpotential in a micro region was considered to be a key for slurry design, and research on its measurement method was conducted. FD curve was measured in liquid using AFM. As a result, it was found that load of the cantilever observed during the jump-in strongly reflects the ζpotential. Furthermore, we achieved to measure microscopic ζpotential on the patterned wafer.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131404599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/issm51728.2020.9377506
John Behnke
The Smart Manufacturing revolution is underway and already driving changes throughout the Semi industry and world. Early adopters are seeing double digit improvements in multiple KPIs. The establishment of a comprehensive Digital Twin of a factory is key to enabling many of these Smart solutions including Factory Scheduling, which is one of the highest ROI Smart initiatives. However, creating a Digital Twin requires the aggregation of many types of data from many discrete data sources and systems.
{"title":"Digital Transformation's Impact on Smart Manufacturing","authors":"John Behnke","doi":"10.1109/issm51728.2020.9377506","DOIUrl":"https://doi.org/10.1109/issm51728.2020.9377506","url":null,"abstract":"The Smart Manufacturing revolution is underway and already driving changes throughout the Semi industry and world. Early adopters are seeing double digit improvements in multiple KPIs. The establishment of a comprehensive Digital Twin of a factory is key to enabling many of these Smart solutions including Factory Scheduling, which is one of the highest ROI Smart initiatives. However, creating a Digital Twin requires the aggregation of many types of data from many discrete data sources and systems.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114885394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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