Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377525
Daisuke Hamaguchi, Tomonari Masada, Takumi Eguchi
In semiconductor manufacturing processes, it is important to quickly identify any signs of the occurrence of defects. We applied a time-series clustering method to the signal data of processing equipment and obtained information related to the occurrence of defects. By using the information as the feature values of a prediction model, we were able to predict defects more accurately than by using only conventional feature values.
{"title":"Feature Extraction from Equipment Sensor Signals with Time Series Clustering and Its Application to Defect Prediction","authors":"Daisuke Hamaguchi, Tomonari Masada, Takumi Eguchi","doi":"10.1109/ISSM51728.2020.9377525","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377525","url":null,"abstract":"In semiconductor manufacturing processes, it is important to quickly identify any signs of the occurrence of defects. We applied a time-series clustering method to the signal data of processing equipment and obtained information related to the occurrence of defects. By using the information as the feature values of a prediction model, we were able to predict defects more accurately than by using only conventional feature values.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116913959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377515
H. Tsuchiyama, Steven Lakeman
The novel sensor for Real-time in situ process monitoring using Quart Crystal Microbalance has been developed to wafer process and deployed in Wafer process. In this document, the deployment result is reviewed and the possibility for the future use is discussed.
{"title":"Using Quartz Crystal Microbalance to Provide Real-Time Process Monitoring","authors":"H. Tsuchiyama, Steven Lakeman","doi":"10.1109/ISSM51728.2020.9377515","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377515","url":null,"abstract":"The novel sensor for Real-time in situ process monitoring using Quart Crystal Microbalance has been developed to wafer process and deployed in Wafer process. In this document, the deployment result is reviewed and the possibility for the future use is discussed.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115112129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377500
Richard Burch, M. Keleher, Kazuki Kunitoshi
We have developed a novel technique to handle Fault Detection and Classification data for Equipment Health Monitoring. While most techniques are very human intensive, this AI-FDC technique allows for less human interaction by taking advantage of recent advancements in Machine Learning. Raw traces are automatically broken down into windows with consistent characteristics, relevant statistics are automatically calculated based on window characteristics, and anomalous traces are detected by the system without labels. This system will accelerate root cause diagnosis of Equipment Breakdowns and prevent subsequent breakdowns.
{"title":"AI-FDC: Automated Top Down System for Fab Wide Process Equipment Health Monitoring","authors":"Richard Burch, M. Keleher, Kazuki Kunitoshi","doi":"10.1109/ISSM51728.2020.9377500","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377500","url":null,"abstract":"We have developed a novel technique to handle Fault Detection and Classification data for Equipment Health Monitoring. While most techniques are very human intensive, this AI-FDC technique allows for less human interaction by taking advantage of recent advancements in Machine Learning. Raw traces are automatically broken down into windows with consistent characteristics, relevant statistics are automatically calculated based on window characteristics, and anomalous traces are detected by the system without labels. This system will accelerate root cause diagnosis of Equipment Breakdowns and prevent subsequent breakdowns.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121284286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Automation of production control (e.g. scheduling) to continuously improve the production efficiency become more important issue, according to labor shortages in the Japanese manufacturing industry have become a serious problem in recent [1]. Our research target is one of severe production systems, a High-mix Low-volume Make-to-Order (MTO) business. Its production planning and scheduling is required a work-leveling of the production load (WLL) as well as the scheduling [2].
{"title":"Optimization of Multi-objective Function of n-step Hybrid Flowshop Scheduling","authors":"Jia Lin, Tomoki Ono, Sho Morie, Qingxin Zhu, Yu Sasaki, S. Arima","doi":"10.1109/ISSM51728.2020.9377505","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377505","url":null,"abstract":"Automation of production control (e.g. scheduling) to continuously improve the production efficiency become more important issue, according to labor shortages in the Japanese manufacturing industry have become a serious problem in recent [1]. Our research target is one of severe production systems, a High-mix Low-volume Make-to-Order (MTO) business. Its production planning and scheduling is required a work-leveling of the production load (WLL) as well as the scheduling [2].","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121793456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377536
A. Ihara, J. Pyo, R. M. D. Mailig, H. Morita, S. Ohmi
In this paper, we have investigated MISFETs with HfNxmultilayer gate dielectrics fabricated with Si surface flattening process. The ID- VGcharacteristics of fabricated MISFETs with 2- and 4-layer gate dielectrics showed negligible hysteresis and excellent subthreshold swing (SS) of 71.6 and 72.5 mV/dec., respectively. This is attributed of Si surface flattening process. Furthermore, although the thickness of gate dielectrics was increased by increasing the number of dielectric layers, the extracted equivalent oxide thickness (EOT) showed similar value. Furthermore, the on/off current (Ion/Ioff) ratio was increased by one order of magnitude.
{"title":"Investigation of high-k HfN multilayer gate dielectrics for MISFET fabricated with Si surface flattening","authors":"A. Ihara, J. Pyo, R. M. D. Mailig, H. Morita, S. Ohmi","doi":"10.1109/ISSM51728.2020.9377536","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377536","url":null,"abstract":"In this paper, we have investigated MISFETs with HfNxmultilayer gate dielectrics fabricated with Si surface flattening process. The ID- VGcharacteristics of fabricated MISFETs with 2- and 4-layer gate dielectrics showed negligible hysteresis and excellent subthreshold swing (SS) of 71.6 and 72.5 mV/dec., respectively. This is attributed of Si surface flattening process. Furthermore, although the thickness of gate dielectrics was increased by increasing the number of dielectric layers, the extracted equivalent oxide thickness (EOT) showed similar value. Furthermore, the on/off current (Ion/Ioff) ratio was increased by one order of magnitude.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129973057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377528
K. Tomita, T. Shiraishi, Hiroaki Kato, Hiroyuki Kishimoto, K. Miyashita, Kenya Kobayashi
Sequential phosphorus doping process is expected to form decent silicon electrodes in narrow and deep trenches. We performed process optimization of FP-MOSFETs with sequential phosphorus-doped silicon. We succeeded in reducing processing variations in field plates and decreasing wafer warpage by processing phosphorus-doped silicon without activation annealing. In addition, inserting 800°C annealing before 1000°C annealing contributes no voids in silicon field plates.
{"title":"Process Optimization of Trench Field Plate Power MOSFETs with Sequential Phosphorus-Doped Silicon","authors":"K. Tomita, T. Shiraishi, Hiroaki Kato, Hiroyuki Kishimoto, K. Miyashita, Kenya Kobayashi","doi":"10.1109/ISSM51728.2020.9377528","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377528","url":null,"abstract":"Sequential phosphorus doping process is expected to form decent silicon electrodes in narrow and deep trenches. We performed process optimization of FP-MOSFETs with sequential phosphorus-doped silicon. We succeeded in reducing processing variations in field plates and decreasing wafer warpage by processing phosphorus-doped silicon without activation annealing. In addition, inserting 800°C annealing before 1000°C annealing contributes no voids in silicon field plates.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114419734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377517
T. Asami, Masaharu Tsujimoto
In recent years, semiconductor products have become increasingly important as essential parts of numerous technological devices. In addition, competition is becoming increasingly fierce. Currently, many semiconductor businesses have a horizontal specialization business structure. However, in the CMOS image sensor (CIS) business, vertically Integrated Device Manufacturer (IDM) companies are leading businesses possessing significant technological advantages. This study applies Baldwin's (2004) functional module analysis method to clarify how IDM companies maintain their superiority in CIS, and examines in particular their knowledge acquisition method for improving the main characteristics of CIS. The basic questions this study addresses are why the CIS business has been able to promote the business of IDM companies, and why has it maintained its advantage over the last 10 years. This study seeks to examine this question and present the mechanism behind its superiority. First, the modules of CIS products and development task flow are separated into modules by function and analyzed. The sensor core and system core require different design capabilities. The photodiode of the sensor core is designed through a combination and application of semiconductor physics and optical knowledge by highly expert design, device physics, and process engineers. In IDM companies, development is accomplished in a complementary manner with mutually integrated technologies. We note particularly that the boundary between companies in the horizontal specialization business in the sensor core design affects technological improvement and the speed of growth. During the heyday of SoC in 1990, technology was transferred and production outsourced from the world's top-class IDM to foundries. Based on the current situation two decades later, we analyzed the behavior at that time by back-casting and extracted five growth factors. Five growth opportunities for latecomers to the high-tech manufacturing industry were factors in the current implementation status and effects of the CIS business.
{"title":"A Study of the CMOS Image Sensor Semiconductor Business: Factors Maintaining the Long- Term Manufacturing Technology Superiority of IDM Companies","authors":"T. Asami, Masaharu Tsujimoto","doi":"10.1109/ISSM51728.2020.9377517","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377517","url":null,"abstract":"In recent years, semiconductor products have become increasingly important as essential parts of numerous technological devices. In addition, competition is becoming increasingly fierce. Currently, many semiconductor businesses have a horizontal specialization business structure. However, in the CMOS image sensor (CIS) business, vertically Integrated Device Manufacturer (IDM) companies are leading businesses possessing significant technological advantages. This study applies Baldwin's (2004) functional module analysis method to clarify how IDM companies maintain their superiority in CIS, and examines in particular their knowledge acquisition method for improving the main characteristics of CIS. The basic questions this study addresses are why the CIS business has been able to promote the business of IDM companies, and why has it maintained its advantage over the last 10 years. This study seeks to examine this question and present the mechanism behind its superiority. First, the modules of CIS products and development task flow are separated into modules by function and analyzed. The sensor core and system core require different design capabilities. The photodiode of the sensor core is designed through a combination and application of semiconductor physics and optical knowledge by highly expert design, device physics, and process engineers. In IDM companies, development is accomplished in a complementary manner with mutually integrated technologies. We note particularly that the boundary between companies in the horizontal specialization business in the sensor core design affects technological improvement and the speed of growth. During the heyday of SoC in 1990, technology was transferred and production outsourced from the world's top-class IDM to foundries. Based on the current situation two decades later, we analyzed the behavior at that time by back-casting and extracted five growth factors. Five growth opportunities for latecomers to the high-tech manufacturing industry were factors in the current implementation status and effects of the CIS business.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116933652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377494
Takayuki Nishimura, Tanaka Hisanori
In this paper, we describe a method for predicting product characteristics, its evaluation results, and application examples. Process equipment data is selected as an explanatory variable. By using an ensemble of gradient boosting trees and neural networks, we were able to construct a prediction model with higher accuracy than the conventional model. In addition, anomaly detection and analysis based on this prediction model are discussed.
{"title":"Anomaly detection and analysis by a gradient boosting trees and neural network ensemble model","authors":"Takayuki Nishimura, Tanaka Hisanori","doi":"10.1109/ISSM51728.2020.9377494","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377494","url":null,"abstract":"In this paper, we describe a method for predicting product characteristics, its evaluation results, and application examples. Process equipment data is selected as an explanatory variable. By using an ensemble of gradient boosting trees and neural networks, we were able to construct a prediction model with higher accuracy than the conventional model. In addition, anomaly detection and analysis based on this prediction model are discussed.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116466559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377530
Y. Daigo, Toru Watanabe, A. Ishiguro, S. Ishii, M. Kushibe, Yoshikazu Moriyama
Harmful effect of by-product on the growth of homo-epitaxial 4H-SiC films using a high speed wafer rotation vertical CVD method was suppressed. Influence of by-product, such as 3C-SiC deposit formed on a hot-wall and Si deposit formed on gas nozzles, on epitaxial growth was investigated in two comparative studies. The analysis of triangular defects with 3C-SiC down-falls on the films revealed that the most of the down-falls which were peeled from the hot-wall adhered to the wafers before the epitaxial growth. By increasing the wafer rotation speed to 300 rpm in the heat-up step before epitaxial growth, the down-falls dropped towards the wafer surface were effectively eliminated, and the maintenance period of the reactor could be increased more than 4 times compared with wafer rotation speed of 50 rpm during the heat-up step. Additionally, the relationship between Si deposit formed on the gas nozzles in the gas inlet and fluctuation of thickness and doping concentration of the films suggested that Si deposit formed on the gas nozzles acts as a trap site of Si source gas. By suppression of the Si deposit using optimizing gas flow condition, no significant fluctuation of thickness and doping concentration of the films were observed and the maintenance period of the gas nozzles could be increased more than 3 times compared with the epitaxial growth using the nozzles on which Si deposit was formed.
{"title":"Reduction of harmful effect due to by-product in CVD reactor for 4H-SiC epitaxy","authors":"Y. Daigo, Toru Watanabe, A. Ishiguro, S. Ishii, M. Kushibe, Yoshikazu Moriyama","doi":"10.1109/ISSM51728.2020.9377530","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377530","url":null,"abstract":"Harmful effect of by-product on the growth of homo-epitaxial 4H-SiC films using a high speed wafer rotation vertical CVD method was suppressed. Influence of by-product, such as 3C-SiC deposit formed on a hot-wall and Si deposit formed on gas nozzles, on epitaxial growth was investigated in two comparative studies. The analysis of triangular defects with 3C-SiC down-falls on the films revealed that the most of the down-falls which were peeled from the hot-wall adhered to the wafers before the epitaxial growth. By increasing the wafer rotation speed to 300 rpm in the heat-up step before epitaxial growth, the down-falls dropped towards the wafer surface were effectively eliminated, and the maintenance period of the reactor could be increased more than 4 times compared with wafer rotation speed of 50 rpm during the heat-up step. Additionally, the relationship between Si deposit formed on the gas nozzles in the gas inlet and fluctuation of thickness and doping concentration of the films suggested that Si deposit formed on the gas nozzles acts as a trap site of Si source gas. By suppression of the Si deposit using optimizing gas flow condition, no significant fluctuation of thickness and doping concentration of the films were observed and the maintenance period of the gas nozzles could be increased more than 3 times compared with the epitaxial growth using the nozzles on which Si deposit was formed.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"455 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125792822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-12-15DOI: 10.1109/ISSM51728.2020.9377512
Hiroaki Kato, Toshifumi Nishiguchi, Saya Shimomura, K. Miyashita, Kenya Kobayashi
Field-Plate (FP) MOSFET structure has been studied to get higher performance characteristics. To get low drift layer resistance, reduction of the trench width is one typical method with FP-MOSFET because it enables us to design the fine cell pitch of the FP-MOSFET. Trench width is relevant to trench angle. However large trench angle for better characteristics causes the variation of the dielectric breakdown voltage on the oxide film that separating the gate and source. Therefore, process window becomes always narrow to get excellent characteristic. For quality control of trench angle, we find that wafer the warpage is relevant to the trench angle. We confirmed the dependence by simulation and experiment. Furthermore, we acquire four correlation data related to the wafer warpage after field plate oxidation. Subsequently, we derived the regression equation for quality control and confirmed the validity of the equation.
{"title":"Quality Control of Trench Field Plate Power MOSFETs by Correlation of Trench Angle and Wafer Warpage","authors":"Hiroaki Kato, Toshifumi Nishiguchi, Saya Shimomura, K. Miyashita, Kenya Kobayashi","doi":"10.1109/ISSM51728.2020.9377512","DOIUrl":"https://doi.org/10.1109/ISSM51728.2020.9377512","url":null,"abstract":"Field-Plate (FP) MOSFET structure has been studied to get higher performance characteristics. To get low drift layer resistance, reduction of the trench width is one typical method with FP-MOSFET because it enables us to design the fine cell pitch of the FP-MOSFET. Trench width is relevant to trench angle. However large trench angle for better characteristics causes the variation of the dielectric breakdown voltage on the oxide film that separating the gate and source. Therefore, process window becomes always narrow to get excellent characteristic. For quality control of trench angle, we find that wafer the warpage is relevant to the trench angle. We confirmed the dependence by simulation and experiment. Furthermore, we acquire four correlation data related to the wafer warpage after field plate oxidation. Subsequently, we derived the regression equation for quality control and confirmed the validity of the equation.","PeriodicalId":270309,"journal":{"name":"2020 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127114033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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