Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771584
Kuan-Ying Chang, Kuan-Ting Chen, W. Ma, Y. Hwang
In this paper, we present an enhanced MUltiple SIgnal Classification (MUSIC) scheme for Direction of Arrival (DoA) scanning using a linear antenna array system. The goal is to construct an obstruction map based on the DoA scanning results for an autonomous mover when navigating in a pedestrian rich environment. A low complexity DoA estimation scheme, which eliminates the requirement of a computationally expensive Eigen Decomposition (ED) in conventional MUSIC algorithm, is developed. An Orthogonal Projection Matrix (OPM) scheme is used. Furthermore, a QR decomposition method is employed to implement the pseudo inverse matrix calculation required in the OPM scheme. This leads to a very computing efficient approach and facilitates real time implementation in hardware accelerators. The simulation results show that the proposed scheme can perform comparably to the conventional scheme at a much lower computing complexity.
{"title":"An Enhanced MUSIC DoA Scanning Scheme for Array Radar Sensing in Autonomous Movers","authors":"Kuan-Ying Chang, Kuan-Ting Chen, W. Ma, Y. Hwang","doi":"10.1109/AICAS.2019.8771584","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771584","url":null,"abstract":"In this paper, we present an enhanced MUltiple SIgnal Classification (MUSIC) scheme for Direction of Arrival (DoA) scanning using a linear antenna array system. The goal is to construct an obstruction map based on the DoA scanning results for an autonomous mover when navigating in a pedestrian rich environment. A low complexity DoA estimation scheme, which eliminates the requirement of a computationally expensive Eigen Decomposition (ED) in conventional MUSIC algorithm, is developed. An Orthogonal Projection Matrix (OPM) scheme is used. Furthermore, a QR decomposition method is employed to implement the pseudo inverse matrix calculation required in the OPM scheme. This leads to a very computing efficient approach and facilitates real time implementation in hardware accelerators. The simulation results show that the proposed scheme can perform comparably to the conventional scheme at a much lower computing complexity.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125574240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771517
Youhak Lee, Chulhee Lee, Hyuk-Jae Lee, Jin-Sung Kim
Fast object detection is important to enable a vision-based automated vending machine. This paper proposes a new scheme to enhance the operation speed of YOLOv3 by removing the computation for the region of non-interest. In order to avoid the accuracy drop by a removal of computation, characteristics of a convolutional layer and a YOLO layer are investigated, and a new processing method is proposed from experimental results. As a result, the operation speed is increased in proportion to the size of the region of non-interest. Experimental results show that the speed is improved by 3.29 times while the accuracy degradation is 2.81% in mAP-50.
{"title":"Fast Detection of Objects Using a YOLOv3 Network for a Vending Machine","authors":"Youhak Lee, Chulhee Lee, Hyuk-Jae Lee, Jin-Sung Kim","doi":"10.1109/AICAS.2019.8771517","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771517","url":null,"abstract":"Fast object detection is important to enable a vision-based automated vending machine. This paper proposes a new scheme to enhance the operation speed of YOLOv3 by removing the computation for the region of non-interest. In order to avoid the accuracy drop by a removal of computation, characteristics of a convolutional layer and a YOLO layer are investigated, and a new processing method is proposed from experimental results. As a result, the operation speed is increased in proportion to the size of the region of non-interest. Experimental results show that the speed is improved by 3.29 times while the accuracy degradation is 2.81% in mAP-50.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130289295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771626
Sheng-Yu He, Chih-Peng Fan
In this work, based on local features of sclera veins, a learning based sclera recognition design is proposed for identity identification. The proposed system is partitioned into two-stage computations. The first stage is the preprocessing process, which includes pupil location, iris segmentation, sclera segmentation, and sclera vein enhancement. At the second stage, by the scale-invariant feature transform (SIFT) technology, the sclera vein features are extracted after image enhancements. By the K-means scheme, the proposed design merges the similar features together to construct a dictionary to describe the interested group features. Next, the sclera images refers the dictionary to get the histogram of group features, and the group features are fed into the support vector machine (SVM) to train an identity classifier. Finally, the sclera recognition tests are evaluated. By the UBIRISv1 dataset, the experimental results show that the recognition accuracy is up to near 100%.
{"title":"SIFT Features and SVM Learning based Sclera Recognition Method with Efficient Sclera Segmentation for Identity Identification","authors":"Sheng-Yu He, Chih-Peng Fan","doi":"10.1109/AICAS.2019.8771626","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771626","url":null,"abstract":"In this work, based on local features of sclera veins, a learning based sclera recognition design is proposed for identity identification. The proposed system is partitioned into two-stage computations. The first stage is the preprocessing process, which includes pupil location, iris segmentation, sclera segmentation, and sclera vein enhancement. At the second stage, by the scale-invariant feature transform (SIFT) technology, the sclera vein features are extracted after image enhancements. By the K-means scheme, the proposed design merges the similar features together to construct a dictionary to describe the interested group features. Next, the sclera images refers the dictionary to get the histogram of group features, and the group features are fed into the support vector machine (SVM) to train an identity classifier. Finally, the sclera recognition tests are evaluated. By the UBIRISv1 dataset, the experimental results show that the recognition accuracy is up to near 100%.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129676954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771604
Tran Minh Quan, Takuyoshi Doike, C. D. Bui, K. Hayashi, S. Arata, A. Kobayashi, Md. Zahidul Islam, K. Niitsu
In this study, we developed an AI-based edge-intelligent hypoglycemia prediction system for the environment with low-periodic blood glucose level. By using long-short-term memory (LSTM), a specialized network for handling time series data among neural networks along with introducing alternate learning and inference, it was possible to predict the BG level with high accuracy. In order to achieve, the system for predicting the blood glucose level was created using LSTM, and the performance of the system was evaluated using the method of the classification problem. The system was successfully predicted the probability of occurrence of hypoglycemia after 30 min at approximately 80% times. Furthermore, it was demonstrated that accuracy is improved by alternately performing learning and prediction.
{"title":"AI-Based Edge-Intelligent Hypoglycemia Prediction System Using Alternate Learning and Inference Method for Blood Glucose Level Data with Low-periodicity","authors":"Tran Minh Quan, Takuyoshi Doike, C. D. Bui, K. Hayashi, S. Arata, A. Kobayashi, Md. Zahidul Islam, K. Niitsu","doi":"10.1109/AICAS.2019.8771604","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771604","url":null,"abstract":"In this study, we developed an AI-based edge-intelligent hypoglycemia prediction system for the environment with low-periodic blood glucose level. By using long-short-term memory (LSTM), a specialized network for handling time series data among neural networks along with introducing alternate learning and inference, it was possible to predict the BG level with high accuracy. In order to achieve, the system for predicting the blood glucose level was created using LSTM, and the performance of the system was evaluated using the method of the classification problem. The system was successfully predicted the probability of occurrence of hypoglycemia after 30 min at approximately 80% times. Furthermore, it was demonstrated that accuracy is improved by alternately performing learning and prediction.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129959568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771601
Donghyeon Lee, Sangheon Lee, H. Lee, Hyuk-Jae Lee, Kyujoong Lee
This paper presents a hardware design to process a CNN for single image super-resolution (SISR). Very deep convolutional network for image super-resolution (VDSR) is a promising algorithm for SISR but it is too complex to be implemented in hardware for commercial products. The proposed design aims to implement VDSR with relatively small hardware resources while minimizing a degradation of image quality. To this end, 1D reorganization of a convolution filter is proposed to reduce the number of multipliers. In addition, the 1D vertical filter is changed to reduce the internal SRAM to store the input feature map. For the implementation with a reasonable hardware cost, the numbers of layers and channels per layer, as well as the parameter resolution, are decreased without a significant reduction of image quality which is observed from simulation results. The 1D reorganization reduces the number of multiplies to 55.6% whereas the size reduction of 1D vertical filter halves the buffer size. As a result, the proposed design processes a full-HD video in real time with 8,143.5k gates and 333.1kB SRAM while the image quality is degraded by 1.06dB when compared with VDSR.
{"title":"Context-Preserving Filter Reorganization for VDSR-Based Super-resolution","authors":"Donghyeon Lee, Sangheon Lee, H. Lee, Hyuk-Jae Lee, Kyujoong Lee","doi":"10.1109/AICAS.2019.8771601","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771601","url":null,"abstract":"This paper presents a hardware design to process a CNN for single image super-resolution (SISR). Very deep convolutional network for image super-resolution (VDSR) is a promising algorithm for SISR but it is too complex to be implemented in hardware for commercial products. The proposed design aims to implement VDSR with relatively small hardware resources while minimizing a degradation of image quality. To this end, 1D reorganization of a convolution filter is proposed to reduce the number of multipliers. In addition, the 1D vertical filter is changed to reduce the internal SRAM to store the input feature map. For the implementation with a reasonable hardware cost, the numbers of layers and channels per layer, as well as the parameter resolution, are decreased without a significant reduction of image quality which is observed from simulation results. The 1D reorganization reduces the number of multiplies to 55.6% whereas the size reduction of 1D vertical filter halves the buffer size. As a result, the proposed design processes a full-HD video in real time with 8,143.5k gates and 333.1kB SRAM while the image quality is degraded by 1.06dB when compared with VDSR.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124600991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/aicas.2019.8771608
{"title":"AICAS 2019 Cover Page","authors":"","doi":"10.1109/aicas.2019.8771608","DOIUrl":"https://doi.org/10.1109/aicas.2019.8771608","url":null,"abstract":"","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126289002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771611
O. Krestinskaya, A. Bakambekova, A. P. James
This work proposes analog hardware implementation of Mean-Pooling Convolutional Neural Network (CNN) with 50% random dropout backpropagation training. We illustrate the effect of variabilities of real memristive devices on the performance of CNN, and tolerance to the input noise. The classification accuracy of CNN is approximately 93% independent on memristor variabilities and input noise. On-chip area and power consumption of analog 180nm CMOS CNN with WOx memristors are 0.09338995mm2 and 3.3992W, respectively.
{"title":"AMSNet: Analog Memristive System Architecture for Mean-Pooling with Dropout Convolutional Neural Network","authors":"O. Krestinskaya, A. Bakambekova, A. P. James","doi":"10.1109/AICAS.2019.8771611","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771611","url":null,"abstract":"This work proposes analog hardware implementation of Mean-Pooling Convolutional Neural Network (CNN) with 50% random dropout backpropagation training. We illustrate the effect of variabilities of real memristive devices on the performance of CNN, and tolerance to the input noise. The classification accuracy of CNN is approximately 93% independent on memristor variabilities and input noise. On-chip area and power consumption of analog 180nm CMOS CNN with WOx memristors are 0.09338995mm2 and 3.3992W, respectively.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126245217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771529
Chieh Tsou, Chi-Chung Liao, Shuenn-Yuh Lee
This paper presents a real-time identification system for epilepsy detection with a neural network (NN) classifier. The identification flow of the proposed system in animal testing is described as follows: 1. Two channel signals are collected from mouse brain. 2. Original signals are filtered in the appropriate bandwidth. 3. Six feature values are calculated. 4. Normal and epilepsy are classified by the classifier. The electroencephalography signal is measured from C57BL/6 mice in animal testing with a sampling rate of 400 Hz. The proposed system is verified on software design and hardware implementation. The software is designed in Matlab, and the hardware is implemented by the field programmable gate array (FPGA) platform. The chip is fabricated with TSMC 0.18 μm CMOS technology. The feature extraction function is realized in FPGA, and the NN architecture is implemented with a chip. The chosen feature sets from the previous measured animal testing data are amplitude, frequency bins, approximate entropy, and standard deviation. The accuracies of the proposed system are approximately 98.76% and 89.88% on software verification and hardware implementation, respectively. Results reveal that the proposed architecture is effective for epilepsy recognition.
{"title":"Epilepsy Identification System with Neural Network Hardware Implementation","authors":"Chieh Tsou, Chi-Chung Liao, Shuenn-Yuh Lee","doi":"10.1109/AICAS.2019.8771529","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771529","url":null,"abstract":"This paper presents a real-time identification system for epilepsy detection with a neural network (NN) classifier. The identification flow of the proposed system in animal testing is described as follows: 1. Two channel signals are collected from mouse brain. 2. Original signals are filtered in the appropriate bandwidth. 3. Six feature values are calculated. 4. Normal and epilepsy are classified by the classifier. The electroencephalography signal is measured from C57BL/6 mice in animal testing with a sampling rate of 400 Hz. The proposed system is verified on software design and hardware implementation. The software is designed in Matlab, and the hardware is implemented by the field programmable gate array (FPGA) platform. The chip is fabricated with TSMC 0.18 μm CMOS technology. The feature extraction function is realized in FPGA, and the NN architecture is implemented with a chip. The chosen feature sets from the previous measured animal testing data are amplitude, frequency bins, approximate entropy, and standard deviation. The accuracies of the proposed system are approximately 98.76% and 89.88% on software verification and hardware implementation, respectively. Results reveal that the proposed architecture is effective for epilepsy recognition.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"439 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125763058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771622
En-Jui Chang, Abbas Rahimi, L. Benini, A. Wu
To interact naturally and achieve mutual sympathy between humans and machines, emotion recognition is one of the most important function to realize advanced human-computer interaction devices. Due to the high correlation between emotion and involuntary physiological changes, physiological signals are a prime candidate for emotion analysis. However, due to the need of a huge amount of training data for a high-quality machine learning model, computational complexity becomes a major bottleneck. To overcome this issue, brain-inspired hyperdimensional (HD) computing, an energy-efficient and fast learning computational paradigm, has a high potential to achieve a balance between accuracy and the amount of necessary training data. We propose an HD Computing-based Multimodality Emotion Recognition (HDC-MER). HDCMER maps real-valued features to binary HD vectors using a random nonlinear function, and further encodes them over time, and fuses across different modalities including GSR, ECG, and EEG. The experimental results show that, compared to the best method using the full training data, HDC-MER achieves higher classification accuracy for both valence (83.2% vs. 80.1%) and arousal (70.1% vs. 68.4%) using only 1/4 training data. HDC-MER also achieves at least 5% higher averaged accuracy compared to all the other methods in any point along the learning curve.
为了实现人与机器之间的自然交互和相互同情，情感识别是实现先进人机交互设备的重要功能之一。由于情绪与非自愿生理变化之间的高度相关性，生理信号是情绪分析的主要候选者。然而，由于一个高质量的机器学习模型需要大量的训练数据，计算复杂性成为一个主要的瓶颈。为了克服这一问题，脑启发的超维计算(HD)作为一种高效且快速的学习计算范式，在准确性和必要的训练数据量之间取得平衡方面具有很大的潜力。我们提出了一种基于高清计算的多模态情感识别(HDC-MER)。HDCMER使用随机非线性函数将实值特征映射到二进制高清矢量，并随着时间的推移对它们进行进一步编码，并融合不同的模态，包括GSR, ECG和EEG。实验结果表明，与使用完整训练数据的最佳方法相比，仅使用1/4训练数据的HDC-MER在效价(83.2% vs. 80.1%)和唤醒(70.1% vs. 68.4%)两方面都取得了更高的分类准确率。与其他方法相比，HDC-MER在学习曲线的任何一点上的平均精度至少高出5%。
{"title":"Hyperdimensional Computing-based Multimodality Emotion Recognition with Physiological Signals","authors":"En-Jui Chang, Abbas Rahimi, L. Benini, A. Wu","doi":"10.1109/AICAS.2019.8771622","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771622","url":null,"abstract":"To interact naturally and achieve mutual sympathy between humans and machines, emotion recognition is one of the most important function to realize advanced human-computer interaction devices. Due to the high correlation between emotion and involuntary physiological changes, physiological signals are a prime candidate for emotion analysis. However, due to the need of a huge amount of training data for a high-quality machine learning model, computational complexity becomes a major bottleneck. To overcome this issue, brain-inspired hyperdimensional (HD) computing, an energy-efficient and fast learning computational paradigm, has a high potential to achieve a balance between accuracy and the amount of necessary training data. We propose an HD Computing-based Multimodality Emotion Recognition (HDC-MER). HDCMER maps real-valued features to binary HD vectors using a random nonlinear function, and further encodes them over time, and fuses across different modalities including GSR, ECG, and EEG. The experimental results show that, compared to the best method using the full training data, HDC-MER achieves higher classification accuracy for both valence (83.2% vs. 80.1%) and arousal (70.1% vs. 68.4%) using only 1/4 training data. HDC-MER also achieves at least 5% higher averaged accuracy compared to all the other methods in any point along the learning curve.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126009224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771615
Jinzhan Peng, Lu Tian, Xijie Jia, Haotian Guo, Yongsheng Xu, Dongliang Xie, Hong Luo, Yi Shan, Yu Wang
Advanced Driver-Assistance Systems (ADAS) can help drivers in the driving process and increase the driving safety by automatically detecting objects, doing basic classification, implementing safeguards, etc. ADAS integrate multiple subsystems including object detection, scene segmentation, lane detection, and so on. Most algorithms are now designed for one specific task, while such separate approaches will be inefficient in ADAS which consists of many modules. In this paper, we establish a multi-task learning framework for lane detection, semantic segmentation, 2D object detection, and orientation prediction on FPGA. The performance on FPGA is optimized by software and hardware co-design. The system deployed on Xilinx zu9 board achieves 55 FPS, which meets real-time processing requirement.
{"title":"Multi-task ADAS system on FPGA","authors":"Jinzhan Peng, Lu Tian, Xijie Jia, Haotian Guo, Yongsheng Xu, Dongliang Xie, Hong Luo, Yi Shan, Yu Wang","doi":"10.1109/AICAS.2019.8771615","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771615","url":null,"abstract":"Advanced Driver-Assistance Systems (ADAS) can help drivers in the driving process and increase the driving safety by automatically detecting objects, doing basic classification, implementing safeguards, etc. ADAS integrate multiple subsystems including object detection, scene segmentation, lane detection, and so on. Most algorithms are now designed for one specific task, while such separate approaches will be inefficient in ADAS which consists of many modules. In this paper, we establish a multi-task learning framework for lane detection, semantic segmentation, 2D object detection, and orientation prediction on FPGA. The performance on FPGA is optimized by software and hardware co-design. The system deployed on Xilinx zu9 board achieves 55 FPS, which meets real-time processing requirement.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115894342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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