Pub Date : 2019-03-01DOI: 10.1109/aicas.2019.8771564
{"title":"AICAS 2019 Message from the Honorary Chair and General Co-Chairs","authors":"","doi":"10.1109/aicas.2019.8771564","DOIUrl":"https://doi.org/10.1109/aicas.2019.8771564","url":null,"abstract":"","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123876462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771602
Sang-gyun Gi, Injune Yeo, Byung-geun Lee
This paper presents a circuit for spike-timing dependent plasticity (STDP) learning of a non-volatile memory (NVM) based spiking neural network (SNN). Unlike conventional hardware for implementation of STDP learning, the proposed circuit does not require additional memory, amplifiers, or an STDP spike generator. Instead, the circuit utilizes the comparison time information of the dynamic comparator to implement a non-linear transfer curve of STDP learning. The circuit includes a dynamic comparator, NVM device, and some digital circuitry to write the conductance of NVM according to the STDP learning rule. Finally, the conductance response model and designed circuit for the STDP learning are used to compare the simulation results of STDP with mathematical STDP. Applications of the proposed circuit are in the design of NVM-based SNN hardware or other bio-inspired hardware systems.
{"title":"Implementation of STDP Learning for Non-volatile Memory-based Spiking Neural Network using Comparator Metastability","authors":"Sang-gyun Gi, Injune Yeo, Byung-geun Lee","doi":"10.1109/AICAS.2019.8771602","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771602","url":null,"abstract":"This paper presents a circuit for spike-timing dependent plasticity (STDP) learning of a non-volatile memory (NVM) based spiking neural network (SNN). Unlike conventional hardware for implementation of STDP learning, the proposed circuit does not require additional memory, amplifiers, or an STDP spike generator. Instead, the circuit utilizes the comparison time information of the dynamic comparator to implement a non-linear transfer curve of STDP learning. The circuit includes a dynamic comparator, NVM device, and some digital circuitry to write the conductance of NVM according to the STDP learning rule. Finally, the conductance response model and designed circuit for the STDP learning are used to compare the simulation results of STDP with mathematical STDP. Applications of the proposed circuit are in the design of NVM-based SNN hardware or other bio-inspired hardware systems.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128499499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel sleep-status discrimination system by adopting a motion sensing mattress which detects the user’s activities on bed including the movement of head, chest, legs and feet. Unlike traditional methods like Polysomnography (PSG) which needs electrical equipment connected to users, or like wrist actigraphy which needs to be contact to users, the proposed system distinguishes sleep states in a non-conscious and non-contact way. The proposed system is built by a machine learning technique in the offline stage, and distinguishes sleep states in the online stage by using our designed sleep-status discrimination algorithm. The experimental results illustrate that the proposed method efficiently distinguishes sleep statuses without using a wearable device contact to body or using PSG diagnosis undertaken at hospitals.
{"title":"Machine Learning Based Sleep-Status Discrimination Using a Motion Sensing Mattress","authors":"Chia-Chien Wang, Tsung-Yi Fan Chiang, Shih-Hau Fang, Chieh-Ju Li, Yeh-Liang Hsu","doi":"10.1109/AICAS.2019.8771632","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771632","url":null,"abstract":"This paper presents a novel sleep-status discrimination system by adopting a motion sensing mattress which detects the user’s activities on bed including the movement of head, chest, legs and feet. Unlike traditional methods like Polysomnography (PSG) which needs electrical equipment connected to users, or like wrist actigraphy which needs to be contact to users, the proposed system distinguishes sleep states in a non-conscious and non-contact way. The proposed system is built by a machine learning technique in the offline stage, and distinguishes sleep states in the online stage by using our designed sleep-status discrimination algorithm. The experimental results illustrate that the proposed method efficiently distinguishes sleep statuses without using a wearable device contact to body or using PSG diagnosis undertaken at hospitals.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124743025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/aicas.2019.8771618
{"title":"AICAS 2019 Table of Contents","authors":"","doi":"10.1109/aicas.2019.8771618","DOIUrl":"https://doi.org/10.1109/aicas.2019.8771618","url":null,"abstract":"","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123505227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771573
Yang Zhao, Zhongxia Shang, Y. Lian
Multiplier is a critical building block in artificial neural network (ANN). The precision and connection structure of the multiplier should be optimized for an ANN to achieve the best energy, speed and area efficiency. Changes in ANN application and CMOS process often result in the redesign of the multiplier. This paper presents an auto generation method for high-performance fixed-point multiplier based on three techniques, i.e. Modified Booth Encoding (MBE) scheme, improved three-dimensional reduction method (ITDM) and mixed parallel pipelining (MPP). The MBE is customized for ReLU activation function based ANN to remove the sign bit of the multiplicand to save area. The ITDM further shorts the critical path by changing the position of half adder in the conventional TDM. The proposed MPP divides the structures into different stages for parallel and pipelined implementation. The auto generated multiplier speed is 4.04 times faster and the layout is 29% denser and more regular than the conventional MBE combining with TDM method based multiplier.
{"title":"Auto Generation of High-Performance Fixed-Point Multiplier for Artificial Neural Networks","authors":"Yang Zhao, Zhongxia Shang, Y. Lian","doi":"10.1109/AICAS.2019.8771573","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771573","url":null,"abstract":"Multiplier is a critical building block in artificial neural network (ANN). The precision and connection structure of the multiplier should be optimized for an ANN to achieve the best energy, speed and area efficiency. Changes in ANN application and CMOS process often result in the redesign of the multiplier. This paper presents an auto generation method for high-performance fixed-point multiplier based on three techniques, i.e. Modified Booth Encoding (MBE) scheme, improved three-dimensional reduction method (ITDM) and mixed parallel pipelining (MPP). The MBE is customized for ReLU activation function based ANN to remove the sign bit of the multiplicand to save area. The ITDM further shorts the critical path by changing the position of half adder in the conventional TDM. The proposed MPP divides the structures into different stages for parallel and pipelined implementation. The auto generated multiplier speed is 4.04 times faster and the layout is 29% denser and more regular than the conventional MBE combining with TDM method based multiplier.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133767319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771612
Kuan-Hsien Liu, Hsin-Hua Liu, S. Pei, Tsung-Jung Liu, Chun-Te Chang
In this paper, we contribute an age estimation method towards dealing with low quality face images. This is a practical and important problem because an image we received may have low resolution or be affected by some noise via transmission. Upon reviewing the literature on facial age estimation, we notice that few articles tackle this low quality image based facial age estimation problem. In our framework, we propose a newly designed deep convolutional neural networks architecture, consisting of five major steps. Firstly, we propose to use a super-resolution method to enhance the input images. Secondly, a data augmentation step is utilized to ease the training procedure. Thirdly, we use a deep network to conduct gender grouping. Fourthly, two recently proposed deep networks are modified with depthwise separable convolutions to perform age estimation within male and female groups. Finally, a fusion procedure is added to further boost age estimation accuracy. In the experiment, we use two benchmark datasets, IMDB-WIKI and MORPH-II, to verify our proposed method and also show a significantly performance improvement over two state-of-the-art deep CNN models.
{"title":"Age Estimation on Low Quality Face Images","authors":"Kuan-Hsien Liu, Hsin-Hua Liu, S. Pei, Tsung-Jung Liu, Chun-Te Chang","doi":"10.1109/AICAS.2019.8771612","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771612","url":null,"abstract":"In this paper, we contribute an age estimation method towards dealing with low quality face images. This is a practical and important problem because an image we received may have low resolution or be affected by some noise via transmission. Upon reviewing the literature on facial age estimation, we notice that few articles tackle this low quality image based facial age estimation problem. In our framework, we propose a newly designed deep convolutional neural networks architecture, consisting of five major steps. Firstly, we propose to use a super-resolution method to enhance the input images. Secondly, a data augmentation step is utilized to ease the training procedure. Thirdly, we use a deep network to conduct gender grouping. Fourthly, two recently proposed deep networks are modified with depthwise separable convolutions to perform age estimation within male and female groups. Finally, a fusion procedure is added to further boost age estimation accuracy. In the experiment, we use two benchmark datasets, IMDB-WIKI and MORPH-II, to verify our proposed method and also show a significantly performance improvement over two state-of-the-art deep CNN models.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129868761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771476
Lin Li, Peter Deaville, A. Sapio, L. Anttila, M. Valkama, M. Wolf, S. Bhattacharyya
Digital predistortion (DPD) has important applications in wireless communication for smart systems, such as, for example, in Internet of Things (IoT) applications for smart cities. DPD is used in wireless communication transmitters to counteract distortions that arise from nonlinearities, such as those related to amplifier characteristics and local oscillator leakage. In this paper, we propose an algorithm-architecture-integrated framework for design and implementation of adaptive DPD systems. The proposed framework provides energy-efficient, real-time DPD performance, and enables efficient reconfiguration of DPD architectures so that communication can be dynamically optimized based on time-varying communication requirements. Our adaptive DPD design framework applies Markov Decision Processes (MDPs) in novel ways to generate optimized runtime control policies for DPD systems. We present a GPU-based adaptive DPD system that is derived using our design framework, and demonstrate its efficiency through extensive experiments.
{"title":"A Framework for Design and Implementation of Adaptive Digital Predistortion Systems","authors":"Lin Li, Peter Deaville, A. Sapio, L. Anttila, M. Valkama, M. Wolf, S. Bhattacharyya","doi":"10.1109/AICAS.2019.8771476","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771476","url":null,"abstract":"Digital predistortion (DPD) has important applications in wireless communication for smart systems, such as, for example, in Internet of Things (IoT) applications for smart cities. DPD is used in wireless communication transmitters to counteract distortions that arise from nonlinearities, such as those related to amplifier characteristics and local oscillator leakage. In this paper, we propose an algorithm-architecture-integrated framework for design and implementation of adaptive DPD systems. The proposed framework provides energy-efficient, real-time DPD performance, and enables efficient reconfiguration of DPD architectures so that communication can be dynamically optimized based on time-varying communication requirements. Our adaptive DPD design framework applies Markov Decision Processes (MDPs) in novel ways to generate optimized runtime control policies for DPD systems. We present a GPU-based adaptive DPD system that is derived using our design framework, and demonstrate its efficiency through extensive experiments.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114393539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771542
Shijin Song, Yongxin Zhu, Junjie Hou, Yu Zheng, Tian Huang, Sen Du
As the killer application of artificial intelligence, autonomous driving is making fundamental transformations to the transportation industry. Computer vision based on deep learning is among the enabling technologies. However, small objects around vehicles are difficult to detect because of poor visual features within small objects as well as insufficient valid samples of small objections. In this paper, we propose an end-to-end detector model based on convolutional neutral network (CNN) to enhance visual features of small traffic signs in real scenarios. With those enhanced features, we manage to obtain an efficient inference model after training. We further make preliminary comparison with Fast R-CNN and Faster R-CNN models. Experimental results indicate that our model outperforms the others by more than 10% improvement in terms of accuracy and recall.
{"title":"Improved Convolutional Neutral Network Based Model for Small Visual Object Detection in Autonomous Driving","authors":"Shijin Song, Yongxin Zhu, Junjie Hou, Yu Zheng, Tian Huang, Sen Du","doi":"10.1109/AICAS.2019.8771542","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771542","url":null,"abstract":"As the killer application of artificial intelligence, autonomous driving is making fundamental transformations to the transportation industry. Computer vision based on deep learning is among the enabling technologies. However, small objects around vehicles are difficult to detect because of poor visual features within small objects as well as insufficient valid samples of small objections. In this paper, we propose an end-to-end detector model based on convolutional neutral network (CNN) to enhance visual features of small traffic signs in real scenarios. With those enhanced features, we manage to obtain an efficient inference model after training. We further make preliminary comparison with Fast R-CNN and Faster R-CNN models. Experimental results indicate that our model outperforms the others by more than 10% improvement in terms of accuracy and recall.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114872540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A codec based on the excited linear prediction (CELP) speech compression method adopting a denoising autoencoder with spectral compensation (DAE-SC) for quality and intelligibility enhancement is proposed in this paper. The sizes of CELP parameters in the encoder are carefully pruned to achieve a higher compression rate. To recover the speech quality and intelligibility degradation due to the pruned CELP parameters, a DAE-SC network with three hidden layers is employed in the decoder. Compared with the conventional CELP codec at a 9.6k bps transmission rate, the proposed speech codec achieves extra 21.9% bit rate reduction with comparable speech quality and intelligibility that are evaluated by four commonly used speech performance metrics.
{"title":"A Pruned-CELP Speech Codec Using Denoising Autoencoder with Spectral Compensation for Quality and Intelligibility Enhancement","authors":"Yu-Ting Lo, Syu-Siang Wang, Yu Tsao, Sheng-Yu Peng","doi":"10.1109/AICAS.2019.8771507","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771507","url":null,"abstract":"A codec based on the excited linear prediction (CELP) speech compression method adopting a denoising autoencoder with spectral compensation (DAE-SC) for quality and intelligibility enhancement is proposed in this paper. The sizes of CELP parameters in the encoder are carefully pruned to achieve a higher compression rate. To recover the speech quality and intelligibility degradation due to the pruned CELP parameters, a DAE-SC network with three hidden layers is employed in the decoder. Compared with the conventional CELP codec at a 9.6k bps transmission rate, the proposed speech codec achieves extra 21.9% bit rate reduction with comparable speech quality and intelligibility that are evaluated by four commonly used speech performance metrics.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134500682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-01DOI: 10.1109/AICAS.2019.8771510
Wei-Fen Lin, Der-Yu Tsai, Luba Tang, C. Hsieh, Cheng-Yi Chou, P. Chang, Luis Hsu
This paper presents ONNC (Open Neural Network Compiler), a retargetable compilation framework designed to connect ONNX (Open Neural Network Exchange) models to proprietary deep learning accelerators (DLAs). The intermediate representations (IRs) of ONNC have one-to-one mapping to ONNX IRs, thus making porting ONNC to proprietary DLAs much simpler than other compilation frameworks such as TVM and Glow especially for hardware with coarse-grained operators that are not part of the generic IRs in the LLVM backend. ONNC also has a flexible pass manager designed to support compiler optimizations at all levels. A docker image of ONNC bundled with a Vanilla backend is released with this paper to enable fast porting to new hardware targets. To illustrate how an ONNC-based toolkit guides our research and development in DLA design, we present a case study on compiler optimizations for activation memory consumption. The study shows that the Best-Fit algorithm with a proposed heuristic and a reordering scheme may act as a near-optimal strategy, getting the memory consumption close to the ideal lower bound in 11 of 12 models from the ONNX model zoo. To our best knowledge, ONNC is the first open source compilation framework that is specially designed to support the ONNX-based models for both commercial and research projects for deep learning applications.
{"title":"ONNC: A Compilation Framework Connecting ONNX to Proprietary Deep Learning Accelerators","authors":"Wei-Fen Lin, Der-Yu Tsai, Luba Tang, C. Hsieh, Cheng-Yi Chou, P. Chang, Luis Hsu","doi":"10.1109/AICAS.2019.8771510","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771510","url":null,"abstract":"This paper presents ONNC (Open Neural Network Compiler), a retargetable compilation framework designed to connect ONNX (Open Neural Network Exchange) models to proprietary deep learning accelerators (DLAs). The intermediate representations (IRs) of ONNC have one-to-one mapping to ONNX IRs, thus making porting ONNC to proprietary DLAs much simpler than other compilation frameworks such as TVM and Glow especially for hardware with coarse-grained operators that are not part of the generic IRs in the LLVM backend. ONNC also has a flexible pass manager designed to support compiler optimizations at all levels. A docker image of ONNC bundled with a Vanilla backend is released with this paper to enable fast porting to new hardware targets. To illustrate how an ONNC-based toolkit guides our research and development in DLA design, we present a case study on compiler optimizations for activation memory consumption. The study shows that the Best-Fit algorithm with a proposed heuristic and a reordering scheme may act as a near-optimal strategy, getting the memory consumption close to the ideal lower bound in 11 of 12 models from the ONNX model zoo. To our best knowledge, ONNC is the first open source compilation framework that is specially designed to support the ONNX-based models for both commercial and research projects for deep learning applications.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130528911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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