Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559583
Autthasith Arrayangkool, C. Warisarn, L. Myint, P. Kovintavewat
In bit-patterned magnetic recording (BPMR), intersymbol interference (ISI) and inter-track interference (ITI) become a major impairment due to small bit and track pitches. One way to alleviate ISI and ITI is to encode the data sequence before recording. In general, two-dimensional (2D) coding scheme requires many redundant bits, thus lowering the code rate. This paper proposes a novel 2D coding scheme (referred to as a simple recorded-bit patterning (RBP) scheme) with high code rate to combat both ISI and ITI effects. Specifically, the data bits will first be patterned by finding the best data pattern based on a look-up table that can avoid severe ISI and ITI effects before recording. Simulation results indicate that the proposed scheme can provide a significant performance improvement if compared to the system without coding.
{"title":"A simple recorded-bit patterning scheme for bit-patterned media recording","authors":"Autthasith Arrayangkool, C. Warisarn, L. Myint, P. Kovintavewat","doi":"10.1109/ECTICON.2013.6559583","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559583","url":null,"abstract":"In bit-patterned magnetic recording (BPMR), intersymbol interference (ISI) and inter-track interference (ITI) become a major impairment due to small bit and track pitches. One way to alleviate ISI and ITI is to encode the data sequence before recording. In general, two-dimensional (2D) coding scheme requires many redundant bits, thus lowering the code rate. This paper proposes a novel 2D coding scheme (referred to as a simple recorded-bit patterning (RBP) scheme) with high code rate to combat both ISI and ITI effects. Specifically, the data bits will first be patterned by finding the best data pattern based on a look-up table that can avoid severe ISI and ITI effects before recording. Simulation results indicate that the proposed scheme can provide a significant performance improvement if compared to the system without coding.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132594783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559547
B. Shakya, E. Nantajeewarawat
A design pattern is a general reusable solution to a commonly occurring problem in software design. It provides a template for solving a problem and can be used in many different situations. Design patterns help designers to reuse successful designs by basing new designs on prior experience. This research proposes a framework for generating UML sequence diagrams from requirements specified in the form of operation contracts, using design patterns as expert knowledge. Design patterns are represented using Ontology Web Language (OWL) and Semantic Web Rule Language (SWRL). From input operation contracts and class diagrams, which are also represented in OWL, Jess Rule Engine is used for execution of SWRL rules to derive output sequence diagrams. An application of the framework is demonstrated.
{"title":"Towards generation of sequence diagrams from operation contracts and design patterns","authors":"B. Shakya, E. Nantajeewarawat","doi":"10.1109/ECTICON.2013.6559547","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559547","url":null,"abstract":"A design pattern is a general reusable solution to a commonly occurring problem in software design. It provides a template for solving a problem and can be used in many different situations. Design patterns help designers to reuse successful designs by basing new designs on prior experience. This research proposes a framework for generating UML sequence diagrams from requirements specified in the form of operation contracts, using design patterns as expert knowledge. Design patterns are represented using Ontology Web Language (OWL) and Semantic Web Rule Language (SWRL). From input operation contracts and class diagrams, which are also represented in OWL, Jess Rule Engine is used for execution of SWRL rules to derive output sequence diagrams. An application of the framework is demonstrated.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116205598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559468
P. Sriploy, P. Uthansakul, M. Uthansakul
From literatures, path loss effect has not been taken into account when analyzing beamforming performance of distributed or cooperative beamforming networks such as Wireless Sensor Networks (WSNs). Therefore, this paper investigates into the mentioned effect on beamforming performance of WSNs through computer simulation. The obtained results indicate that the path loss occurring between the networks and destination extremely degrades beam pattern and beamforming gain.
{"title":"Effect of path loss on the distributed beamforming for Wireless Sensor Networks","authors":"P. Sriploy, P. Uthansakul, M. Uthansakul","doi":"10.1109/ECTICON.2013.6559468","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559468","url":null,"abstract":"From literatures, path loss effect has not been taken into account when analyzing beamforming performance of distributed or cooperative beamforming networks such as Wireless Sensor Networks (WSNs). Therefore, this paper investigates into the mentioned effect on beamforming performance of WSNs through computer simulation. The obtained results indicate that the path loss occurring between the networks and destination extremely degrades beam pattern and beamforming gain.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131826317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559528
T. Suwanasri, C. Suwanasri, Sakda Nobnorp, S. Wattanawongpitak
The requirement to renovate the deteriorated and aging electrical asset is now playing a significant role on the quality of electrical supply. Thus this paper presents the performance evaluation of 115 kV circuit breaker in power substation. The degraded high voltage circuit breakers should be assessed and clearly identified as supported reasons for planning the renovation task of electrical asset. This performance assessment based on symptom, failed-type and obsolescence criteria are used to clearly identify the visible deterioration. The proposed method was implemented with sixteen circuit breakers in two high voltage substations in Thai electrical utility as examples for illustrating the application of the method. The results show that performances of high voltage circuit breakers are in three stages for healthy, moderate, and risk performance. In the risk stage, the circuit breaker should be intensively cared. The proposed method can be further adapted to other high voltage equipment in power substation.
{"title":"Performance evaluation based on symptom, failed-type and obsolescence criteria of high voltage circuit breaker","authors":"T. Suwanasri, C. Suwanasri, Sakda Nobnorp, S. Wattanawongpitak","doi":"10.1109/ECTICON.2013.6559528","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559528","url":null,"abstract":"The requirement to renovate the deteriorated and aging electrical asset is now playing a significant role on the quality of electrical supply. Thus this paper presents the performance evaluation of 115 kV circuit breaker in power substation. The degraded high voltage circuit breakers should be assessed and clearly identified as supported reasons for planning the renovation task of electrical asset. This performance assessment based on symptom, failed-type and obsolescence criteria are used to clearly identify the visible deterioration. The proposed method was implemented with sixteen circuit breakers in two high voltage substations in Thai electrical utility as examples for illustrating the application of the method. The results show that performances of high voltage circuit breakers are in three stages for healthy, moderate, and risk performance. In the risk stage, the circuit breaker should be intensively cared. The proposed method can be further adapted to other high voltage equipment in power substation.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129391893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559584
Chutitham Apapipat, K. Audomvongseree
The uncertainty of wind speed causing fluctuations of generated output power can be remedied by installation of battery to wind power generation system. The purpose of this paper is to determine the appropriate battery capacity to cope with this problem. The proposed algorithm begins with wind speed model. Then, the output power can be calculated based on Doubly Fed Induction Generator (DFIG) dynamic model. The rest of the interconnected power system is modeled as an infinite bus. The battery used in this analysis is lead-acid battery. The proposed algorithm has been tested with a constructed test system. Satisfactory results were obtained.
{"title":"Determination of the optimal battery capacity of a wind generation system with power fluctuation consideration","authors":"Chutitham Apapipat, K. Audomvongseree","doi":"10.1109/ECTICON.2013.6559584","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559584","url":null,"abstract":"The uncertainty of wind speed causing fluctuations of generated output power can be remedied by installation of battery to wind power generation system. The purpose of this paper is to determine the appropriate battery capacity to cope with this problem. The proposed algorithm begins with wind speed model. Then, the output power can be calculated based on Doubly Fed Induction Generator (DFIG) dynamic model. The rest of the interconnected power system is modeled as an infinite bus. The battery used in this analysis is lead-acid battery. The proposed algorithm has been tested with a constructed test system. Satisfactory results were obtained.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133571450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559609
Tanawat Promtaveepong, N. Prompoon
The software development life cycle consists of many steps, such as the planning stage, the design stage, the development stage etc. Each step produce assets that can be reused, based on the assets' context, which can help reduce the initial capital and the time needed to develop software systems. At the same time, it improves the quality and productivity. However this is not possible if the organization is lacking best practices. This research proposes a Reuse Asset Management Process, based on the standard of ISO/IEC 12207:2008 and practices of the IEEE 1517:2010 standard, which deals with the software detailed design process, to serve as a guideline for process management.
{"title":"Process definition for reuse asset management process for software detailed design","authors":"Tanawat Promtaveepong, N. Prompoon","doi":"10.1109/ECTICON.2013.6559609","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559609","url":null,"abstract":"The software development life cycle consists of many steps, such as the planning stage, the design stage, the development stage etc. Each step produce assets that can be reused, based on the assets' context, which can help reduce the initial capital and the time needed to develop software systems. At the same time, it improves the quality and productivity. However this is not possible if the organization is lacking best practices. This research proposes a Reuse Asset Management Process, based on the standard of ISO/IEC 12207:2008 and practices of the IEEE 1517:2010 standard, which deals with the software detailed design process, to serve as a guideline for process management.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133080998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559497
Sirinee Thongpanja, A. Phinyomark, C. Limsakul, P. Phukpattaranont
The probability density function (PDF) of surface electromyography (sEMG) signals can be modelled with the Gaussian and Laplacian PDFs. However, the sEMG PDF is dependent on the levels of contraction of the muscles. Different techniques have been proposed for testing Gaussianity levels of sEMG, i.e., kurtosis, negentropy, and mean bicoherence power, whereas the suitable technique has not been reported yet. In this paper, the experimental sEMG PDF and its relationship with the levels of muscle contraction were re-examined and the suitable Gaussianity test was presented based on sEMG acquired from biceps brachii muscle during the static contraction of the muscle at different load levels. The results show that the EMG PDF was non-Gaussian at low level of contraction and it tends to be more Gaussian at high level of contraction. Kurtosis and negentropy decreased as muscle load levels increased, whereas the consistent results between mean bicoherence power and muscle load levels were not found. Negentropy showed a better linear relationship with the levels of contraction of biceps brachii than other techniques.
{"title":"Probability density of electromyography signal for different levels of contraction of biceps brachii","authors":"Sirinee Thongpanja, A. Phinyomark, C. Limsakul, P. Phukpattaranont","doi":"10.1109/ECTICON.2013.6559497","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559497","url":null,"abstract":"The probability density function (PDF) of surface electromyography (sEMG) signals can be modelled with the Gaussian and Laplacian PDFs. However, the sEMG PDF is dependent on the levels of contraction of the muscles. Different techniques have been proposed for testing Gaussianity levels of sEMG, i.e., kurtosis, negentropy, and mean bicoherence power, whereas the suitable technique has not been reported yet. In this paper, the experimental sEMG PDF and its relationship with the levels of muscle contraction were re-examined and the suitable Gaussianity test was presented based on sEMG acquired from biceps brachii muscle during the static contraction of the muscle at different load levels. The results show that the EMG PDF was non-Gaussian at low level of contraction and it tends to be more Gaussian at high level of contraction. Kurtosis and negentropy decreased as muscle load levels increased, whereas the consistent results between mean bicoherence power and muscle load levels were not found. Negentropy showed a better linear relationship with the levels of contraction of biceps brachii than other techniques.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"294 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122092745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559510
T. Thanasaksiri
This paper analyzes the lightning performance of 22 kV single and double circuits overhead distribution lines by means of installation the additional underbuilt shield wire. The simulations have been implemented using ATPDraw and calculations by applying equations taken from IEEE std. 1410-2010. The total number of flashovers, direct stroke and induced voltage flashovers, have been evaluated. The additional underbuilt shield wire sizes and the placement locations have been determined.
{"title":"Improving the lightning performance of overhead lines applying additional underbuilt shield wire","authors":"T. Thanasaksiri","doi":"10.1109/ECTICON.2013.6559510","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559510","url":null,"abstract":"This paper analyzes the lightning performance of 22 kV single and double circuits overhead distribution lines by means of installation the additional underbuilt shield wire. The simulations have been implemented using ATPDraw and calculations by applying equations taken from IEEE std. 1410-2010. The total number of flashovers, direct stroke and induced voltage flashovers, have been evaluated. The additional underbuilt shield wire sizes and the placement locations have been determined.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123610485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559529
Salita Sombatsiri, K. Kobashi, K. Sakanushi, Y. Takeuchi, M. Imai
Recently, a design space exploration problem has been raised with an attempt to reduce time and resources for designing an optimal system-on-a-chip (SoC). This research proposes a design space exploration method considering the architectures containing an AMBA shared bus. The AMBA standard bus specification widely used in many SoC industries as an efficient on-chip interconnect. The proposed method explores the architecture candidates containing AMBA shared buses and their parameters. It also estimates the execution time and the area of each architecture. The first experiment has indicated that the area estimation result is different from the logic synthesis result by less than 1 %. The second experiment has demonstrated that the proposed method found 7 Pareto solutions among over 4 billion architectures in the design space in 19 hours.
{"title":"An AMBA hierarchical shared bus architecture design space exploration method considering pipeline, burst and split transaction","authors":"Salita Sombatsiri, K. Kobashi, K. Sakanushi, Y. Takeuchi, M. Imai","doi":"10.1109/ECTICON.2013.6559529","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559529","url":null,"abstract":"Recently, a design space exploration problem has been raised with an attempt to reduce time and resources for designing an optimal system-on-a-chip (SoC). This research proposes a design space exploration method considering the architectures containing an AMBA shared bus. The AMBA standard bus specification widely used in many SoC industries as an efficient on-chip interconnect. The proposed method explores the architecture candidates containing AMBA shared buses and their parameters. It also estimates the execution time and the area of each architecture. The first experiment has indicated that the area estimation result is different from the logic synthesis result by less than 1 %. The second experiment has demonstrated that the proposed method found 7 Pareto solutions among over 4 billion architectures in the design space in 19 hours.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124849384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-15DOI: 10.1109/ECTICON.2013.6559495
Worachat Chawarut, Lilakiatsakun Woraphon
Performance and energy management in cloud data-center are major concerns that cloud service providers have to encounter due to computing demand has been increasing. Many researchers have proposed solutions to reduce energy consumption such as scheduling and migration while maintaining an appropriate level of performance to customers. In this paper, we propose a new CPU re-allocation algorithm that combined DVFS concept with live migration technique to improve efficiency of energy management and adaptation scheme on real-time service. The proposed algorithm works as three characteristics that are Longest Completion Time (LCT), Highest Utilization (HU) and Lowest Utilization (LU). The result shows the reduction of energy consumption and execution time upon applied characteristics and adaptation scheme.
{"title":"Energy-aware and real-time service management in cloud computing","authors":"Worachat Chawarut, Lilakiatsakun Woraphon","doi":"10.1109/ECTICON.2013.6559495","DOIUrl":"https://doi.org/10.1109/ECTICON.2013.6559495","url":null,"abstract":"Performance and energy management in cloud data-center are major concerns that cloud service providers have to encounter due to computing demand has been increasing. Many researchers have proposed solutions to reduce energy consumption such as scheduling and migration while maintaining an appropriate level of performance to customers. In this paper, we propose a new CPU re-allocation algorithm that combined DVFS concept with live migration technique to improve efficiency of energy management and adaptation scheme on real-time service. The proposed algorithm works as three characteristics that are Longest Completion Time (LCT), Highest Utilization (HU) and Lowest Utilization (LU). The result shows the reduction of energy consumption and execution time upon applied characteristics and adaptation scheme.","PeriodicalId":273802,"journal":{"name":"2013 10th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126161921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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