The design of a dual modulus prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called extended true single phase clock (E-TSPC), an extension of the true single phase clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.
{"title":"A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35 /spl mu/m CMOS technology","authors":"Fernando P. H. de Miranda, J. Navarro, W. Noije","doi":"10.1145/1016568.1016598","DOIUrl":"https://doi.org/10.1145/1016568.1016598","url":null,"abstract":"The design of a dual modulus prescaler 32/33 in a 0.35 /spl mu/m CMOS technology is presented. The prescaler is a circuit employed in high frequency synthesizer designs. In the proposed circuit the technique called extended true single phase clock (E-TSPC), an extension of the true single phase clock (TSPC) technique, was applied. Additionally some new structures to double the data output rate are also employed. Simulations, based on the prescaler layout, were carried out and the results indicate that the circuit can reach up to 4 GHz with 4.38 mW of power consumption and power supply of 3.3 V.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124921543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new algorithm for technology mapping aiming at standard-cell generators is proposed. The proposed method has features that explore several AND/OR circuit decompositions by using an n-ary tree representation of the circuit. In the covering step, the cell that leads to the smaller depth increase is chosen. Depth calculation is not limited to the subject tree and takes into account all previously mapped trees representing sub-expressions used as inputs. Experimental results show gains in circuit depth measured by the number of gates in series, as well as in area measured by transistor count when compared to SIS mapping approach using the same libraries. The gain in circuit depth translates to better timing as verified by SPICE simulations.
{"title":"Advanced technology mapping for standard-cell generators","authors":"Vinícius P. Correia, A. Reis","doi":"10.1145/1016568.1016636","DOIUrl":"https://doi.org/10.1145/1016568.1016636","url":null,"abstract":"In this paper, a new algorithm for technology mapping aiming at standard-cell generators is proposed. The proposed method has features that explore several AND/OR circuit decompositions by using an n-ary tree representation of the circuit. In the covering step, the cell that leads to the smaller depth increase is chosen. Depth calculation is not limited to the subject tree and takes into account all previously mapped trees representing sub-expressions used as inputs. Experimental results show gains in circuit depth measured by the number of gates in series, as well as in area measured by transistor count when compared to SIS mapping approach using the same libraries. The gain in circuit depth translates to better timing as verified by SPICE simulations.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123222415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper deals with the problem of clock skew errors in time-interleaved analog-to-digital converters. Deterministic sample-time errors between time-interleaved channels generate nonlinear distortion and degrade SFDR. We propose a fully digital calibration method that uses, on the one hand, adaptive FIR filters to reconstruct a correctly sampled signal and, on the other hand, a new blind clock skew detection algorithm that guides the adaptive filters. This calibration method applies to any number of parallel channels in a time-interleaved architecture. Here, we show theoretical analysis and simulation results for 4 channels case. It is concluded that the calibration technique can greatly attenuate the spurs and improve the SNDR.
{"title":"Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters","authors":"D. Camarero, J. Naviner, P. Loumeau","doi":"10.1145/1016568.1016629","DOIUrl":"https://doi.org/10.1145/1016568.1016629","url":null,"abstract":"This paper deals with the problem of clock skew errors in time-interleaved analog-to-digital converters. Deterministic sample-time errors between time-interleaved channels generate nonlinear distortion and degrade SFDR. We propose a fully digital calibration method that uses, on the one hand, adaptive FIR filters to reconstruct a correctly sampled signal and, on the other hand, a new blind clock skew detection algorithm that guides the adaptive filters. This calibration method applies to any number of parallel channels in a time-interleaved architecture. Here, we show theoretical analysis and simulation results for 4 channels case. It is concluded that the calibration technique can greatly attenuate the spurs and improve the SNDR.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129975709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For the design of an embedded system, there is a variety of available processors, each one offering a different trade-off concerning factors such as performance and power consumption. High-level performance estimation of the embedded software implemented in a particular architecture is essential for a fast design space exploration, including the choice of the most appropriate processor. However, advanced architectures present many features, such as deep pipelines, branch prediction mechanisms and cache sizes, that have a non-linear impact on the execution time, which becomes hard to evaluate. In order to cope with this problem, this paper presents a neural network based approach for high-level performance estimation, which easily adapts to the non-linear behavior of the execution time in such advanced architectures. A method for automatic classification of applications is proposed, based on topological information extracted from the control flow graph of the application, enabling the utilization of domain-specific estimators and thus resulting in more accurate estimates. Practical experiments on a variety of benchmarks show estimation results with a mean error of 6.41% and a maximum error of 32%, which is more precise than previous work based on linear and non-linear approaches.
{"title":"Accurate software performance estimation using domain classification and neural networks","authors":"M. Oyamada, Felipe Zschornack, F. Wagner","doi":"10.1145/1016568.1016617","DOIUrl":"https://doi.org/10.1145/1016568.1016617","url":null,"abstract":"For the design of an embedded system, there is a variety of available processors, each one offering a different trade-off concerning factors such as performance and power consumption. High-level performance estimation of the embedded software implemented in a particular architecture is essential for a fast design space exploration, including the choice of the most appropriate processor. However, advanced architectures present many features, such as deep pipelines, branch prediction mechanisms and cache sizes, that have a non-linear impact on the execution time, which becomes hard to evaluate. In order to cope with this problem, this paper presents a neural network based approach for high-level performance estimation, which easily adapts to the non-linear behavior of the execution time in such advanced architectures. A method for automatic classification of applications is proposed, based on topological information extracted from the control flow graph of the application, enabling the utilization of domain-specific estimators and thus resulting in more accurate estimates. Practical experiments on a variety of benchmarks show estimation results with a mean error of 6.41% and a maximum error of 32%, which is more precise than previous work based on linear and non-linear approaches.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115575829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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