This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate is derived, and a representation of digital switching noise in time domain can be easily calculated through a dedicated computer program. This representation is used to perform an analog simulation using SPICE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires. Simulation results for two case studies are presented.
{"title":"An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICs","authors":"G. Trucco, G. Boselli, V. Liberali","doi":"10.1145/1016568.1016606","DOIUrl":"https://doi.org/10.1145/1016568.1016606","url":null,"abstract":"This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate is derived, and a representation of digital switching noise in time domain can be easily calculated through a dedicated computer program. This representation is used to perform an analog simulation using SPICE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires. Simulation results for two case studies are presented.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131375611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The reduction of leakage power has become an important issue for high performance designs. One way to achieve low-leakage and high performance designs is the use of multi-threshold techniques. In this paper, a new mixed-V/sub th/ (MVT) CMOS design technique is proposed, which uses different threshold voltages within a logic gate. This new technique allows the reduction of leakage power, while the performance stays constant. A set of algorithms is given assigning optimal distribution of gates. Results indicate that the new MVT approach can provide up to 40% leakage reduction by constant performance compared to dual-V/sub th/ (DVT) gate-level techniques.
{"title":"Low power gate-level design with mixed-V/sub th/ (MVT) techniques","authors":"F. Sill, F. Grassert, D. Timmermann","doi":"10.1145/1016568.1016641","DOIUrl":"https://doi.org/10.1145/1016568.1016641","url":null,"abstract":"The reduction of leakage power has become an important issue for high performance designs. One way to achieve low-leakage and high performance designs is the use of multi-threshold techniques. In this paper, a new mixed-V/sub th/ (MVT) CMOS design technique is proposed, which uses different threshold voltages within a logic gate. This new technique allows the reduction of leakage power, while the performance stays constant. A set of algorithms is given assigning optimal distribution of gates. Results indicate that the new MVT approach can provide up to 40% leakage reduction by constant performance compared to dual-V/sub th/ (DVT) gate-level techniques.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125976503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Analog BIST and SoC testing are two topics that have been extensively, but independently, studied in the last few years. However, current mixed-signals systems require the combination of these subjects to generate a cost-effective test solution for the whole SoC. This paper discusses the impact on the global system testing time of an analog BIST method based on digital reuse. Experimental results show that the reuse of digital blocks to test analog signals is indeed a very efficient strategy, even under power constraints, as long as the BIST technique reduces the analog testing time.
{"title":"Improving mixed-single SOC testing: a power-aware reuse-based approach with analog BIST","authors":"A. Andrade, É. Cota, M. Lubaszewski","doi":"10.1145/1016568.1016601","DOIUrl":"https://doi.org/10.1145/1016568.1016601","url":null,"abstract":"Analog BIST and SoC testing are two topics that have been extensively, but independently, studied in the last few years. However, current mixed-signals systems require the combination of these subjects to generate a cost-effective test solution for the whole SoC. This paper discusses the impact on the global system testing time of an analog BIST method based on digital reuse. Experimental results show that the reuse of digital blocks to test analog signals is indeed a very efficient strategy, even under power constraints, as long as the BIST technique reduces the analog testing time.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125600694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a design methodology for RF CMOS low noise amplifiers (LNA). This methodology uses a current-based MOSFET model, which allows a detailed analysis of an LNA for all MOSFET's inversion regions. Design equations, including the induced gate noise in MOS devices are also presented and a design example with simulation results is shown.
{"title":"Design of RF CMOS low noise amplifiers using a current based MOSFET model","authors":"V. Baroncini, O. C. Gouveia-Filho","doi":"10.1145/1016568.1016596","DOIUrl":"https://doi.org/10.1145/1016568.1016596","url":null,"abstract":"This paper presents a design methodology for RF CMOS low noise amplifiers (LNA). This methodology uses a current-based MOSFET model, which allows a detailed analysis of an LNA for all MOSFET's inversion regions. Design equations, including the induced gate noise in MOS devices are also presented and a design example with simulation results is shown.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127949574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wireless communication penetrates more and more areas of our everyday lives. Turbo-codes provide good forward-error correction to improve the data transfer reliability. They are used in current standards and future system designers considers them promising candidates. Dedicated hardware, however, is too expensive to use in a new and still rapidly changing system; due to the nonrecurring engineering and mask costs. In this paper, we therefore present a scalable turbo-decoder architecture targeted towards FPGA implementation for low-volume devices. It allows to optimally exploit the given hardware resources on FPGA to match the desired system throughput. Our design is ported to the Xilinx Virtex-II family. On the Virtex-II 3000, we achieve a maximum throughput of 26 Mbit/s at 84 MHz with a latency of 185 /spl mu/s.
{"title":"FPGA implementation of parallel turbo-decoders","authors":"M. Thul, N. Wehn","doi":"10.1145/1016568.1016622","DOIUrl":"https://doi.org/10.1145/1016568.1016622","url":null,"abstract":"Wireless communication penetrates more and more areas of our everyday lives. Turbo-codes provide good forward-error correction to improve the data transfer reliability. They are used in current standards and future system designers considers them promising candidates. Dedicated hardware, however, is too expensive to use in a new and still rapidly changing system; due to the nonrecurring engineering and mask costs. In this paper, we therefore present a scalable turbo-decoder architecture targeted towards FPGA implementation for low-volume devices. It allows to optimally exploit the given hardware resources on FPGA to match the desired system throughput. Our design is ported to the Xilinx Virtex-II family. On the Virtex-II 3000, we achieve a maximum throughput of 26 Mbit/s at 84 MHz with a latency of 185 /spl mu/s.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114330886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a VLSI implementation of a multi-standard channel-decoder for EDGE, WCDMA, and CDMA2k convolutional-codes is presented. The new architecture employs the MAP algorithm for convolutional decoding to support soft-outputs. The decoder is designed for base-station applications. The maximum throughput of the decoder is 16 Mbps for WCDMA and CDMA2k, and 70 Mbps for EDGE, at a clock frequency of 200 MHz.
{"title":"A multi-standard channel-decoder for base-station applications","authors":"Timo Vogt, N. Wehn, P. Alves","doi":"10.1145/1016568.1016621","DOIUrl":"https://doi.org/10.1145/1016568.1016621","url":null,"abstract":"In this paper, a VLSI implementation of a multi-standard channel-decoder for EDGE, WCDMA, and CDMA2k convolutional-codes is presented. The new architecture employs the MAP algorithm for convolutional decoding to support soft-outputs. The decoder is designed for base-station applications. The maximum throughput of the decoder is 16 Mbps for WCDMA and CDMA2k, and 70 Mbps for EDGE, at a clock frequency of 200 MHz.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133102481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The theoretical model for a mixed signal front-end interface for the SOC employing a fixed analog cell is presented in this work. The set of developed equations can be used for high level design space exploration. Moreover, the proposed architecture leads to programmable analog processing functions using digital modules, well suited to current FPGAs platforms and general purpose SOC. Some guidelines are addressed on how the proposed architecture can lead to greater level of analog design automation. Experimental results show constant performance over a large frequency range of the input signal, and validate the proposed design equations.
{"title":"Modeling and designing high performance analog reconfigurable circuits","authors":"E. Fabris, L. Carro, S. Bampi","doi":"10.1145/1016568.1016588","DOIUrl":"https://doi.org/10.1145/1016568.1016588","url":null,"abstract":"The theoretical model for a mixed signal front-end interface for the SOC employing a fixed analog cell is presented in this work. The set of developed equations can be used for high level design space exploration. Moreover, the proposed architecture leads to programmable analog processing functions using digital modules, well suited to current FPGAs platforms and general purpose SOC. Some guidelines are addressed on how the proposed architecture can lead to greater level of analog design automation. Experimental results show constant performance over a large frequency range of the input signal, and validate the proposed design equations.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129567186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Karina R. G. da Silva, E. Melcher, G. Araújo, Valdiney Alves Pimenta
The advent of new 90 nm/130 nm VLSI technology and SoC design methodologies, has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any design flow. New methods are required that allow for easier, quicker and more reusable verification. In this paper we propose an automatic verification methodology approach that enables fast, transaction-level, coverage-driven, self-checking and random-constraint functional verification. Our approach uses the systemC verification library (SCV), to synthesize a tool capable of automatically generating testbench templates. A case study from a real MP3 design is used to show the effectiveness of our approach.
{"title":"An automatic testbench generation tool for a systemC functional verification methodology","authors":"Karina R. G. da Silva, E. Melcher, G. Araújo, Valdiney Alves Pimenta","doi":"10.1145/1016568.1016592","DOIUrl":"https://doi.org/10.1145/1016568.1016592","url":null,"abstract":"The advent of new 90 nm/130 nm VLSI technology and SoC design methodologies, has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any design flow. New methods are required that allow for easier, quicker and more reusable verification. In this paper we propose an automatic verification methodology approach that enables fast, transaction-level, coverage-driven, self-checking and random-constraint functional verification. Our approach uses the systemC verification library (SCV), to synthesize a tool capable of automatically generating testbench templates. A case study from a real MP3 design is used to show the effectiveness of our approach.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126309730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fernando Cortez Sica, C. Coelho, J. Nacif, H. Foster, A. O. Fernandes
In complex system-on-a-chip (SoC) designs, designers often need to add new features into an original processor core, such as to extend the exception handling mechanism to consider exceptions in the remaining portion of the SoC design. We present in this paper a scalable architecture that can be used to add complex exception handling mechanisms in processor cores and how it can be used to extend the fixed set of exceptions found in microprocessor cores. This mechanism is based on the use of assertion libraries linked by an assertion processor to incorporate these new functionalities.
{"title":"Exception handling in microprocessors using assertion libraries","authors":"Fernando Cortez Sica, C. Coelho, J. Nacif, H. Foster, A. O. Fernandes","doi":"10.1145/1016568.1016590","DOIUrl":"https://doi.org/10.1145/1016568.1016590","url":null,"abstract":"In complex system-on-a-chip (SoC) designs, designers often need to add new features into an original processor core, such as to extend the exception handling mechanism to consider exceptions in the remaining portion of the SoC design. We present in this paper a scalable architecture that can be used to add complex exception handling mechanisms in processor cores and how it can be used to extend the fixed set of exceptions found in microprocessor cores. This mechanism is based on the use of assertion libraries linked by an assertion processor to incorporate these new functionalities.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117028380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SoC (system-on-chip) designs have introduced several new challenges for the functional verification and test disciplines. Besides the ever-growing functional complexity, we need to manage from several clock domains and low-power modes to all sorts of IP blocks like processors, complex peripherals, analog functions and different kinds of embedded memories. The reuse of 3/sup rd/ party IP may help accelerating the design of new products, but it usually does not help the functional verification and it may even add to its complexity. The same die may be used in several packages with a different number of pins and bond-out options. This presentation discusses these and other verification and test challenges. It also describes what tools, techniques and methodologies the industry is currently using to cope with them, and finalizes outlining some future directions.
SoC(片上系统)设计为功能验证和测试学科带来了几个新的挑战。除了不断增长的功能复杂性，我们需要管理从多个时钟域和低功耗模式到各种IP块，如处理器，复杂外设，模拟功能和不同类型的嵌入式存储器。3/sup / party IP的重用可能有助于加速新产品的设计，但它通常无助于功能验证，甚至可能增加其复杂性。相同的模具可用于具有不同数量引脚和粘接选项的几个封装中。本演讲将讨论这些以及其他验证和测试挑战。它还描述了行业目前使用的工具、技术和方法，并最终概述了一些未来的方向。
{"title":"Verification and test challenges in SoC designs","authors":"C.A.M. Duenas","doi":"10.1145/1016568.1016573","DOIUrl":"https://doi.org/10.1145/1016568.1016573","url":null,"abstract":"SoC (system-on-chip) designs have introduced several new challenges for the functional verification and test disciplines. Besides the ever-growing functional complexity, we need to manage from several clock domains and low-power modes to all sorts of IP blocks like processors, complex peripherals, analog functions and different kinds of embedded memories. The reuse of 3/sup rd/ party IP may help accelerating the design of new products, but it usually does not help the functional verification and it may even add to its complexity. The same die may be used in several packages with a different number of pins and bond-out options. This presentation discusses these and other verification and test challenges. It also describes what tools, techniques and methodologies the industry is currently using to cope with them, and finalizes outlining some future directions.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121556168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：