M. Ayala-Rincón, R. Jacobi, Luis Gustavo A. Carvalho, C. Llanos, R. Hartenstein
Systolic arrays provide a large amount of parallelism. However, their applicability is restricted to a small set of computational problems due to their lack of flexibility. This limitation can be circumvented by using reconfigurable systolic arrays, where the node interconnections and operations can be redefined even at run time. In this context, several alternative systolic architectures can be explored and powerful tools are needed to model and evaluate them. We show how well-known rewriting-logic environments could be used to quickly model and simulate complex application specific digital systems speeding-up its subsequent prototyping. We show how to use rewriting-logic to model and evaluate reconfigurable systolic architectures which are applied to the efficient treatment of several dynamic programming methods for resolving well-known problems such as global and local sequence alignment (Smith-Waterman algorithm), approximate string matching and computation of the longest common subsequence. A VHDL description of the conceived architecture was implemented from the rewriting-logic based abstract models and synthesized over an FPGA of the APEX family.
{"title":"Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic","authors":"M. Ayala-Rincón, R. Jacobi, Luis Gustavo A. Carvalho, C. Llanos, R. Hartenstein","doi":"10.1145/1016568.1016634","DOIUrl":"https://doi.org/10.1145/1016568.1016634","url":null,"abstract":"Systolic arrays provide a large amount of parallelism. However, their applicability is restricted to a small set of computational problems due to their lack of flexibility. This limitation can be circumvented by using reconfigurable systolic arrays, where the node interconnections and operations can be redefined even at run time. In this context, several alternative systolic architectures can be explored and powerful tools are needed to model and evaluate them. We show how well-known rewriting-logic environments could be used to quickly model and simulate complex application specific digital systems speeding-up its subsequent prototyping. We show how to use rewriting-logic to model and evaluate reconfigurable systolic architectures which are applied to the efficient treatment of several dynamic programming methods for resolving well-known problems such as global and local sequence alignment (Smith-Waterman algorithm), approximate string matching and computation of the longest common subsequence. A VHDL description of the conceived architecture was implemented from the rewriting-logic based abstract models and synthesized over an FPGA of the APEX family.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127018320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Edgar Mauricio Camacho-Galeano, C. Galup-Montoro, M. C. Schneider
This paper presents the design of an ultra-low-power self-biased 400 pA current source. An efficient design methodology has resulted in a cell area around 0.045 mm/sup 2/ (0.027 mm/sup 2/) in the AMIS 1.5 /spl mu/m (TSMC 0.35 /spl mu/m) CMOS technology and power consumption around 2 nW for 1.2 V supply. Simulated and experimental results validate the design and show that the current sources can operate at supply voltages down to 1.1 V with a good regulation (<4%/V variation of the supply voltage in a 0.35 /spl mu/m technology). This current source is suitable for very-low-power applications.
{"title":"An ultra-low-power self-biased current reference","authors":"Edgar Mauricio Camacho-Galeano, C. Galup-Montoro, M. C. Schneider","doi":"10.1145/1016568.1016611","DOIUrl":"https://doi.org/10.1145/1016568.1016611","url":null,"abstract":"This paper presents the design of an ultra-low-power self-biased 400 pA current source. An efficient design methodology has resulted in a cell area around 0.045 mm/sup 2/ (0.027 mm/sup 2/) in the AMIS 1.5 /spl mu/m (TSMC 0.35 /spl mu/m) CMOS technology and power consumption around 2 nW for 1.2 V supply. Simulated and experimental results validate the design and show that the current sources can operate at supply voltages down to 1.1 V with a good regulation (<4%/V variation of the supply voltage in a 0.35 /spl mu/m technology). This current source is suitable for very-low-power applications.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125285895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. A. Sammane, J. Schmaltz, D. Toma, P. Ostier, D. Borrione
TheoSim is a symbolic verification tool that fills the gap between the simulation of test cases, and the use of theorem provers, for the validation of initial specifications, and the exploration of the very first design steps of digital integrated systems. The principles of Theosim are presented, followed by its application to the verification of the first design step of a state-of-the-art network on chip architecture.
{"title":"TheoSim: combining symbolic simulation and theorem proving for hardware verification","authors":"G. A. Sammane, J. Schmaltz, D. Toma, P. Ostier, D. Borrione","doi":"10.1145/1016568.1016591","DOIUrl":"https://doi.org/10.1145/1016568.1016591","url":null,"abstract":"TheoSim is a symbolic verification tool that fills the gap between the simulation of test cases, and the use of theorem provers, for the validation of initial specifications, and the exploration of the very first design steps of digital integrated systems. The principles of Theosim are presented, followed by its application to the verification of the first design step of a state-of-the-art network on chip architecture.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123868444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Alexandre M. Amory, É. Cota, M. Lubaszewski, F. Moraes
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is evaluated considering the number of reused processors, the number of external interfaces, and power dissipation. Experimental results for a set of industrial examples based on the ITC'02 benchmarks show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time.
{"title":"Reducing test time with processor reuse in network-on-chip based systems","authors":"Alexandre M. Amory, É. Cota, M. Lubaszewski, F. Moraes","doi":"10.1145/1016568.1016602","DOIUrl":"https://doi.org/10.1145/1016568.1016602","url":null,"abstract":"This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores embedded into a system on chip. The resulting test time of the system is evaluated considering the number of reused processors, the number of external interfaces, and power dissipation. Experimental results for a set of industrial examples based on the ITC'02 benchmarks show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124915808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern application scenarios out of multimedia and mobile communication domains demand more and more performant data processing architectures, which cannot be achieved by using current DSP or microprocessor approaches. This contribution describes a new architecture approach out of the reconfigurable array field which offers a set of new features to increase the flexibility and usability of reconfigurable array architectures by increasing the performance benefit concurrently and decreasing the communication overhead caused by the system controller by managing the architecture. The main focus of this publication is I/O interface where the authors can discuss the concepts in detail.
{"title":"Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures","authors":"Alexander Thomas, T. Zander, J. Becker","doi":"10.1145/1016568.1016609","DOIUrl":"https://doi.org/10.1145/1016568.1016609","url":null,"abstract":"Modern application scenarios out of multimedia and mobile communication domains demand more and more performant data processing architectures, which cannot be achieved by using current DSP or microprocessor approaches. This contribution describes a new architecture approach out of the reconfigurable array field which offers a set of new features to increase the flexibility and usability of reconfigurable array architectures by increasing the performance benefit concurrently and decreasing the communication overhead caused by the system controller by managing the architecture. The main focus of this publication is I/O interface where the authors can discuss the concepts in detail.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129647854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For the rapid prototyping of mixed-signal systems in the automotive industry, tools such as MatrixX or Simulink permit the validation of control concepts. However, the physical properties of analog circuits must often be modeled. In this case, behavioral models are created and used in a real time simulation as a virtual prototype. This paper gives an overview of methods that allow us to generate analog circuit models in C++, these portions of C++ can be used as a virtual prototype. In order to achieve the necessary performance, the generation of behavioral models is combined with very fast simulation methods.
{"title":"A SystemC based case study of a sensor application using the BeCom modeling methodology for virtual prototyping","authors":"C. Meise, C. Grimm","doi":"10.1145/1016568.1016633","DOIUrl":"https://doi.org/10.1145/1016568.1016633","url":null,"abstract":"For the rapid prototyping of mixed-signal systems in the automotive industry, tools such as MatrixX or Simulink permit the validation of control concepts. However, the physical properties of analog circuits must often be modeled. In this case, behavioral models are created and used in a real time simulation as a virtual prototype. This paper gives an overview of methods that allow us to generate analog circuit models in C++, these portions of C++ can be used as a virtual prototype. In order to achieve the necessary performance, the generation of behavioral models is combined with very fast simulation methods.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128922826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The design of a 1.8V power supply, multi-frequency on-chip IC oscillator with a built-in low voltage detection (LVD) circuitry is described. Since the modules share the same bandgap cell, the system includes a new bandgap isolation strategy based on wide swing cascode current mirrors to reduce noise coupling into the LVD. The IC oscillator generates four selectable clock frequencies: 4 MHz and 8 MHz from 1.8 V to 5.5 V, 12 MHz and 22 MHz from 2.7 V to 5.5 V. After fine-tuning the oscillator via digital trimming its output frequency varies less than /spl plusmn/2.5% around the target frequency over supply ranges and from -40 to 125/spl deg/C. The measured clock jitter is below 0.1% whereas the recover time from stop is 5 /spl mu/s. The low voltage detection circuit monitors the supply voltage applied to the system and generates the appropriate warning or even initiates a system shutdown before the in-circuit SoC presents malfunction. The module was implemented in a 0.5 /spl mu/m CMOS technology, occupies an area of 360/spl times/530 /spl mu/m/sup 2/ and requires no external reference or components.
{"title":"A 1.8 V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability","authors":"A. V. Boas, J. Soldera, A. Olmos","doi":"10.1145/1016568.1016587","DOIUrl":"https://doi.org/10.1145/1016568.1016587","url":null,"abstract":"The design of a 1.8V power supply, multi-frequency on-chip IC oscillator with a built-in low voltage detection (LVD) circuitry is described. Since the modules share the same bandgap cell, the system includes a new bandgap isolation strategy based on wide swing cascode current mirrors to reduce noise coupling into the LVD. The IC oscillator generates four selectable clock frequencies: 4 MHz and 8 MHz from 1.8 V to 5.5 V, 12 MHz and 22 MHz from 2.7 V to 5.5 V. After fine-tuning the oscillator via digital trimming its output frequency varies less than /spl plusmn/2.5% around the target frequency over supply ranges and from -40 to 125/spl deg/C. The measured clock jitter is below 0.1% whereas the recover time from stop is 5 /spl mu/s. The low voltage detection circuit monitors the supply voltage applied to the system and generates the appropriate warning or even initiates a system shutdown before the in-circuit SoC presents malfunction. The module was implemented in a 0.5 /spl mu/m CMOS technology, occupies an area of 360/spl times/530 /spl mu/m/sup 2/ and requires no external reference or components.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116479212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. S. B. Nascimento, P. Maciel, M. Lima, R. E. Sant'Anna, A. Silva-Filho
The digital control systems in industry has been used in most of the applications based on expensive programmable logical controllers (PLC). These systems are, in general, highly complex and slow, with an operation cycle around 10 ms. In this work, a reconfigurable logic controller (RLC) approach is presented, based on a small and low cost Xilinx Virtex-II FPGA architecture, operating as a virtual hardware machine. In this context, the main process is specified in a formal language, based on Petri nets or SFC (sequential function chart). For applications that demand more hardware than that available in the FPGA, a partial reconfiguration mechanism takes place. From the Petri net specification, the main process is split into multiple contexts, which are sequentially executed within the same FPGA, without violating the operation cycle of application.
{"title":"A partial reconfigurable architecture for controllers based on Petri nets","authors":"P. S. B. Nascimento, P. Maciel, M. Lima, R. E. Sant'Anna, A. Silva-Filho","doi":"10.1145/1016568.1016581","DOIUrl":"https://doi.org/10.1145/1016568.1016581","url":null,"abstract":"The digital control systems in industry has been used in most of the applications based on expensive programmable logical controllers (PLC). These systems are, in general, highly complex and slow, with an operation cycle around 10 ms. In this work, a reconfigurable logic controller (RLC) approach is presented, based on a small and low cost Xilinx Virtex-II FPGA architecture, operating as a virtual hardware machine. In this context, the main process is specified in a formal language, based on Petri nets or SFC (sequential function chart). For applications that demand more hardware than that available in the FPGA, a partial reconfiguration mechanism takes place. From the Petri net specification, the main process is split into multiple contexts, which are sequentially executed within the same FPGA, without violating the operation cycle of application.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133898994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This tutorial aims to introduce circuit designers to the problems of making integrated circuits more testable. An efficient test procedure for a complex, mixed-signal application specific integrated circuit (ASIC), must take several factors into consideration: stimuli generation, sufficient access, single test output, simple measurement set and system-level decomposition. These factors worth attention for specific circuits classes, since there is no universal method valid for any kind of analog and/or mixed-signal function. Attention is paid to integrated filters and integrated analog-to-digital and digital-to-analog converters, as they are today the main analog and mixed-signal cores found in state-of-the-art complex systems-on-chips (SoC). In particular, the possibilities offered by techniques using small circuit modifications are specially focused, as the means to improve circuit testability, and thus the fault coverage, while avoiding at most to degrade the performance of the final electronic system. Practical silicon examples are presented, trying to give a flavour on the pros and cons that design for test is offering nowadays to integrated circuit designers. To meet the goals stated above, the following topics are addressed in this tutorial: introduction to mixed-signal test (main test concepts, digital vs. analog testing, test practice in integrated circuit industry, design and test inter-relations), testing approaches (fault-based, specification-based, techniques for testing filters, techniques for testing converters), and design-for-test techniques (enhancing testability, built-in self-test and on-line test). This tutorial is intended for professionals interested in analog and mixed-signal integrated circuits in general: designers interested in how to consider tests in early design phases, test engineers interested in incorporating test within the design flow, and academics involved in research and education on test procedures and strategies.
{"title":"Test and design-for-test of mixed-signal integrated circuits","authors":"J. Huertas","doi":"10.1145/1016568.1016578","DOIUrl":"https://doi.org/10.1145/1016568.1016578","url":null,"abstract":"This tutorial aims to introduce circuit designers to the problems of making integrated circuits more testable. An efficient test procedure for a complex, mixed-signal application specific integrated circuit (ASIC), must take several factors into consideration: stimuli generation, sufficient access, single test output, simple measurement set and system-level decomposition. These factors worth attention for specific circuits classes, since there is no universal method valid for any kind of analog and/or mixed-signal function. Attention is paid to integrated filters and integrated analog-to-digital and digital-to-analog converters, as they are today the main analog and mixed-signal cores found in state-of-the-art complex systems-on-chips (SoC). In particular, the possibilities offered by techniques using small circuit modifications are specially focused, as the means to improve circuit testability, and thus the fault coverage, while avoiding at most to degrade the performance of the final electronic system. Practical silicon examples are presented, trying to give a flavour on the pros and cons that design for test is offering nowadays to integrated circuit designers. To meet the goals stated above, the following topics are addressed in this tutorial: introduction to mixed-signal test (main test concepts, digital vs. analog testing, test practice in integrated circuit industry, design and test inter-relations), testing approaches (fault-based, specification-based, techniques for testing filters, techniques for testing converters), and design-for-test techniques (enhancing testability, built-in self-test and on-line test). This tutorial is intended for professionals interested in analog and mixed-signal integrated circuits in general: designers interested in how to consider tests in early design phases, test engineers interested in incorporating test within the design flow, and academics involved in research and education on test procedures and strategies.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"405 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134195207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Critical dimensions are scaling faster than our control of them. In addition to manufacturing variations, chip design has to deal with wear-out phenomena and dynamic changes in temperature or power-supply voltage. As a result, parametric delay variability is proportionately increasing with each new generation of technology, as is leakage power variability. Further, the number of independent and significant sources of variability is rapidly increasing. These effects present two key challenges: timing verification and robust design in the presence of uncertainties. This presentation describes the role of statistical timing in addressing these challenges and the concomitant shift in chip design methodology from a deterministic to a probabilistic paradigm. The importance of correctly capturing correlations is stressed. Different methods of statistical timing and their relative merits are discussed. The diagnostics provided by statistical timers and the use of such diagnostics in targeting robust design are presented.
{"title":"Statistical analysis and design: from picoseconds to probabilities","authors":"C. Visweswariah","doi":"10.1145/1016568.1016576","DOIUrl":"https://doi.org/10.1145/1016568.1016576","url":null,"abstract":"Critical dimensions are scaling faster than our control of them. In addition to manufacturing variations, chip design has to deal with wear-out phenomena and dynamic changes in temperature or power-supply voltage. As a result, parametric delay variability is proportionately increasing with each new generation of technology, as is leakage power variability. Further, the number of independent and significant sources of variability is rapidly increasing. These effects present two key challenges: timing verification and robust design in the presence of uncertainties. This presentation describes the role of statistical timing in addressing these challenges and the concomitant shift in chip design methodology from a deterministic to a probabilistic paradigm. The importance of correctly capturing correlations is stressed. Different methods of statistical timing and their relative merits are discussed. The diagnostics provided by statistical timers and the use of such diagnostics in targeting robust design are presented.","PeriodicalId":275811,"journal":{"name":"Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130823234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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