Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206176
Zhang Qihui, Chen Jianghua, Zhang Shaohui, Meng Nan
A VLSI implementation of the DCT-based JPEG encoder customized for grayscale images is presented. The JPEG encoder mainly includes FDCT, quantization, run-length encoder and entropy encoding. The two-dimensional DCT is divided into two one-dimensional DCTs because of its separability property and a pipeline technique is adopted to achieve an efficient and optimized FDCT architecture. And then an eight-stage pipelined nonrestoring divider of quantization algorithm is put forward to reach a high operating frequency, and a complete divider is processed at each 8 clock cycles when the pipeline is full. Finally, the chip layout is carried out in a 0.13 µm CMOS technology. The estimated area and power consumption of the designed encoder are 0.283 mm2 and 260 mW, respectively. The proposed encoder is 100% compatibility with the JPEG standard and can be extended to a color application.
{"title":"A VLSI implementation of pipelined JPEG encoder for grayscale images","authors":"Zhang Qihui, Chen Jianghua, Zhang Shaohui, Meng Nan","doi":"10.1109/ISSCS.2009.5206176","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206176","url":null,"abstract":"A VLSI implementation of the DCT-based JPEG encoder customized for grayscale images is presented. The JPEG encoder mainly includes FDCT, quantization, run-length encoder and entropy encoding. The two-dimensional DCT is divided into two one-dimensional DCTs because of its separability property and a pipeline technique is adopted to achieve an efficient and optimized FDCT architecture. And then an eight-stage pipelined nonrestoring divider of quantization algorithm is put forward to reach a high operating frequency, and a complete divider is processed at each 8 clock cycles when the pipeline is full. Finally, the chip layout is carried out in a 0.13 µm CMOS technology. The estimated area and power consumption of the designed encoder are 0.283 mm2 and 260 mW, respectively. The proposed encoder is 100% compatibility with the JPEG standard and can be extended to a color application.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116350318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206109
E. David, M. Zamfir
This paper presents a method for correcting digital image artifacts that appear in images acquired by digital cameras caused by flash light reflection on out of focus airborne particles. This method makes use of polar coordinates representation of artifacts and it is assumed that they were previously detected.
{"title":"Correction of image artifacts produced by airborne flash reflections","authors":"E. David, M. Zamfir","doi":"10.1109/ISSCS.2009.5206109","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206109","url":null,"abstract":"This paper presents a method for correcting digital image artifacts that appear in images acquired by digital cameras caused by flash light reflection on out of focus airborne particles. This method makes use of polar coordinates representation of artifacts and it is assumed that they were previously detected.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116500604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206159
A. Lazar, M. Florea, D. Burdia, Luminiţa-Camelia Lazăr, G. Lazar, Dan Butnicu
There are many portable devices applications implemented in System On a Chip (SOC) technology, which need to have a safety operation in extreme conditions for voltage power supplies. Due to that, a good voltage level power supply evaluation is required. This paper proposes a possible design for bandgap reference (BGR) used to generate multiple reference voltage levels for a Power-On Reset (POR) circuit. In this way, a reduced sensitivity to temperature and various process variations is achieved for the POR voltage threshold levels. The BGR circuit has been designed, simulated, and implemented. The results show that the reference voltage VREF has only a 5% variation under the temperature range from -55.DEG.C. to 125.DEG.C. The power consumption is 40uW considering a 3.3 V power supply.
{"title":"A bandgap reference circuit design for Power-on Reset related circuits","authors":"A. Lazar, M. Florea, D. Burdia, Luminiţa-Camelia Lazăr, G. Lazar, Dan Butnicu","doi":"10.1109/ISSCS.2009.5206159","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206159","url":null,"abstract":"There are many portable devices applications implemented in System On a Chip (SOC) technology, which need to have a safety operation in extreme conditions for voltage power supplies. Due to that, a good voltage level power supply evaluation is required. This paper proposes a possible design for bandgap reference (BGR) used to generate multiple reference voltage levels for a Power-On Reset (POR) circuit. In this way, a reduced sensitivity to temperature and various process variations is achieved for the POR voltage threshold levels. The BGR circuit has been designed, simulated, and implemented. The results show that the reference voltage VREF has only a 5% variation under the temperature range from -55.DEG.C. to 125.DEG.C. The power consumption is 40uW considering a 3.3 V power supply.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127626179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206088
P. Vijaya Sankara Rao, P. Mandal
In this work we propose self-termination scheme for high-speed current-mode differential signaling. This scheme eliminates the need of any dedicated passive terminator avoiding signal reflection both at the transmitter and receiver. We present fully differential, high speed transmitter/receiver(Tx/Rx) pair suitable for this self-terminated differential current-mode signaling scheme. We propose high-speed, power efficient self terminating transmitter with modified Cherry-Hooper topology. Also propose, self terminated, differential current-mode receiver realized by modified regulated gate cascode (RGC) based common-source (CS) trans-impedance amplifier (TIA) with folded active inductor peaking. The transmitter and receiver circuits are implemented in 1.8-V, 0.18-µm Digital CMOS technology with an ƒT of 27-GHz. The designed transmitter and receiver circuits, handle data rates up-to 8-Gb/s for the targeted BER of 10−12, while transmitting the data over backplane FR4 PCB trace of length 7.5-inch. The power consumed in the transmitter and receiver circuits is 10.31-mW and 10.17-mW respectively at 8-Gb/s data rate.
{"title":"Self-termination scheme for high-speed chip-to-chip data communication","authors":"P. Vijaya Sankara Rao, P. Mandal","doi":"10.1109/ISSCS.2009.5206088","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206088","url":null,"abstract":"In this work we propose self-termination scheme for high-speed current-mode differential signaling. This scheme eliminates the need of any dedicated passive terminator avoiding signal reflection both at the transmitter and receiver. We present fully differential, high speed transmitter/receiver(Tx/Rx) pair suitable for this self-terminated differential current-mode signaling scheme. We propose high-speed, power efficient self terminating transmitter with modified Cherry-Hooper topology. Also propose, self terminated, differential current-mode receiver realized by modified regulated gate cascode (RGC) based common-source (CS) trans-impedance amplifier (TIA) with folded active inductor peaking. The transmitter and receiver circuits are implemented in 1.8-V, 0.18-µm Digital CMOS technology with an ƒT of 27-GHz. The designed transmitter and receiver circuits, handle data rates up-to 8-Gb/s for the targeted BER of 10−12, while transmitting the data over backplane FR4 PCB trace of length 7.5-inch. The power consumed in the transmitter and receiver circuits is 10.31-mW and 10.17-mW respectively at 8-Gb/s data rate.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126337382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206193
Angeliki Leonida, Orhan Hazar Mutgan, A. Rusu
This paper presents a digitally calibrated Continuous Time Quadrature ΣΔ ADC for WiMAX/LTE narrow bands. The proposed architecture employs a 5th order 2-bit quadrature bandpass ΣΔ modulator. Dithering and Adaptive Line Enhancement techniques are combined to compensate for mismatch errors in the I/Q paths. The proposed calibration technique introduces no complexity in the ADC design and can be used online. The simulation results show an improvement of 16.75dB in SINAD and 34.42dB in Image Rejection, when a ±30% variation in the loop active RC filter coefficients is introduced in the behavioral model.
{"title":"A digitally calibrated CT quadrature bandpass ΣΔ ADC for Wimax/LTE","authors":"Angeliki Leonida, Orhan Hazar Mutgan, A. Rusu","doi":"10.1109/ISSCS.2009.5206193","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206193","url":null,"abstract":"This paper presents a digitally calibrated Continuous Time Quadrature ΣΔ ADC for WiMAX/LTE narrow bands. The proposed architecture employs a 5th order 2-bit quadrature bandpass ΣΔ modulator. Dithering and Adaptive Line Enhancement techniques are combined to compensate for mismatch errors in the I/Q paths. The proposed calibration technique introduces no complexity in the ADC design and can be used online. The simulation results show an improvement of 16.75dB in SINAD and 34.42dB in Image Rejection, when a ±30% variation in the loop active RC filter coefficients is introduced in the behavioral model.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128133254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206215
Ioana Firoiu, A. Isar, J. Boucher
The success of wavelet techniques in many fields of signal and image processing was proved to be highly influenced by the properties of the wavelet transform used, mainly the shift-invariance and the directional selectivity. In the present paper we propose an improved version of the inverse Hyperanalytic Wavelet Transform (HWT), which uses hyperanalytic mother wavelets. We have already proposed implementations of the HWT and of its inverse (IHWT). The implementation supposes the computation of the discrete wavelet transform (DWT) of the hyperanalytic signal associated to the input signal. Our old computation method of the IHWT extracts the real part of the signal at the output of the inverse discrete wavelet transform (IDWT). The aim of this paper is a new implementation of the IHWT, which permits a better shift invariance. We will compare this implementation with our previous one, with the DWT and with Kingsbury's Double-Tree Complex Wavelet Transform (DT CWT).
{"title":"An improved version of the inverse Hyperanalytic Wavelet Transform","authors":"Ioana Firoiu, A. Isar, J. Boucher","doi":"10.1109/ISSCS.2009.5206215","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206215","url":null,"abstract":"The success of wavelet techniques in many fields of signal and image processing was proved to be highly influenced by the properties of the wavelet transform used, mainly the shift-invariance and the directional selectivity. In the present paper we propose an improved version of the inverse Hyperanalytic Wavelet Transform (HWT), which uses hyperanalytic mother wavelets. We have already proposed implementations of the HWT and of its inverse (IHWT). The implementation supposes the computation of the discrete wavelet transform (DWT) of the hyperanalytic signal associated to the input signal. Our old computation method of the IHWT extracts the real part of the signal at the output of the inverse discrete wavelet transform (IDWT). The aim of this paper is a new implementation of the IHWT, which permits a better shift invariance. We will compare this implementation with our previous one, with the DWT and with Kingsbury's Double-Tree Complex Wavelet Transform (DT CWT).","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"10 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132609847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206093
A. Cristian, Cacoveanu Remus
The paper presents briefly the OBSAI RP3-01 interface existing between the Remote Radio Unit (RRU) and the Baseband module (BBM) of a Base Station (BS) with a split architecture. It describes a layer based implementation model for BS split architecture with MIMO capabilities and it presents some implementation results obtained when targeting the XC4VFX60 device. The interface features are suitable for spatial diversity and spatial multiplexing schemes and redundancy support.
{"title":"BS split architecture with MIMO capabilities support based on OBSAI RP3-01 interface","authors":"A. Cristian, Cacoveanu Remus","doi":"10.1109/ISSCS.2009.5206093","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206093","url":null,"abstract":"The paper presents briefly the OBSAI RP3-01 interface existing between the Remote Radio Unit (RRU) and the Baseband module (BBM) of a Base Station (BS) with a split architecture. It describes a layer based implementation model for BS split architecture with MIMO capabilities and it presents some implementation results obtained when targeting the XC4VFX60 device. The interface features are suitable for spatial diversity and spatial multiplexing schemes and redundancy support.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128941272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206152
B. S. Mereuta, M. Lucanu, C.V. Pavel
The paper presents a three-phase SVPWM inverter that works at zero voltage transition on switches in the moment of commutation. The relations used to calculate every state time and quasi-resonant circuit topology are given. The results got after inverter's simulation in Simulink are shown below.
{"title":"A ZVS circuit used in a three-phase SVPWM inverter","authors":"B. S. Mereuta, M. Lucanu, C.V. Pavel","doi":"10.1109/ISSCS.2009.5206152","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206152","url":null,"abstract":"The paper presents a three-phase SVPWM inverter that works at zero voltage transition on switches in the moment of commutation. The relations used to calculate every state time and quasi-resonant circuit topology are given. The results got after inverter's simulation in Simulink are shown below.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130757127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206081
Andrei-George Oprina, E. Simion, Gheorghe Simion
In this paper we describe a contrario detection method used in image processing in order to identify new objects which apper in digital images. The principle of a contrario detection is to first define an a priori model for the generic case when there is nothing to detect. Detection will only take place when the number of occurrences of such an event in the a priori model is low.
{"title":"Computer vision principles. A contrario method","authors":"Andrei-George Oprina, E. Simion, Gheorghe Simion","doi":"10.1109/ISSCS.2009.5206081","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206081","url":null,"abstract":"In this paper we describe a contrario detection method used in image processing in order to identify new objects which apper in digital images. The principle of a contrario detection is to first define an a priori model for the generic case when there is nothing to detect. Detection will only take place when the number of occurrences of such an event in the a priori model is low.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133436419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206166
Lawrence Leinweber, F. Wolff, C. Papachristou, F. Merat
We propose a protocol that minimizes the cryptographic effort on an RFID tag without requiring a backend database record for each tag. The protocol allows a tag to identify itself only to its owner. When a product is sold, the tag ownership is changed in a secure way. Security is based on public key cryptography, which is becoming economically practical for RFID tags. With this protocol, tag owners need not share secrets with each other or any central database and therefore privacy will be provided by technology, which is inherently more robust than public policy.
{"title":"A minimal protocol with public key cryptography for identification and privacy in RFID tags","authors":"Lawrence Leinweber, F. Wolff, C. Papachristou, F. Merat","doi":"10.1109/ISSCS.2009.5206166","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206166","url":null,"abstract":"We propose a protocol that minimizes the cryptographic effort on an RFID tag without requiring a backend database record for each tag. The protocol allows a tag to identify itself only to its owner. When a product is sold, the tag ownership is changed in a secure way. Security is based on public key cryptography, which is becoming economically practical for RFID tags. With this protocol, tag owners need not share secrets with each other or any central database and therefore privacy will be provided by technology, which is inherently more robust than public policy.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131675298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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